| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000062 # Number of seconds simulated 4sim_ticks 62213000 # Number of ticks simulated 5final_tick 62213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000065 # Number of seconds simulated 4sim_ticks 64758000 # Number of ticks simulated 5final_tick 64758000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 276862 # Simulator instruction rate (inst/s) 8host_op_rate 276760 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2667377590 # Simulator tick rate (ticks/s) 10host_mem_usage 639424 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host | 7host_inst_rate 560678 # Simulator instruction rate (inst/s) 8host_op_rate 559951 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5612828222 # Simulator tick rate (ticks/s) 10host_mem_usage 638096 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host |
| 12sim_insts 6453 # Number of instructions simulated 13sim_ops 6453 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 6453 # Number of instructions simulated 13sim_ops 6453 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states | 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
| 17system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory | 17system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory |
| 25system.mem_ctrl.bw_read::cpu.inst 285985244 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 172825615 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 458810859 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 285985244 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 285985244 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 285985244 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 172825615 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 458810859 # Total bandwidth to/from this memory (bytes/s) | 25system.mem_ctrl.bw_read::cpu.inst 274745977 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 166033540 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 440779518 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 274745977 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 274745977 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 274745977 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 166033540 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 440779518 # Total bandwidth to/from this memory (bytes/s) |
| 33system.mem_ctrl.readReqs 446 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry | 33system.mem_ctrl.readReqs 446 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.mem_ctrl.totGap 61962000 # Total gap between requests | 79system.mem_ctrl.totGap 64501000 # Total gap between requests |
| 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see | 80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 185.768755 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 255.860208 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 22 23.16% 23.16% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 36 37.89% 61.05% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 14 14.74% 75.79% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 5 5.26% 81.05% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation 203system.mem_ctrl.totQLat 3590750 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 11953250 # Total ticks spent from burst creation until serviced by the DRAM | 190system.mem_ctrl.bytesPerActivate::samples 105 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 264.533333 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 181.831163 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 249.307389 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 27 25.71% 25.71% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 40 38.10% 63.81% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 10 9.52% 73.33% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 9 8.57% 81.90% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 7 6.67% 88.57% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 6 5.71% 94.29% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 1 0.95% 95.24% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 105 # Bytes accessed per row activation 203system.mem_ctrl.totQLat 6134000 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 14496500 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers | 205system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers |
| 206system.mem_ctrl.avgQLat 8051.01 # Average queueing delay per DRAM burst | 206system.mem_ctrl.avgQLat 13753.36 # Average queueing delay per DRAM burst |
| 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.mem_ctrl.avgMemAccLat 26801.01 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 458.81 # Average DRAM read bandwidth in MiByte/s | 208system.mem_ctrl.avgMemAccLat 32503.36 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 440.78 # Average DRAM read bandwidth in MiByte/s |
| 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.mem_ctrl.avgRdBWSys 458.81 # Average system read bandwidth in MiByte/s | 211system.mem_ctrl.avgRdBWSys 440.78 # Average system read bandwidth in MiByte/s |
| 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 214system.mem_ctrl.busUtil 3.58 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.58 # Data bus utilization in percentage for reads | 214system.mem_ctrl.busUtil 3.44 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.44 # Data bus utilization in percentage for reads |
| 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing | 216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads | 219system.mem_ctrl.readRowHits 337 # Number of row buffer hits during reads |
| 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes | 220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads | 221system.mem_ctrl.readRowHitRate 75.56 # Row buffer hit rate for reads |
| 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes | 222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.mem_ctrl.avgGap 138928.25 # Average gap between requests 224system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 227system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ) | 223system.mem_ctrl.avgGap 144621.08 # Average gap between requests 224system.mem_ctrl.pageHitRate 75.56 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 314160 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 163185 # Energy for precharge commands per rank (pJ) 227system.mem_ctrl_0.readEnergy 1542240 # Energy for read commands per rank (pJ) |
| 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 229system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 230system.mem_ctrl_0.actBackEnergy 37021500 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 383250 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.totalEnergy 43027155 # Total energy per rank (pJ) 233system.mem_ctrl_0.averagePower 785.686791 # Core power per rank (mW) 234system.mem_ctrl_0.memoryStateTime::IDLE 966000 # Time in different power states 235system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states 236system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.mem_ctrl_0.memoryStateTime::ACT 52514000 # Time in different power states 238system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.mem_ctrl_1.actEnergy 370440 # Energy for activate commands per rank (pJ) 240system.mem_ctrl_1.preEnergy 202125 # Energy for precharge commands per rank (pJ) 241system.mem_ctrl_1.readEnergy 1466400 # Energy for read commands per rank (pJ) | 229system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) 230system.mem_ctrl_0.actBackEnergy 3812160 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 131040 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.actPowerDownEnergy 22575420 # Energy for active power-down per rank (pJ) 233system.mem_ctrl_0.prePowerDownEnergy 2515200 # Energy for precharge power-down per rank (pJ) 234system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 235system.mem_ctrl_0.totalEnergy 35970525 # Total energy per rank (pJ) 236system.mem_ctrl_0.averagePower 555.454282 # Core power per rank (mW) 237system.mem_ctrl_0.totalIdleTime 55623250 # Total Idle time Per DRAM Rank 238system.mem_ctrl_0.memoryStateTime::IDLE 77000 # Time in different power states 239system.mem_ctrl_0.memoryStateTime::REF 2080000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states 241system.mem_ctrl_0.memoryStateTime::PRE_PDN 6549500 # Time in different power states 242system.mem_ctrl_0.memoryStateTime::ACT 6531250 # Time in different power states 243system.mem_ctrl_0.memoryStateTime::ACT_PDN 49520250 # Time in different power states 244system.mem_ctrl_1.actEnergy 464100 # Energy for activate commands per rank (pJ) 245system.mem_ctrl_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) 246system.mem_ctrl_1.readEnergy 1642200 # Energy for read commands per rank (pJ) |
| 242system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 247system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 243system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 244system.mem_ctrl_1.actBackEnergy 35989515 # Energy for active background per rank (pJ) 245system.mem_ctrl_1.preBackEnergy 1288500 # Energy for precharge background per rank (pJ) 246system.mem_ctrl_1.totalEnergy 42876900 # Total energy per rank (pJ) 247system.mem_ctrl_1.averagePower 782.943096 # Core power per rank (mW) 248system.mem_ctrl_1.memoryStateTime::IDLE 1815750 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT 51141750 # Time in different power states 252system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states | 248system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) 249system.mem_ctrl_1.actBackEnergy 4174680 # Energy for active background per rank (pJ) 250system.mem_ctrl_1.preBackEnergy 251520 # Energy for precharge background per rank (pJ) 251system.mem_ctrl_1.actPowerDownEnergy 24338430 # Energy for active power-down per rank (pJ) 252system.mem_ctrl_1.prePowerDownEnergy 604800 # Energy for precharge power-down per rank (pJ) 253system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 254system.mem_ctrl_1.totalEnergy 36628140 # Total energy per rank (pJ) 255system.mem_ctrl_1.averagePower 565.609126 # Core power per rank (mW) 256system.mem_ctrl_1.totalIdleTime 54728750 # Total Idle time Per DRAM Rank 257system.mem_ctrl_1.memoryStateTime::IDLE 283000 # Time in different power states 258system.mem_ctrl_1.memoryStateTime::REF 2080000 # Time in different power states 259system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states 260system.mem_ctrl_1.memoryStateTime::PRE_PDN 1573250 # Time in different power states 261system.mem_ctrl_1.memoryStateTime::ACT 7457000 # Time in different power states 262system.mem_ctrl_1.memoryStateTime::ACT_PDN 53364750 # Time in different power states 263system.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
| 254system.cpu.dtb.fetch_hits 0 # ITB hits 255system.cpu.dtb.fetch_misses 0 # ITB misses 256system.cpu.dtb.fetch_acv 0 # ITB acv 257system.cpu.dtb.fetch_accesses 0 # ITB accesses 258system.cpu.dtb.read_hits 1190 # DTB read hits 259system.cpu.dtb.read_misses 7 # DTB read misses 260system.cpu.dtb.read_acv 0 # DTB read access violations 261system.cpu.dtb.read_accesses 1197 # DTB read accesses --- 17 unchanged lines hidden (view full) --- 279system.cpu.itb.write_misses 0 # DTB write misses 280system.cpu.itb.write_acv 0 # DTB write access violations 281system.cpu.itb.write_accesses 0 # DTB write accesses 282system.cpu.itb.data_hits 0 # DTB hits 283system.cpu.itb.data_misses 0 # DTB misses 284system.cpu.itb.data_acv 0 # DTB access violations 285system.cpu.itb.data_accesses 0 # DTB accesses 286system.cpu.workload.num_syscalls 17 # Number of system calls | 264system.cpu.dtb.fetch_hits 0 # ITB hits 265system.cpu.dtb.fetch_misses 0 # ITB misses 266system.cpu.dtb.fetch_acv 0 # ITB acv 267system.cpu.dtb.fetch_accesses 0 # ITB accesses 268system.cpu.dtb.read_hits 1190 # DTB read hits 269system.cpu.dtb.read_misses 7 # DTB read misses 270system.cpu.dtb.read_acv 0 # DTB read access violations 271system.cpu.dtb.read_accesses 1197 # DTB read accesses --- 17 unchanged lines hidden (view full) --- 289system.cpu.itb.write_misses 0 # DTB write misses 290system.cpu.itb.write_acv 0 # DTB write access violations 291system.cpu.itb.write_accesses 0 # DTB write accesses 292system.cpu.itb.data_hits 0 # DTB hits 293system.cpu.itb.data_misses 0 # DTB misses 294system.cpu.itb.data_acv 0 # DTB access violations 295system.cpu.itb.data_accesses 0 # DTB accesses 296system.cpu.workload.num_syscalls 17 # Number of system calls |
| 287system.cpu.pwrStateResidencyTicks::ON 62213000 # Cumulative time (in ticks) in various power states 288system.cpu.numCycles 62213 # number of cpu cycles simulated | 297system.cpu.pwrStateResidencyTicks::ON 64758000 # Cumulative time (in ticks) in various power states 298system.cpu.numCycles 64758 # number of cpu cycles simulated |
| 289system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 290system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 291system.cpu.committedInsts 6453 # Number of instructions committed 292system.cpu.committedOps 6453 # Number of ops (including micro ops) committed 293system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses 294system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 295system.cpu.num_func_calls 251 # number of times a function call or return occured 296system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls 297system.cpu.num_int_insts 6380 # number of integer instructions 298system.cpu.num_fp_insts 10 # number of float instructions 299system.cpu.num_int_register_reads 8392 # number of times the integer registers were read 300system.cpu.num_int_register_writes 4621 # number of times the integer registers were written 301system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 302system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 303system.cpu.num_mem_refs 2065 # number of memory refs 304system.cpu.num_load_insts 1197 # Number of load instructions 305system.cpu.num_store_insts 868 # Number of store instructions 306system.cpu.num_idle_cycles 0 # Number of idle cycles | 299system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 300system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 301system.cpu.committedInsts 6453 # Number of instructions committed 302system.cpu.committedOps 6453 # Number of ops (including micro ops) committed 303system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses 304system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 305system.cpu.num_func_calls 251 # number of times a function call or return occured 306system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls 307system.cpu.num_int_insts 6380 # number of integer instructions 308system.cpu.num_fp_insts 10 # number of float instructions 309system.cpu.num_int_register_reads 8392 # number of times the integer registers were read 310system.cpu.num_int_register_writes 4621 # number of times the integer registers were written 311system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 312system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 313system.cpu.num_mem_refs 2065 # number of memory refs 314system.cpu.num_load_insts 1197 # Number of load instructions 315system.cpu.num_store_insts 868 # Number of store instructions 316system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 307system.cpu.num_busy_cycles 62213 # Number of busy cycles | 317system.cpu.num_busy_cycles 64758 # Number of busy cycles |
| 308system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 309system.cpu.idle_fraction 0 # Percentage of idle cycles 310system.cpu.Branches 1060 # Number of branches fetched 311system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction 312system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction 313system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction 314system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction 315system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 338system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction 339system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction 340system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction 341system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction 342system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction 343system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 344system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 345system.cpu.op_class::total 6463 # Class of executed instruction | 318system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 319system.cpu.idle_fraction 0 # Percentage of idle cycles 320system.cpu.Branches 1060 # Number of branches fetched 321system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction 322system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction 323system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction 324system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction 325system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 348system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction 349system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction 350system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction 351system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction 352system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction 353system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 354system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 355system.cpu.op_class::total 6463 # Class of executed instruction |
| 346system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states | 356system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
| 347system.cpu.dcache.tags.replacements 0 # number of replacements | 357system.cpu.dcache.tags.replacements 0 # number of replacements |
| 348system.cpu.dcache.tags.tagsinuse 104.646393 # Cycle average of tags in use | 358system.cpu.dcache.tags.tagsinuse 104.399751 # Cycle average of tags in use |
| 349system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. 350system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 351system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. 352system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 359system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. 360system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 361system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. 362system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 353system.cpu.dcache.tags.occ_blocks::cpu.data 104.646393 # Average occupied blocks per requestor 354system.cpu.dcache.tags.occ_percent::cpu.data 0.102194 # Average percentage of cache occupancy 355system.cpu.dcache.tags.occ_percent::total 0.102194 # Average percentage of cache occupancy | 363system.cpu.dcache.tags.occ_blocks::cpu.data 104.399751 # Average occupied blocks per requestor 364system.cpu.dcache.tags.occ_percent::cpu.data 0.101953 # Average percentage of cache occupancy 365system.cpu.dcache.tags.occ_percent::total 0.101953 # Average percentage of cache occupancy |
| 356system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 357system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 358system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 359system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id 360system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses 361system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses | 366system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 367system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 368system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 369system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id 370system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses 371system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses |
| 362system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states | 372system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
| 363system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits 364system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits 365system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 366system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 367system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits 368system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits 369system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits 370system.cpu.dcache.overall_hits::total 1887 # number of overall hits 371system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 372system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 373system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 374system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 375system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 376system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 377system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 378system.cpu.dcache.overall_misses::total 168 # number of overall misses | 373system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits 374system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits 375system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 376system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 377system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits 378system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits 379system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits 380system.cpu.dcache.overall_hits::total 1887 # number of overall hits 381system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 382system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 383system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 384system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 385system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 386system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 387system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 388system.cpu.dcache.overall_misses::total 168 # number of overall misses |
| 379system.cpu.dcache.ReadReq_miss_latency::cpu.data 9887000 # number of ReadReq miss cycles 380system.cpu.dcache.ReadReq_miss_latency::total 9887000 # number of ReadReq miss cycles 381system.cpu.dcache.WriteReq_miss_latency::cpu.data 7630000 # number of WriteReq miss cycles 382system.cpu.dcache.WriteReq_miss_latency::total 7630000 # number of WriteReq miss cycles 383system.cpu.dcache.demand_miss_latency::cpu.data 17517000 # number of demand (read+write) miss cycles 384system.cpu.dcache.demand_miss_latency::total 17517000 # number of demand (read+write) miss cycles 385system.cpu.dcache.overall_miss_latency::cpu.data 17517000 # number of overall miss cycles 386system.cpu.dcache.overall_miss_latency::total 17517000 # number of overall miss cycles | 389system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261000 # number of ReadReq miss cycles 390system.cpu.dcache.ReadReq_miss_latency::total 10261000 # number of ReadReq miss cycles 391system.cpu.dcache.WriteReq_miss_latency::cpu.data 7802000 # number of WriteReq miss cycles 392system.cpu.dcache.WriteReq_miss_latency::total 7802000 # number of WriteReq miss cycles 393system.cpu.dcache.demand_miss_latency::cpu.data 18063000 # number of demand (read+write) miss cycles 394system.cpu.dcache.demand_miss_latency::total 18063000 # number of demand (read+write) miss cycles 395system.cpu.dcache.overall_miss_latency::cpu.data 18063000 # number of overall miss cycles 396system.cpu.dcache.overall_miss_latency::total 18063000 # number of overall miss cycles |
| 387system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) 388system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) 389system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 390system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 391system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses 392system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses 393system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses 394system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses 395system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses 396system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses 397system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 398system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 399system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses 400system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses 401system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses 402system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses | 397system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) 398system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) 399system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 400system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 401system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses 402system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses 403system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses 404system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses 405system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses 406system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses 407system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 408system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 409system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses 410system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses 411system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses 412system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses |
| 403system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 104073.684211 # average ReadReq miss latency 404system.cpu.dcache.ReadReq_avg_miss_latency::total 104073.684211 # average ReadReq miss latency 405system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104520.547945 # average WriteReq miss latency 406system.cpu.dcache.WriteReq_avg_miss_latency::total 104520.547945 # average WriteReq miss latency 407system.cpu.dcache.demand_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency 408system.cpu.dcache.demand_avg_miss_latency::total 104267.857143 # average overall miss latency 409system.cpu.dcache.overall_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency 410system.cpu.dcache.overall_avg_miss_latency::total 104267.857143 # average overall miss latency | 413system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316 # average ReadReq miss latency 414system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316 # average ReadReq miss latency 415system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329 # average WriteReq miss latency 416system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329 # average WriteReq miss latency 417system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency 418system.cpu.dcache.demand_avg_miss_latency::total 107517.857143 # average overall miss latency 419system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency 420system.cpu.dcache.overall_avg_miss_latency::total 107517.857143 # average overall miss latency |
| 411system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 412system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 413system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 415system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 416system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 417system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 418system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 419system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 420system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 421system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 422system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 423system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 424system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses | 421system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 422system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 423system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 424system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 425system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 426system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 427system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 428system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 429system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 430system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 431system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 432system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 433system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 434system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses |
| 425system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9697000 # number of ReadReq MSHR miss cycles 426system.cpu.dcache.ReadReq_mshr_miss_latency::total 9697000 # number of ReadReq MSHR miss cycles 427system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7484000 # number of WriteReq MSHR miss cycles 428system.cpu.dcache.WriteReq_mshr_miss_latency::total 7484000 # number of WriteReq MSHR miss cycles 429system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17181000 # number of demand (read+write) MSHR miss cycles 430system.cpu.dcache.demand_mshr_miss_latency::total 17181000 # number of demand (read+write) MSHR miss cycles 431system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17181000 # number of overall MSHR miss cycles 432system.cpu.dcache.overall_mshr_miss_latency::total 17181000 # number of overall MSHR miss cycles | 435system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10071000 # number of ReadReq MSHR miss cycles 436system.cpu.dcache.ReadReq_mshr_miss_latency::total 10071000 # number of ReadReq MSHR miss cycles 437system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7656000 # number of WriteReq MSHR miss cycles 438system.cpu.dcache.WriteReq_mshr_miss_latency::total 7656000 # number of WriteReq MSHR miss cycles 439system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17727000 # number of demand (read+write) MSHR miss cycles 440system.cpu.dcache.demand_mshr_miss_latency::total 17727000 # number of demand (read+write) MSHR miss cycles 441system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17727000 # number of overall MSHR miss cycles 442system.cpu.dcache.overall_mshr_miss_latency::total 17727000 # number of overall MSHR miss cycles |
| 433system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses 434system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses 435system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 436system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 437system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses 438system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses 439system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses 440system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses | 443system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses 444system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses 445system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 446system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 447system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses 448system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses 449system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses 450system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses |
| 441system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 102073.684211 # average ReadReq mshr miss latency 442system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 102073.684211 # average ReadReq mshr miss latency 443system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102520.547945 # average WriteReq mshr miss latency 444system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102520.547945 # average WriteReq mshr miss latency 445system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency 446system.cpu.dcache.demand_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency 447system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency 448system.cpu.dcache.overall_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency 449system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states | 451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316 # average ReadReq mshr miss latency 452system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316 # average ReadReq mshr miss latency 453system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329 # average WriteReq mshr miss latency 454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329 # average WriteReq mshr miss latency 455system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency 456system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency 457system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency 458system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency 459system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
| 450system.cpu.icache.tags.replacements 62 # number of replacements | 460system.cpu.icache.tags.replacements 62 # number of replacements |
| 451system.cpu.icache.tags.tagsinuse 113.718871 # Cycle average of tags in use | 461system.cpu.icache.tags.tagsinuse 113.445692 # Cycle average of tags in use |
| 452system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 453system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 454system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 455system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 462system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 463system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 464system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 465system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 456system.cpu.icache.tags.occ_blocks::cpu.inst 113.718871 # Average occupied blocks per requestor 457system.cpu.icache.tags.occ_percent::cpu.inst 0.444214 # Average percentage of cache occupancy 458system.cpu.icache.tags.occ_percent::total 0.444214 # Average percentage of cache occupancy | 466system.cpu.icache.tags.occ_blocks::cpu.inst 113.445692 # Average occupied blocks per requestor 467system.cpu.icache.tags.occ_percent::cpu.inst 0.443147 # Average percentage of cache occupancy 468system.cpu.icache.tags.occ_percent::total 0.443147 # Average percentage of cache occupancy |
| 459system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id 460system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 461system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 462system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id 463system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses 464system.cpu.icache.tags.data_accesses 13209 # Number of data accesses | 469system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id 470system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 471system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 472system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id 473system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses 474system.cpu.icache.tags.data_accesses 13209 # Number of data accesses |
| 465system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states | 475system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
| 466system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits 467system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits 468system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits 469system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits 470system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits 471system.cpu.icache.overall_hits::total 6183 # number of overall hits 472system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses 473system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses 474system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses 475system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses 476system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses 477system.cpu.icache.overall_misses::total 281 # number of overall misses | 476system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits 477system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits 478system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits 479system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits 480system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits 481system.cpu.icache.overall_hits::total 6183 # number of overall hits 482system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses 483system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses 484system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses 485system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses 486system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses 487system.cpu.icache.overall_misses::total 281 # number of overall misses |
| 478system.cpu.icache.ReadReq_miss_latency::cpu.inst 28558000 # number of ReadReq miss cycles 479system.cpu.icache.ReadReq_miss_latency::total 28558000 # number of ReadReq miss cycles 480system.cpu.icache.demand_miss_latency::cpu.inst 28558000 # number of demand (read+write) miss cycles 481system.cpu.icache.demand_miss_latency::total 28558000 # number of demand (read+write) miss cycles 482system.cpu.icache.overall_miss_latency::cpu.inst 28558000 # number of overall miss cycles 483system.cpu.icache.overall_miss_latency::total 28558000 # number of overall miss cycles | 488system.cpu.icache.ReadReq_miss_latency::cpu.inst 30557000 # number of ReadReq miss cycles 489system.cpu.icache.ReadReq_miss_latency::total 30557000 # number of ReadReq miss cycles 490system.cpu.icache.demand_miss_latency::cpu.inst 30557000 # number of demand (read+write) miss cycles 491system.cpu.icache.demand_miss_latency::total 30557000 # number of demand (read+write) miss cycles 492system.cpu.icache.overall_miss_latency::cpu.inst 30557000 # number of overall miss cycles 493system.cpu.icache.overall_miss_latency::total 30557000 # number of overall miss cycles |
| 484system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) 485system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) 486system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses 487system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses 488system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses 489system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses 490system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses 491system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses 492system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses 493system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses 494system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses 495system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses | 494system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) 495system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) 496system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses 497system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses 498system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses 499system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses 500system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses 501system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses 502system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses 503system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses 504system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses 505system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses |
| 496system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101629.893238 # average ReadReq miss latency 497system.cpu.icache.ReadReq_avg_miss_latency::total 101629.893238 # average ReadReq miss latency 498system.cpu.icache.demand_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency 499system.cpu.icache.demand_avg_miss_latency::total 101629.893238 # average overall miss latency 500system.cpu.icache.overall_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency 501system.cpu.icache.overall_avg_miss_latency::total 101629.893238 # average overall miss latency | 506system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242 # average ReadReq miss latency 507system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242 # average ReadReq miss latency 508system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency 509system.cpu.icache.demand_avg_miss_latency::total 108743.772242 # average overall miss latency 510system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency 511system.cpu.icache.overall_avg_miss_latency::total 108743.772242 # average overall miss latency |
| 502system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 503system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 504system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 505system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 506system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 507system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 508system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses 509system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses 510system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses 511system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses 512system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses 513system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses | 512system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 513system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 514system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 515system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 516system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 517system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 518system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses 519system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses 520system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses 521system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses 522system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses 523system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses |
| 514system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27996000 # number of ReadReq MSHR miss cycles 515system.cpu.icache.ReadReq_mshr_miss_latency::total 27996000 # number of ReadReq MSHR miss cycles 516system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27996000 # number of demand (read+write) MSHR miss cycles 517system.cpu.icache.demand_mshr_miss_latency::total 27996000 # number of demand (read+write) MSHR miss cycles 518system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27996000 # number of overall MSHR miss cycles 519system.cpu.icache.overall_mshr_miss_latency::total 27996000 # number of overall MSHR miss cycles | 524system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29995000 # number of ReadReq MSHR miss cycles 525system.cpu.icache.ReadReq_mshr_miss_latency::total 29995000 # number of ReadReq MSHR miss cycles 526system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29995000 # number of demand (read+write) MSHR miss cycles 527system.cpu.icache.demand_mshr_miss_latency::total 29995000 # number of demand (read+write) MSHR miss cycles 528system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29995000 # number of overall MSHR miss cycles 529system.cpu.icache.overall_mshr_miss_latency::total 29995000 # number of overall MSHR miss cycles |
| 520system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses 521system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses 522system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses 523system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses 524system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses 525system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses | 530system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses 531system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses 532system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses 533system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses 534system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses 535system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses |
| 526system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99629.893238 # average ReadReq mshr miss latency 527system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99629.893238 # average ReadReq mshr miss latency 528system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency 529system.cpu.icache.demand_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency 530system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency 531system.cpu.icache.overall_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency | 536system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242 # average ReadReq mshr miss latency 537system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242 # average ReadReq mshr miss latency 538system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency 539system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency 540system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency 541system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency |
| 532system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 533system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 534system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 535system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 536system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 537system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 542system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 543system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 544system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 545system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 546system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 547system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 538system.l2bus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states | 548system.l2bus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
| 539system.l2bus.trans_dist::ReadResp 376 # Transaction distribution 540system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution 541system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution 542system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution 543system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution 544system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) 545system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 546system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 558system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 559system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 560system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 561system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 562system.l2bus.snoop_fanout::total 449 # Request fanout histogram 563system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) 564system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 565system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) | 549system.l2bus.trans_dist::ReadResp 376 # Transaction distribution 550system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution 551system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution 552system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution 553system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution 554system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) 555system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 556system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 568system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 569system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 570system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 571system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 572system.l2bus.snoop_fanout::total 449 # Request fanout histogram 573system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) 574system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 575system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) |
| 566system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) | 576system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) |
| 567system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) 568system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) | 577system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) 578system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| 569system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states | 579system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
| 570system.l2cache.tags.replacements 0 # number of replacements | 580system.l2cache.tags.replacements 0 # number of replacements |
| 571system.l2cache.tags.tagsinuse 233.175851 # Cycle average of tags in use | 581system.l2cache.tags.tagsinuse 232.606847 # Cycle average of tags in use |
| 572system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. 573system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. 574system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. 575system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 582system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. 583system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. 584system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. 585system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 576system.l2cache.tags.occ_blocks::cpu.inst 128.472749 # Average occupied blocks per requestor 577system.l2cache.tags.occ_blocks::cpu.data 104.703102 # Average occupied blocks per requestor 578system.l2cache.tags.occ_percent::cpu.inst 0.031365 # Average percentage of cache occupancy 579system.l2cache.tags.occ_percent::cpu.data 0.025562 # Average percentage of cache occupancy 580system.l2cache.tags.occ_percent::total 0.056928 # Average percentage of cache occupancy | 586system.l2cache.tags.occ_blocks::cpu.inst 128.152617 # Average occupied blocks per requestor 587system.l2cache.tags.occ_blocks::cpu.data 104.454231 # Average occupied blocks per requestor 588system.l2cache.tags.occ_percent::cpu.inst 0.031287 # Average percentage of cache occupancy 589system.l2cache.tags.occ_percent::cpu.data 0.025502 # Average percentage of cache occupancy 590system.l2cache.tags.occ_percent::total 0.056789 # Average percentage of cache occupancy |
| 581system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id 582system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 583system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id 584system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id 585system.l2cache.tags.tag_accesses 4534 # Number of tag accesses 586system.l2cache.tags.data_accesses 4534 # Number of data accesses | 591system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id 592system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 593system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id 594system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id 595system.l2cache.tags.tag_accesses 4534 # Number of tag accesses 596system.l2cache.tags.data_accesses 4534 # Number of data accesses |
| 587system.l2cache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states | 597system.l2cache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
| 588system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits 589system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 590system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 591system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 592system.l2cache.overall_hits::cpu.inst 3 # number of overall hits 593system.l2cache.overall_hits::total 3 # number of overall hits 594system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 595system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 596system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses 597system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses 598system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses 599system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 600system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 601system.l2cache.demand_misses::total 446 # number of demand (read+write) misses 602system.l2cache.overall_misses::cpu.inst 278 # number of overall misses 603system.l2cache.overall_misses::cpu.data 168 # number of overall misses 604system.l2cache.overall_misses::total 446 # number of overall misses | 598system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits 599system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 600system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 601system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 602system.l2cache.overall_hits::cpu.inst 3 # number of overall hits 603system.l2cache.overall_hits::total 3 # number of overall hits 604system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 605system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 606system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses 607system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses 608system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses 609system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 610system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 611system.l2cache.demand_misses::total 446 # number of demand (read+write) misses 612system.l2cache.overall_misses::cpu.inst 278 # number of overall misses 613system.l2cache.overall_misses::cpu.data 168 # number of overall misses 614system.l2cache.overall_misses::total 446 # number of overall misses |
| 605system.l2cache.ReadExReq_miss_latency::cpu.data 7265000 # number of ReadExReq miss cycles 606system.l2cache.ReadExReq_miss_latency::total 7265000 # number of ReadExReq miss cycles 607system.l2cache.ReadSharedReq_miss_latency::cpu.inst 27088000 # number of ReadSharedReq miss cycles 608system.l2cache.ReadSharedReq_miss_latency::cpu.data 9412000 # number of ReadSharedReq miss cycles 609system.l2cache.ReadSharedReq_miss_latency::total 36500000 # number of ReadSharedReq miss cycles 610system.l2cache.demand_miss_latency::cpu.inst 27088000 # number of demand (read+write) miss cycles 611system.l2cache.demand_miss_latency::cpu.data 16677000 # number of demand (read+write) miss cycles 612system.l2cache.demand_miss_latency::total 43765000 # number of demand (read+write) miss cycles 613system.l2cache.overall_miss_latency::cpu.inst 27088000 # number of overall miss cycles 614system.l2cache.overall_miss_latency::cpu.data 16677000 # number of overall miss cycles 615system.l2cache.overall_miss_latency::total 43765000 # number of overall miss cycles | 615system.l2cache.ReadExReq_miss_latency::cpu.data 7437000 # number of ReadExReq miss cycles 616system.l2cache.ReadExReq_miss_latency::total 7437000 # number of ReadExReq miss cycles 617system.l2cache.ReadSharedReq_miss_latency::cpu.inst 29087000 # number of ReadSharedReq miss cycles 618system.l2cache.ReadSharedReq_miss_latency::cpu.data 9786000 # number of ReadSharedReq miss cycles 619system.l2cache.ReadSharedReq_miss_latency::total 38873000 # number of ReadSharedReq miss cycles 620system.l2cache.demand_miss_latency::cpu.inst 29087000 # number of demand (read+write) miss cycles 621system.l2cache.demand_miss_latency::cpu.data 17223000 # number of demand (read+write) miss cycles 622system.l2cache.demand_miss_latency::total 46310000 # number of demand (read+write) miss cycles 623system.l2cache.overall_miss_latency::cpu.inst 29087000 # number of overall miss cycles 624system.l2cache.overall_miss_latency::cpu.data 17223000 # number of overall miss cycles 625system.l2cache.overall_miss_latency::total 46310000 # number of overall miss cycles |
| 616system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 617system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 618system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) 619system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) 620system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses) 621system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses 622system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 623system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 630system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 631system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses 632system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses 633system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 634system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses 635system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses 636system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 637system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses | 626system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 627system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 628system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) 629system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) 630system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses) 631system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses 632system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 633system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 640system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 641system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses 642system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses 643system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 644system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses 645system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses 646system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 647system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses |
| 638system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99520.547945 # average ReadExReq miss latency 639system.l2cache.ReadExReq_avg_miss_latency::total 99520.547945 # average ReadExReq miss latency 640system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97438.848921 # average ReadSharedReq miss latency 641system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99073.684211 # average ReadSharedReq miss latency 642system.l2cache.ReadSharedReq_avg_miss_latency::total 97855.227882 # average ReadSharedReq miss latency 643system.l2cache.demand_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency 644system.l2cache.demand_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency 645system.l2cache.demand_avg_miss_latency::total 98127.802691 # average overall miss latency 646system.l2cache.overall_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency 647system.l2cache.overall_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency 648system.l2cache.overall_avg_miss_latency::total 98127.802691 # average overall miss latency | 648system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329 # average ReadExReq miss latency 649system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329 # average ReadExReq miss latency 650system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403 # average ReadSharedReq miss latency 651system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316 # average ReadSharedReq miss latency 652system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177 # average ReadSharedReq miss latency 653system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency 654system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency 655system.l2cache.demand_avg_miss_latency::total 103834.080717 # average overall miss latency 656system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency 657system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency 658system.l2cache.overall_avg_miss_latency::total 103834.080717 # average overall miss latency |
| 649system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 650system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 651system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 652system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 653system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 654system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 655system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 656system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 657system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses 658system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 659system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses 660system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 661system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 662system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 663system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 664system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 665system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses | 659system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 660system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 661system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 662system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 663system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 664system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 665system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 666system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 667system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses 668system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 669system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses 670system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 671system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 672system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 673system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 674system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 675system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses |
| 666system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5805000 # number of ReadExReq MSHR miss cycles 667system.l2cache.ReadExReq_mshr_miss_latency::total 5805000 # number of ReadExReq MSHR miss cycles 668system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21528000 # number of ReadSharedReq MSHR miss cycles 669system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7512000 # number of ReadSharedReq MSHR miss cycles 670system.l2cache.ReadSharedReq_mshr_miss_latency::total 29040000 # number of ReadSharedReq MSHR miss cycles 671system.l2cache.demand_mshr_miss_latency::cpu.inst 21528000 # number of demand (read+write) MSHR miss cycles 672system.l2cache.demand_mshr_miss_latency::cpu.data 13317000 # number of demand (read+write) MSHR miss cycles 673system.l2cache.demand_mshr_miss_latency::total 34845000 # number of demand (read+write) MSHR miss cycles 674system.l2cache.overall_mshr_miss_latency::cpu.inst 21528000 # number of overall MSHR miss cycles 675system.l2cache.overall_mshr_miss_latency::cpu.data 13317000 # number of overall MSHR miss cycles 676system.l2cache.overall_mshr_miss_latency::total 34845000 # number of overall MSHR miss cycles | 676system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5977000 # number of ReadExReq MSHR miss cycles 677system.l2cache.ReadExReq_mshr_miss_latency::total 5977000 # number of ReadExReq MSHR miss cycles 678system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 23527000 # number of ReadSharedReq MSHR miss cycles 679system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7886000 # number of ReadSharedReq MSHR miss cycles 680system.l2cache.ReadSharedReq_mshr_miss_latency::total 31413000 # number of ReadSharedReq MSHR miss cycles 681system.l2cache.demand_mshr_miss_latency::cpu.inst 23527000 # number of demand (read+write) MSHR miss cycles 682system.l2cache.demand_mshr_miss_latency::cpu.data 13863000 # number of demand (read+write) MSHR miss cycles 683system.l2cache.demand_mshr_miss_latency::total 37390000 # number of demand (read+write) MSHR miss cycles 684system.l2cache.overall_mshr_miss_latency::cpu.inst 23527000 # number of overall MSHR miss cycles 685system.l2cache.overall_mshr_miss_latency::cpu.data 13863000 # number of overall MSHR miss cycles 686system.l2cache.overall_mshr_miss_latency::total 37390000 # number of overall MSHR miss cycles |
| 677system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 678system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 679system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses 680system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 681system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses 682system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses 683system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 684system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses 685system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses 686system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 687system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses | 687system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 688system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 689system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses 690system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 691system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses 692system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses 693system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 694system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses 695system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses 696system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 697system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses |
| 688system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79520.547945 # average ReadExReq mshr miss latency 689system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79520.547945 # average ReadExReq mshr miss latency 690system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77438.848921 # average ReadSharedReq mshr miss latency 691system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79073.684211 # average ReadSharedReq mshr miss latency 692system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77855.227882 # average ReadSharedReq mshr miss latency 693system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency 694system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency 695system.l2cache.demand_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency 696system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency 697system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency 698system.l2cache.overall_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency | 698system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329 # average ReadExReq mshr miss latency 699system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329 # average ReadExReq mshr miss latency 700system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403 # average ReadSharedReq mshr miss latency 701system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316 # average ReadSharedReq mshr miss latency 702system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177 # average ReadSharedReq mshr miss latency 703system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency 704system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency 705system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency 706system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency 707system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency 708system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency |
| 699system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. 700system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 701system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 702system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 703system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 704system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 709system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. 710system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 711system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 712system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 713system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 714system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 705system.membus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states | 715system.membus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
| 706system.membus.trans_dist::ReadResp 373 # Transaction distribution 707system.membus.trans_dist::ReadExReq 73 # Transaction distribution 708system.membus.trans_dist::ReadExResp 73 # Transaction distribution 709system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 710system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 711system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 712system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 713system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 720system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 721system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 722system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 723system.membus.snoop_fanout::min_value 0 # Request fanout histogram 724system.membus.snoop_fanout::max_value 0 # Request fanout histogram 725system.membus.snoop_fanout::total 446 # Request fanout histogram 726system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 727system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) | 716system.membus.trans_dist::ReadResp 373 # Transaction distribution 717system.membus.trans_dist::ReadExReq 73 # Transaction distribution 718system.membus.trans_dist::ReadExResp 73 # Transaction distribution 719system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 720system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 721system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 722system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 723system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 730system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 731system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 732system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 733system.membus.snoop_fanout::min_value 0 # Request fanout histogram 734system.membus.snoop_fanout::max_value 0 # Request fanout histogram 735system.membus.snoop_fanout::total 446 # Request fanout histogram 736system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 737system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) |
| 728system.membus.respLayer0.occupancy 2375750 # Layer occupancy (ticks) 729system.membus.respLayer0.utilization 3.8 # Layer utilization (%) | 738system.membus.respLayer0.occupancy 2377500 # Layer occupancy (ticks) 739system.membus.respLayer0.utilization 3.7 # Layer utilization (%) |
| 730 731---------- End Simulation Statistics ---------- | 740 741---------- End Simulation Statistics ---------- |