| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000061 # Number of seconds simulated 4sim_ticks 61470000 # Number of ticks simulated 5final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000061 # Number of seconds simulated 4sim_ticks 61470000 # Number of ticks simulated 5final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 556042 # Simulator instruction rate (inst/s) 8host_op_rate 555477 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5286056763 # Simulator tick rate (ticks/s) 10host_mem_usage 634812 # Number of bytes of host memory used | 7host_inst_rate 534192 # Simulator instruction rate (inst/s) 8host_op_rate 533574 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5078648410 # Simulator tick rate (ticks/s) 10host_mem_usage 679784 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 6453 # Number of instructions simulated 13sim_ops 6453 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 6453 # Number of instructions simulated 13sim_ops 6453 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states |
|
| 16system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 21system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 22system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 244system.mem_ctrl_1.preBackEnergy 1324500 # Energy for precharge background per rank (pJ) 245system.mem_ctrl_1.totalEnergy 42918630 # Total energy per rank (pJ) 246system.mem_ctrl_1.averagePower 783.705097 # Core power per rank (mW) 247system.mem_ctrl_1.memoryStateTime::IDLE 2128500 # Time in different power states 248system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 245system.mem_ctrl_1.preBackEnergy 1324500 # Energy for precharge background per rank (pJ) 246system.mem_ctrl_1.totalEnergy 42918630 # Total energy per rank (pJ) 247system.mem_ctrl_1.averagePower 783.705097 # Core power per rank (mW) 248system.mem_ctrl_1.memoryStateTime::IDLE 2128500 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states 252system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states |
|
| 252system.cpu.dtb.fetch_hits 0 # ITB hits 253system.cpu.dtb.fetch_misses 0 # ITB misses 254system.cpu.dtb.fetch_acv 0 # ITB acv 255system.cpu.dtb.fetch_accesses 0 # ITB accesses 256system.cpu.dtb.read_hits 1190 # DTB read hits 257system.cpu.dtb.read_misses 7 # DTB read misses 258system.cpu.dtb.read_acv 0 # DTB read access violations 259system.cpu.dtb.read_accesses 1197 # DTB read accesses --- 17 unchanged lines hidden (view full) --- 277system.cpu.itb.write_misses 0 # DTB write misses 278system.cpu.itb.write_acv 0 # DTB write access violations 279system.cpu.itb.write_accesses 0 # DTB write accesses 280system.cpu.itb.data_hits 0 # DTB hits 281system.cpu.itb.data_misses 0 # DTB misses 282system.cpu.itb.data_acv 0 # DTB access violations 283system.cpu.itb.data_accesses 0 # DTB accesses 284system.cpu.workload.num_syscalls 17 # Number of system calls | 254system.cpu.dtb.fetch_hits 0 # ITB hits 255system.cpu.dtb.fetch_misses 0 # ITB misses 256system.cpu.dtb.fetch_acv 0 # ITB acv 257system.cpu.dtb.fetch_accesses 0 # ITB accesses 258system.cpu.dtb.read_hits 1190 # DTB read hits 259system.cpu.dtb.read_misses 7 # DTB read misses 260system.cpu.dtb.read_acv 0 # DTB read access violations 261system.cpu.dtb.read_accesses 1197 # DTB read accesses --- 17 unchanged lines hidden (view full) --- 279system.cpu.itb.write_misses 0 # DTB write misses 280system.cpu.itb.write_acv 0 # DTB write access violations 281system.cpu.itb.write_accesses 0 # DTB write accesses 282system.cpu.itb.data_hits 0 # DTB hits 283system.cpu.itb.data_misses 0 # DTB misses 284system.cpu.itb.data_acv 0 # DTB access violations 285system.cpu.itb.data_accesses 0 # DTB accesses 286system.cpu.workload.num_syscalls 17 # Number of system calls |
| 287system.cpu.pwrStateResidencyTicks::ON 61470000 # Cumulative time (in ticks) in various power states |
|
| 285system.cpu.numCycles 61470 # number of cpu cycles simulated 286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 288system.cpu.committedInsts 6453 # Number of instructions committed 289system.cpu.committedOps 6453 # Number of ops (including micro ops) committed 290system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses 291system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 292system.cpu.num_func_calls 251 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 335system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction 336system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction 337system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction 338system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction 339system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction 340system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 341system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 342system.cpu.op_class::total 6463 # Class of executed instruction | 288system.cpu.numCycles 61470 # number of cpu cycles simulated 289system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 290system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 291system.cpu.committedInsts 6453 # Number of instructions committed 292system.cpu.committedOps 6453 # Number of ops (including micro ops) committed 293system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses 294system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 295system.cpu.num_func_calls 251 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 338system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction 339system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction 340system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction 341system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction 342system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction 343system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 344system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 345system.cpu.op_class::total 6463 # Class of executed instruction |
| 346system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states |
|
| 343system.cpu.dcache.tags.replacements 0 # number of replacements 344system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use 345system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. 346system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 347system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. 348system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 349system.cpu.dcache.tags.occ_blocks::cpu.data 104.645861 # Average occupied blocks per requestor 350system.cpu.dcache.tags.occ_percent::cpu.data 0.102193 # Average percentage of cache occupancy 351system.cpu.dcache.tags.occ_percent::total 0.102193 # Average percentage of cache occupancy 352system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 353system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 354system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 355system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id 356system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses 357system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses | 347system.cpu.dcache.tags.replacements 0 # number of replacements 348system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use 349system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. 350system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 351system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. 352system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 353system.cpu.dcache.tags.occ_blocks::cpu.data 104.645861 # Average occupied blocks per requestor 354system.cpu.dcache.tags.occ_percent::cpu.data 0.102193 # Average percentage of cache occupancy 355system.cpu.dcache.tags.occ_percent::total 0.102193 # Average percentage of cache occupancy 356system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 357system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 358system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 359system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id 360system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses 361system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses |
| 362system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states |
|
| 358system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits 359system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits 360system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 361system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 362system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits 363system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits 364system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits 365system.cpu.dcache.overall_hits::total 1887 # number of overall hits --- 70 unchanged lines hidden (view full) --- 436system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency 437system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency 438system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency 439system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency 440system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 441system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency 442system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 443system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency | 363system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits 364system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits 365system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 366system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 367system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits 368system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits 369system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits 370system.cpu.dcache.overall_hits::total 1887 # number of overall hits --- 70 unchanged lines hidden (view full) --- 441system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency 442system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency 443system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency 444system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency 445system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 446system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency 447system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 448system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency |
| 449system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states |
|
| 444system.cpu.icache.tags.replacements 62 # number of replacements 445system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use 446system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 447system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 448system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 449system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 450system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor 451system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy 452system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy 453system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id 454system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 455system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 456system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id 457system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses 458system.cpu.icache.tags.data_accesses 13209 # Number of data accesses | 450system.cpu.icache.tags.replacements 62 # number of replacements 451system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use 452system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 453system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 454system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 455system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 456system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor 457system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy 458system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy 459system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id 460system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 461system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 462system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id 463system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses 464system.cpu.icache.tags.data_accesses 13209 # Number of data accesses |
| 465system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states |
|
| 459system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits 460system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits 461system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits 462system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits 463system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits 464system.cpu.icache.overall_hits::total 6183 # number of overall hits 465system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses 466system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 523system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency 524system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency 525system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 526system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 527system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 528system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 529system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 530system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 466system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits 467system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits 468system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits 469system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits 470system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits 471system.cpu.icache.overall_hits::total 6183 # number of overall hits 472system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses 473system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses --- 56 unchanged lines hidden (view full) --- 530system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency 531system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency 532system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 533system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 534system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 535system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 536system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 537system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 538system.l2bus.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states |
|
| 531system.l2bus.trans_dist::ReadResp 376 # Transaction distribution 532system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution 533system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution 534system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution 535system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution 536system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) 537system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 538system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 552system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 553system.l2bus.snoop_fanout::total 449 # Request fanout histogram 554system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) 555system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 556system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) 557system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) 558system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) 559system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) | 539system.l2bus.trans_dist::ReadResp 376 # Transaction distribution 540system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution 541system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution 542system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution 543system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution 544system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) 545system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 546system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) --- 13 unchanged lines hidden (view full) --- 560system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 561system.l2bus.snoop_fanout::total 449 # Request fanout histogram 562system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) 563system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 564system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) 565system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) 566system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) 567system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| 568system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states |
|
| 560system.l2cache.tags.replacements 0 # number of replacements 561system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use 562system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. 563system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 564system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks. 565system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 566system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor 567system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor 568system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy 569system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy 570system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy 571system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 572system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 573system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 574system.l2cache.tags.occ_task_id_percent::1024 0.091064 # Percentage of cache occupancy per task id 575system.l2cache.tags.tag_accesses 4534 # Number of tag accesses 576system.l2cache.tags.data_accesses 4534 # Number of data accesses | 569system.l2cache.tags.replacements 0 # number of replacements 570system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use 571system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. 572system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 573system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks. 574system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 575system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor 576system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor 577system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy 578system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy 579system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy 580system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 581system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 582system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 583system.l2cache.tags.occ_task_id_percent::1024 0.091064 # Percentage of cache occupancy per task id 584system.l2cache.tags.tag_accesses 4534 # Number of tag accesses 585system.l2cache.tags.data_accesses 4534 # Number of data accesses |
| 586system.l2cache.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states |
|
| 577system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits 578system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 579system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 580system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 581system.l2cache.overall_hits::cpu.inst 3 # number of overall hits 582system.l2cache.overall_hits::total 3 # number of overall hits 583system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 584system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses --- 95 unchanged lines hidden (view full) --- 680system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency 681system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency 682system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 683system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 684system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency 685system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 686system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 687system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency | 587system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits 588system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 589system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 590system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 591system.l2cache.overall_hits::cpu.inst 3 # number of overall hits 592system.l2cache.overall_hits::total 3 # number of overall hits 593system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 594system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses --- 95 unchanged lines hidden (view full) --- 690system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency 691system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency 692system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 693system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 694system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency 695system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 696system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 697system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency |
| 698system.membus.pwrStateResidencyTicks::UNDEFINED 61470000 # Cumulative time (in ticks) in various power states |
|
| 688system.membus.trans_dist::ReadResp 373 # Transaction distribution 689system.membus.trans_dist::ReadExReq 73 # Transaction distribution 690system.membus.trans_dist::ReadExResp 73 # Transaction distribution 691system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 692system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 693system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 694system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 695system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 699system.membus.trans_dist::ReadResp 373 # Transaction distribution 700system.membus.trans_dist::ReadExReq 73 # Transaction distribution 701system.membus.trans_dist::ReadExResp 73 # Transaction distribution 702system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 703system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 704system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 705system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 706system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |