| stats.txt (11390:f40859930028) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000061 # Number of seconds simulated 4sim_ticks 61470000 # Number of ticks simulated 5final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000061 # Number of seconds simulated 4sim_ticks 61470000 # Number of ticks simulated 5final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 62593 # Simulator instruction rate (inst/s) 8host_op_rate 62569 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 595804848 # Simulator tick rate (ticks/s) 10host_mem_usage 614668 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host | 7host_inst_rate 583425 # Simulator instruction rate (inst/s) 8host_op_rate 580281 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5518802940 # Simulator tick rate (ticks/s) 10host_mem_usage 637904 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host |
| 12sim_insts 6453 # Number of instructions simulated 13sim_ops 6453 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory --- 384 unchanged lines hidden (view full) --- 404system.cpu.dcache.overall_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency 405system.cpu.dcache.overall_avg_miss_latency::total 103452.380952 # average overall miss latency 406system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 407system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 408system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 409system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 410system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 411system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 6453 # Number of instructions simulated 13sim_ops 6453 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory --- 384 unchanged lines hidden (view full) --- 404system.cpu.dcache.overall_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency 405system.cpu.dcache.overall_avg_miss_latency::total 103452.380952 # average overall miss latency 406system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 407system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 408system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 409system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 410system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 411system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 412system.cpu.dcache.fast_writes 0 # number of fast writes performed 413system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 414system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 415system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 416system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 417system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 418system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 419system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 420system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 421system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 438system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency 439system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency 440system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency 441system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency 442system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 443system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency 444system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 445system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency | 412system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 413system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 414system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 415system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 416system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 417system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 418system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 419system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 436system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency 437system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency 438system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency 439system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency 440system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 441system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency 442system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 443system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency |
| 446system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 447system.cpu.icache.tags.replacements 62 # number of replacements 448system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use 449system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 450system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 451system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 452system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 453system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor 454system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 496system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency 497system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency 498system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 499system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 500system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 501system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 502system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 503system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 444system.cpu.icache.tags.replacements 62 # number of replacements 445system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use 446system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 447system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 448system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 449system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 450system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor 451system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 493system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency 494system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency 495system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 496system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 497system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 498system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 499system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 500system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 504system.cpu.icache.fast_writes 0 # number of fast writes performed 505system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 506system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses 507system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses 508system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses 509system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses 510system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses 511system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses 512system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles 513system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 522system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses 523system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses 524system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency 525system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency 526system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency 527system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency 528system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency 529system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency | 501system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses 502system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses 503system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses 504system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses 505system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses 506system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses 507system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles 508system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles --- 8 unchanged lines hidden (view full) --- 517system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses 518system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses 519system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency 520system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency 521system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency 522system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency 523system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency 524system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency |
| 530system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 531system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 532system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 533system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 534system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 535system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 536system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 537system.l2bus.trans_dist::ReadResp 376 # Transaction distribution 538system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution --- 103 unchanged lines hidden (view full) --- 642system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency 643system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency 644system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 645system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 647system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 648system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 649system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 525system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 526system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 527system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 528system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 529system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 530system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 531system.l2bus.trans_dist::ReadResp 376 # Transaction distribution 532system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution --- 103 unchanged lines hidden (view full) --- 636system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency 637system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency 638system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 639system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 640system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 641system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 642system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 643system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 650system.l2cache.fast_writes 0 # number of fast writes performed 651system.l2cache.cache_copies 0 # number of cache copies performed | |
| 652system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 653system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 654system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses 655system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 656system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses 657system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 658system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 659system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses --- 28 unchanged lines hidden (view full) --- 688system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency 689system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency 690system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 691system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 692system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency 693system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 694system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 695system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency | 644system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 645system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 646system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses 647system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 648system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses 649system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 650system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 651system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses --- 28 unchanged lines hidden (view full) --- 680system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency 681system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency 682system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 683system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 684system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency 685system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 686system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 687system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency |
| 696system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 697system.membus.trans_dist::ReadResp 373 # Transaction distribution 698system.membus.trans_dist::ReadExReq 73 # Transaction distribution 699system.membus.trans_dist::ReadExResp 73 # Transaction distribution 700system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 701system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 702system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 703system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 704system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 688system.membus.trans_dist::ReadResp 373 # Transaction distribution 689system.membus.trans_dist::ReadExReq 73 # Transaction distribution 690system.membus.trans_dist::ReadExResp 73 # Transaction distribution 691system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 692system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 693system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 694system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 695system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |