Cross Reference: /gem5/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000062 # Number of seconds simulated

4sim_ticks 61608000 # Number of ticks simulated
5final_tick 61608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

4sim_ticks 61610000 # Number of ticks simulated
5final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 214452 # Simulator instruction rate (inst/s)
8host_op_rate 214360 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2049936831 # Simulator tick rate (ticks/s)
10host_mem_usage 674692 # Number of bytes of host memory used
11host_seconds 0.03 # Real time elapsed on the host

7host_inst_rate 402374 # Simulator instruction rate (inst/s)
8host_op_rate 402048 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 3843418590 # Simulator tick rate (ticks/s)
10host_mem_usage 682268 # Number of bytes of host memory used
11host_seconds 0.02 # Real time elapsed on the host

12sim_insts 6440 # Number of instructions simulated
13sim_ops 6440 # Number of ops (including micro ops) simulated
14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
17system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory
18system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory
19system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
20system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
21system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
22system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory
23system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory

24system.mem_ctrl.bw_read::cpu.inst 288793663 # Total read bandwidth from this memory (bytes/s)
25system.mem_ctrl.bw_read::cpu.data 174522789 # Total read bandwidth from this memory (bytes/s)
26system.mem_ctrl.bw_read::total 463316452 # Total read bandwidth from this memory (bytes/s)
27system.mem_ctrl.bw_inst_read::cpu.inst 288793663 # Instruction read bandwidth from this memory (bytes/s)
28system.mem_ctrl.bw_inst_read::total 288793663 # Instruction read bandwidth from this memory (bytes/s)
29system.mem_ctrl.bw_total::cpu.inst 288793663 # Total bandwidth to/from this memory (bytes/s)
30system.mem_ctrl.bw_total::cpu.data 174522789 # Total bandwidth to/from this memory (bytes/s)
31system.mem_ctrl.bw_total::total 463316452 # Total bandwidth to/from this memory (bytes/s)

24system.mem_ctrl.bw_read::cpu.inst 288784288 # Total read bandwidth from this memory (bytes/s)
25system.mem_ctrl.bw_read::cpu.data 174517124 # Total read bandwidth from this memory (bytes/s)
26system.mem_ctrl.bw_read::total 463301412 # Total read bandwidth from this memory (bytes/s)
27system.mem_ctrl.bw_inst_read::cpu.inst 288784288 # Instruction read bandwidth from this memory (bytes/s)
28system.mem_ctrl.bw_inst_read::total 288784288 # Instruction read bandwidth from this memory (bytes/s)
29system.mem_ctrl.bw_total::cpu.inst 288784288 # Total bandwidth to/from this memory (bytes/s)
30system.mem_ctrl.bw_total::cpu.data 174517124 # Total bandwidth to/from this memory (bytes/s)
31system.mem_ctrl.bw_total::total 463301412 # Total bandwidth to/from this memory (bytes/s)

32system.mem_ctrl.readReqs 446 # Number of read requests accepted
33system.mem_ctrl.writeReqs 0 # Number of write requests accepted
34system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue
35system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM
37system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM
39system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side

--- 30 unchanged lines hidden (view full) ---

70system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts
71system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts
72system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts
73system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts
74system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts
75system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
76system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
77system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry

78system.mem_ctrl.totGap 61358000 # Total gap between requests

78system.mem_ctrl.totGap 61360000 # Total gap between requests

79system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
80system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
81system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2)
82system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2)
83system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
84system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
85system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2)
86system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2)

--- 113 unchanged lines hidden (view full) ---

200system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation
201system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation
202system.mem_ctrl.totQLat 3464500 # Total ticks spent queuing
203system.mem_ctrl.totMemAccLat 11827000 # Total ticks spent from burst creation until serviced by the DRAM
204system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers
205system.mem_ctrl.avgQLat 7767.94 # Average queueing delay per DRAM burst
206system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
207system.mem_ctrl.avgMemAccLat 26517.94 # Average memory access latency per DRAM burst

208system.mem_ctrl.avgRdBW 463.32 # Average DRAM read bandwidth in MiByte/s

208system.mem_ctrl.avgRdBW 463.30 # Average DRAM read bandwidth in MiByte/s

209system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s

210system.mem_ctrl.avgRdBWSys 463.32 # Average system read bandwidth in MiByte/s

210system.mem_ctrl.avgRdBWSys 463.30 # Average system read bandwidth in MiByte/s

211system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
212system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
213system.mem_ctrl.busUtil 3.62 # Data bus utilization in percentage
214system.mem_ctrl.busUtilRead 3.62 # Data bus utilization in percentage for reads
215system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes
216system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
217system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing
218system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads
219system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes
220system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads
221system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes

222system.mem_ctrl.avgGap 137573.99 # Average gap between requests

222system.mem_ctrl.avgGap 137578.48 # Average gap between requests

223system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined
224system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ)
225system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ)
226system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ)
227system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ)
228system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
229system.mem_ctrl_0.actBackEnergy 37159155 # Energy for active background per rank (pJ)
230system.mem_ctrl_0.preBackEnergy 262500 # Energy for precharge background per rank (pJ)

--- 46 unchanged lines hidden (view full) ---

277system.cpu.itb.write_misses 0 # DTB write misses
278system.cpu.itb.write_acv 0 # DTB write access violations
279system.cpu.itb.write_accesses 0 # DTB write accesses
280system.cpu.itb.data_hits 0 # DTB hits
281system.cpu.itb.data_misses 0 # DTB misses
282system.cpu.itb.data_acv 0 # DTB access violations
283system.cpu.itb.data_accesses 0 # DTB accesses
284system.cpu.workload.num_syscalls 17 # Number of system calls

285system.cpu.numCycles 61608 # number of cpu cycles simulated

285system.cpu.numCycles 61610 # number of cpu cycles simulated

286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
288system.cpu.committedInsts 6440 # Number of instructions committed
289system.cpu.committedOps 6440 # Number of ops (including micro ops) committed
290system.cpu.num_int_alu_accesses 6368 # Number of integer alu accesses
291system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
292system.cpu.num_func_calls 251 # number of times a function call or return occured
293system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls
294system.cpu.num_int_insts 6368 # number of integer instructions
295system.cpu.num_fp_insts 10 # number of float instructions
296system.cpu.num_int_register_reads 8380 # number of times the integer registers were read
297system.cpu.num_int_register_writes 4614 # number of times the integer registers were written
298system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
299system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
300system.cpu.num_mem_refs 2063 # number of memory refs
301system.cpu.num_load_insts 1195 # Number of load instructions
302system.cpu.num_store_insts 868 # Number of store instructions
303system.cpu.num_idle_cycles 0 # Number of idle cycles

304system.cpu.num_busy_cycles 61608 # Number of busy cycles

304system.cpu.num_busy_cycles 61610 # Number of busy cycles

305system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
306system.cpu.idle_fraction 0 # Percentage of idle cycles
307system.cpu.Branches 1054 # Number of branches fetched
308system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction
309system.cpu.op_class::IntAlu 4365 67.67% 67.97% # Class of executed instruction
310system.cpu.op_class::IntMult 1 0.02% 67.98% # Class of executed instruction
311system.cpu.op_class::IntDiv 0 0.00% 67.98% # Class of executed instruction
312system.cpu.op_class::FloatAdd 2 0.03% 68.02% # Class of executed instruction

--- 23 unchanged lines hidden (view full) ---

336system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.02% # Class of executed instruction
337system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.02% # Class of executed instruction
338system.cpu.op_class::MemRead 1195 18.53% 86.54% # Class of executed instruction
339system.cpu.op_class::MemWrite 868 13.46% 100.00% # Class of executed instruction
340system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
341system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
342system.cpu.op_class::total 6450 # Class of executed instruction
343system.cpu.dcache.tags.replacements 0 # number of replacements

344system.cpu.dcache.tags.tagsinuse 104.300595 # Cycle average of tags in use

344system.cpu.dcache.tags.tagsinuse 104.302306 # Cycle average of tags in use

345system.cpu.dcache.tags.total_refs 1885 # Total number of references to valid blocks.
346system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
347system.cpu.dcache.tags.avg_refs 11.220238 # Average number of references to valid blocks.
348system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

349system.cpu.dcache.tags.occ_blocks::cpu.data 104.300595 # Average occupied blocks per requestor
350system.cpu.dcache.tags.occ_percent::cpu.data 0.101856 # Average percentage of cache occupancy
351system.cpu.dcache.tags.occ_percent::total 0.101856 # Average percentage of cache occupancy

349system.cpu.dcache.tags.occ_blocks::cpu.data 104.302306 # Average occupied blocks per requestor
350system.cpu.dcache.tags.occ_percent::cpu.data 0.101858 # Average percentage of cache occupancy
351system.cpu.dcache.tags.occ_percent::total 0.101858 # Average percentage of cache occupancy

352system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
353system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
354system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
355system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id
356system.cpu.dcache.tags.tag_accesses 4274 # Number of tag accesses
357system.cpu.dcache.tags.data_accesses 4274 # Number of data accesses
358system.cpu.dcache.ReadReq_hits::cpu.data 1093 # number of ReadReq hits
359system.cpu.dcache.ReadReq_hits::total 1093 # number of ReadReq hits

--- 80 unchanged lines hidden (view full) ---

440system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101945.205479 # average WriteReq mshr miss latency
441system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101945.205479 # average WriteReq mshr miss latency
442system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency
443system.cpu.dcache.demand_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency
444system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency
445system.cpu.dcache.overall_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency
446system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
447system.cpu.icache.tags.replacements 62 # number of replacements

448system.cpu.icache.tags.tagsinuse 113.923956 # Cycle average of tags in use

448system.cpu.icache.tags.tagsinuse 113.926978 # Cycle average of tags in use

449system.cpu.icache.tags.total_refs 6170 # Total number of references to valid blocks.
450system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks.
451system.cpu.icache.tags.avg_refs 21.957295 # Average number of references to valid blocks.
452system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

453system.cpu.icache.tags.occ_blocks::cpu.inst 113.923956 # Average occupied blocks per requestor
454system.cpu.icache.tags.occ_percent::cpu.inst 0.445015 # Average percentage of cache occupancy
455system.cpu.icache.tags.occ_percent::total 0.445015 # Average percentage of cache occupancy

453system.cpu.icache.tags.occ_blocks::cpu.inst 113.926978 # Average occupied blocks per requestor
454system.cpu.icache.tags.occ_percent::cpu.inst 0.445027 # Average percentage of cache occupancy
455system.cpu.icache.tags.occ_percent::total 0.445027 # Average percentage of cache occupancy

456system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id
457system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
458system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
459system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id
460system.cpu.icache.tags.tag_accesses 13183 # Number of tag accesses
461system.cpu.icache.tags.data_accesses 13183 # Number of data accesses
462system.cpu.icache.ReadReq_hits::cpu.inst 6170 # number of ReadReq hits
463system.cpu.icache.ReadReq_hits::total 6170 # number of ReadReq hits
464system.cpu.icache.demand_hits::cpu.inst 6170 # number of demand (read+write) hits
465system.cpu.icache.demand_hits::total 6170 # number of demand (read+write) hits
466system.cpu.icache.overall_hits::cpu.inst 6170 # number of overall hits
467system.cpu.icache.overall_hits::total 6170 # number of overall hits
468system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses
469system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses
470system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses
471system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses
472system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses
473system.cpu.icache.overall_misses::total 281 # number of overall misses

474system.cpu.icache.ReadReq_miss_latency::cpu.inst 28179000 # number of ReadReq miss cycles
475system.cpu.icache.ReadReq_miss_latency::total 28179000 # number of ReadReq miss cycles
476system.cpu.icache.demand_miss_latency::cpu.inst 28179000 # number of demand (read+write) miss cycles
477system.cpu.icache.demand_miss_latency::total 28179000 # number of demand (read+write) miss cycles
478system.cpu.icache.overall_miss_latency::cpu.inst 28179000 # number of overall miss cycles
479system.cpu.icache.overall_miss_latency::total 28179000 # number of overall miss cycles

474system.cpu.icache.ReadReq_miss_latency::cpu.inst 28181000 # number of ReadReq miss cycles
475system.cpu.icache.ReadReq_miss_latency::total 28181000 # number of ReadReq miss cycles
476system.cpu.icache.demand_miss_latency::cpu.inst 28181000 # number of demand (read+write) miss cycles
477system.cpu.icache.demand_miss_latency::total 28181000 # number of demand (read+write) miss cycles
478system.cpu.icache.overall_miss_latency::cpu.inst 28181000 # number of overall miss cycles
479system.cpu.icache.overall_miss_latency::total 28181000 # number of overall miss cycles

480system.cpu.icache.ReadReq_accesses::cpu.inst 6451 # number of ReadReq accesses(hits+misses)
481system.cpu.icache.ReadReq_accesses::total 6451 # number of ReadReq accesses(hits+misses)
482system.cpu.icache.demand_accesses::cpu.inst 6451 # number of demand (read+write) accesses
483system.cpu.icache.demand_accesses::total 6451 # number of demand (read+write) accesses
484system.cpu.icache.overall_accesses::cpu.inst 6451 # number of overall (read+write) accesses
485system.cpu.icache.overall_accesses::total 6451 # number of overall (read+write) accesses
486system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043559 # miss rate for ReadReq accesses
487system.cpu.icache.ReadReq_miss_rate::total 0.043559 # miss rate for ReadReq accesses
488system.cpu.icache.demand_miss_rate::cpu.inst 0.043559 # miss rate for demand accesses
489system.cpu.icache.demand_miss_rate::total 0.043559 # miss rate for demand accesses
490system.cpu.icache.overall_miss_rate::cpu.inst 0.043559 # miss rate for overall accesses
491system.cpu.icache.overall_miss_rate::total 0.043559 # miss rate for overall accesses

492system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100281.138790 # average ReadReq miss latency
493system.cpu.icache.ReadReq_avg_miss_latency::total 100281.138790 # average ReadReq miss latency
494system.cpu.icache.demand_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency
495system.cpu.icache.demand_avg_miss_latency::total 100281.138790 # average overall miss latency
496system.cpu.icache.overall_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency
497system.cpu.icache.overall_avg_miss_latency::total 100281.138790 # average overall miss latency

492system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100288.256228 # average ReadReq miss latency
493system.cpu.icache.ReadReq_avg_miss_latency::total 100288.256228 # average ReadReq miss latency
494system.cpu.icache.demand_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
495system.cpu.icache.demand_avg_miss_latency::total 100288.256228 # average overall miss latency
496system.cpu.icache.overall_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
497system.cpu.icache.overall_avg_miss_latency::total 100288.256228 # average overall miss latency

498system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
499system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
500system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
501system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
502system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
503system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
504system.cpu.icache.fast_writes 0 # number of fast writes performed
505system.cpu.icache.cache_copies 0 # number of cache copies performed
506system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses
507system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses
508system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses
509system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses
510system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses
511system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses

512system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27617000 # number of ReadReq MSHR miss cycles
513system.cpu.icache.ReadReq_mshr_miss_latency::total 27617000 # number of ReadReq MSHR miss cycles
514system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27617000 # number of demand (read+write) MSHR miss cycles
515system.cpu.icache.demand_mshr_miss_latency::total 27617000 # number of demand (read+write) MSHR miss cycles
516system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27617000 # number of overall MSHR miss cycles
517system.cpu.icache.overall_mshr_miss_latency::total 27617000 # number of overall MSHR miss cycles

512system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27619000 # number of ReadReq MSHR miss cycles
513system.cpu.icache.ReadReq_mshr_miss_latency::total 27619000 # number of ReadReq MSHR miss cycles
514system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27619000 # number of demand (read+write) MSHR miss cycles
515system.cpu.icache.demand_mshr_miss_latency::total 27619000 # number of demand (read+write) MSHR miss cycles
516system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27619000 # number of overall MSHR miss cycles
517system.cpu.icache.overall_mshr_miss_latency::total 27619000 # number of overall MSHR miss cycles

518system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for ReadReq accesses
519system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043559 # mshr miss rate for ReadReq accesses
520system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for demand accesses
521system.cpu.icache.demand_mshr_miss_rate::total 0.043559 # mshr miss rate for demand accesses
522system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for overall accesses
523system.cpu.icache.overall_mshr_miss_rate::total 0.043559 # mshr miss rate for overall accesses

524system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98281.138790 # average ReadReq mshr miss latency
525system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98281.138790 # average ReadReq mshr miss latency
526system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency
527system.cpu.icache.demand_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency
528system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency
529system.cpu.icache.overall_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency

524system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98288.256228 # average ReadReq mshr miss latency
525system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98288.256228 # average ReadReq mshr miss latency
526system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
527system.cpu.icache.demand_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency
528system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
529system.cpu.icache.overall_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency

530system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

531system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
532system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data.
533system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
534system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
535system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
536system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

531system.l2bus.trans_dist::ReadResp 376 # Transaction distribution
532system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution
533system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution
534system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution
535system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution
536system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes)
537system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
538system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes)
539system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes)
540system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
541system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes)
542system.l2bus.snoops 0 # Total snoops (count)
543system.l2bus.snoop_fanout::samples 511 # Request fanout histogram

537system.l2bus.trans_dist::ReadResp 376 # Transaction distribution
538system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution
539system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution
540system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution
541system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution
542system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes)
543system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
544system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes)
545system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes)
546system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
547system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes)
548system.l2bus.snoops 0 # Total snoops (count)
549system.l2bus.snoop_fanout::samples 511 # Request fanout histogram

544system.l2bus.snoop_fanout::mean 1 # Request fanout histogram
545system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram

550system.l2bus.snoop_fanout::mean 0.001957 # Request fanout histogram
551system.l2bus.snoop_fanout::stdev 0.044237 # Request fanout histogram

546system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

552system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram

547system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
548system.l2bus.snoop_fanout::1 511 100.00% 100.00% # Request fanout histogram

553system.l2bus.snoop_fanout::0 510 99.80% 99.80% # Request fanout histogram
554system.l2bus.snoop_fanout::1 1 0.20% 100.00% # Request fanout histogram

549system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
550system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

555system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
556system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

551system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram

557system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram

552system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
553system.l2bus.snoop_fanout::total 511 # Request fanout histogram
554system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks)
555system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
556system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks)
557system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
558system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks)
559system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
560system.l2cache.tags.replacements 0 # number of replacements

558system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
559system.l2bus.snoop_fanout::total 511 # Request fanout histogram
560system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks)
561system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
562system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks)
563system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
564system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks)
565system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
566system.l2cache.tags.replacements 0 # number of replacements

561system.l2cache.tags.tagsinuse 185.387550 # Cycle average of tags in use

567system.l2cache.tags.tagsinuse 185.392407 # Cycle average of tags in use

562system.l2cache.tags.total_refs 65 # Total number of references to valid blocks.
563system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
564system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks.
565system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

568system.l2cache.tags.total_refs 65 # Total number of references to valid blocks.
569system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
570system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks.
571system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

566system.l2cache.tags.occ_blocks::cpu.inst 128.677366 # Average occupied blocks per requestor
567system.l2cache.tags.occ_blocks::cpu.data 56.710184 # Average occupied blocks per requestor
568system.l2cache.tags.occ_percent::cpu.inst 0.031415 # Average percentage of cache occupancy

572system.l2cache.tags.occ_blocks::cpu.inst 128.681337 # Average occupied blocks per requestor
573system.l2cache.tags.occ_blocks::cpu.data 56.711070 # Average occupied blocks per requestor
574system.l2cache.tags.occ_percent::cpu.inst 0.031416 # Average percentage of cache occupancy

569system.l2cache.tags.occ_percent::cpu.data 0.013845 # Average percentage of cache occupancy

575system.l2cache.tags.occ_percent::cpu.data 0.013845 # Average percentage of cache occupancy

570system.l2cache.tags.occ_percent::total 0.045261 # Average percentage of cache occupancy

576system.l2cache.tags.occ_percent::total 0.045262 # Average percentage of cache occupancy