1 2---------- Begin Simulation Statistics ---------- |
3sim_seconds 0.000065 # Number of seconds simulated 4sim_ticks 64758000 # Number of ticks simulated 5final_tick 64758000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 560678 # Simulator instruction rate (inst/s) 8host_op_rate 559951 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5612828222 # Simulator tick rate (ticks/s) 10host_mem_usage 638096 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host |
12sim_insts 6453 # Number of instructions simulated 13sim_ops 6453 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
16system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
17system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 19system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 20system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 21system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 22system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory 24system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory |
25system.mem_ctrl.bw_read::cpu.inst 274745977 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::cpu.data 166033540 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_read::total 440779518 # Total read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::cpu.inst 274745977 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_inst_read::total 274745977 # Instruction read bandwidth from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.inst 274745977 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::cpu.data 166033540 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.bw_total::total 440779518 # Total bandwidth to/from this memory (bytes/s) |
33system.mem_ctrl.readReqs 446 # Number of read requests accepted 34system.mem_ctrl.writeReqs 0 # Number of write requests accepted 35system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue 36system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM 38system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 40system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 76system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 77system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 78system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry |
79system.mem_ctrl.totGap 64501000 # Total gap between requests |
80system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 86system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2) 87system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) --- 94 unchanged lines hidden (view full) --- 182system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see |
190system.mem_ctrl.bytesPerActivate::samples 105 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::mean 264.533333 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::gmean 181.831163 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::stdev 249.307389 # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::0-127 27 25.71% 25.71% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::128-255 40 38.10% 63.81% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::256-383 10 9.52% 73.33% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::384-511 9 8.57% 81.90% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::512-639 7 6.67% 88.57% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::640-767 6 5.71% 94.29% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::768-895 1 0.95% 95.24% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation 202system.mem_ctrl.bytesPerActivate::total 105 # Bytes accessed per row activation 203system.mem_ctrl.totQLat 6134000 # Total ticks spent queuing 204system.mem_ctrl.totMemAccLat 14496500 # Total ticks spent from burst creation until serviced by the DRAM |
205system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers |
206system.mem_ctrl.avgQLat 13753.36 # Average queueing delay per DRAM burst |
207system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst |
208system.mem_ctrl.avgMemAccLat 32503.36 # Average memory access latency per DRAM burst 209system.mem_ctrl.avgRdBW 440.78 # Average DRAM read bandwidth in MiByte/s |
210system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
211system.mem_ctrl.avgRdBWSys 440.78 # Average system read bandwidth in MiByte/s |
212system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
214system.mem_ctrl.busUtil 3.44 # Data bus utilization in percentage 215system.mem_ctrl.busUtilRead 3.44 # Data bus utilization in percentage for reads |
216system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 218system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing |
219system.mem_ctrl.readRowHits 337 # Number of row buffer hits during reads |
220system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes |
221system.mem_ctrl.readRowHitRate 75.56 # Row buffer hit rate for reads |
222system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes |
223system.mem_ctrl.avgGap 144621.08 # Average gap between requests 224system.mem_ctrl.pageHitRate 75.56 # Row buffer hit rate, read and write combined 225system.mem_ctrl_0.actEnergy 314160 # Energy for activate commands per rank (pJ) 226system.mem_ctrl_0.preEnergy 163185 # Energy for precharge commands per rank (pJ) 227system.mem_ctrl_0.readEnergy 1542240 # Energy for read commands per rank (pJ) |
228system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
229system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) 230system.mem_ctrl_0.actBackEnergy 3812160 # Energy for active background per rank (pJ) 231system.mem_ctrl_0.preBackEnergy 131040 # Energy for precharge background per rank (pJ) 232system.mem_ctrl_0.actPowerDownEnergy 22575420 # Energy for active power-down per rank (pJ) 233system.mem_ctrl_0.prePowerDownEnergy 2515200 # Energy for precharge power-down per rank (pJ) 234system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 235system.mem_ctrl_0.totalEnergy 35970525 # Total energy per rank (pJ) 236system.mem_ctrl_0.averagePower 555.454282 # Core power per rank (mW) 237system.mem_ctrl_0.totalIdleTime 55623250 # Total Idle time Per DRAM Rank 238system.mem_ctrl_0.memoryStateTime::IDLE 77000 # Time in different power states 239system.mem_ctrl_0.memoryStateTime::REF 2080000 # Time in different power states 240system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states 241system.mem_ctrl_0.memoryStateTime::PRE_PDN 6549500 # Time in different power states 242system.mem_ctrl_0.memoryStateTime::ACT 6531250 # Time in different power states 243system.mem_ctrl_0.memoryStateTime::ACT_PDN 49520250 # Time in different power states 244system.mem_ctrl_1.actEnergy 464100 # Energy for activate commands per rank (pJ) 245system.mem_ctrl_1.preEnergy 235290 # Energy for precharge commands per rank (pJ) 246system.mem_ctrl_1.readEnergy 1642200 # Energy for read commands per rank (pJ) |
247system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
248system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ) 249system.mem_ctrl_1.actBackEnergy 4174680 # Energy for active background per rank (pJ) 250system.mem_ctrl_1.preBackEnergy 251520 # Energy for precharge background per rank (pJ) 251system.mem_ctrl_1.actPowerDownEnergy 24338430 # Energy for active power-down per rank (pJ) 252system.mem_ctrl_1.prePowerDownEnergy 604800 # Energy for precharge power-down per rank (pJ) 253system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 254system.mem_ctrl_1.totalEnergy 36628140 # Total energy per rank (pJ) 255system.mem_ctrl_1.averagePower 565.609126 # Core power per rank (mW) 256system.mem_ctrl_1.totalIdleTime 54728750 # Total Idle time Per DRAM Rank 257system.mem_ctrl_1.memoryStateTime::IDLE 283000 # Time in different power states 258system.mem_ctrl_1.memoryStateTime::REF 2080000 # Time in different power states 259system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states 260system.mem_ctrl_1.memoryStateTime::PRE_PDN 1573250 # Time in different power states 261system.mem_ctrl_1.memoryStateTime::ACT 7457000 # Time in different power states 262system.mem_ctrl_1.memoryStateTime::ACT_PDN 53364750 # Time in different power states 263system.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
264system.cpu.dtb.fetch_hits 0 # ITB hits 265system.cpu.dtb.fetch_misses 0 # ITB misses 266system.cpu.dtb.fetch_acv 0 # ITB acv 267system.cpu.dtb.fetch_accesses 0 # ITB accesses 268system.cpu.dtb.read_hits 1190 # DTB read hits 269system.cpu.dtb.read_misses 7 # DTB read misses 270system.cpu.dtb.read_acv 0 # DTB read access violations 271system.cpu.dtb.read_accesses 1197 # DTB read accesses --- 17 unchanged lines hidden (view full) --- 289system.cpu.itb.write_misses 0 # DTB write misses 290system.cpu.itb.write_acv 0 # DTB write access violations 291system.cpu.itb.write_accesses 0 # DTB write accesses 292system.cpu.itb.data_hits 0 # DTB hits 293system.cpu.itb.data_misses 0 # DTB misses 294system.cpu.itb.data_acv 0 # DTB access violations 295system.cpu.itb.data_accesses 0 # DTB accesses 296system.cpu.workload.num_syscalls 17 # Number of system calls |
297system.cpu.pwrStateResidencyTicks::ON 64758000 # Cumulative time (in ticks) in various power states 298system.cpu.numCycles 64758 # number of cpu cycles simulated |
299system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 300system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 301system.cpu.committedInsts 6453 # Number of instructions committed 302system.cpu.committedOps 6453 # Number of ops (including micro ops) committed 303system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses 304system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 305system.cpu.num_func_calls 251 # number of times a function call or return occured 306system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls 307system.cpu.num_int_insts 6380 # number of integer instructions 308system.cpu.num_fp_insts 10 # number of float instructions 309system.cpu.num_int_register_reads 8392 # number of times the integer registers were read 310system.cpu.num_int_register_writes 4621 # number of times the integer registers were written 311system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 312system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 313system.cpu.num_mem_refs 2065 # number of memory refs 314system.cpu.num_load_insts 1197 # Number of load instructions 315system.cpu.num_store_insts 868 # Number of store instructions 316system.cpu.num_idle_cycles 0 # Number of idle cycles |
317system.cpu.num_busy_cycles 64758 # Number of busy cycles |
318system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 319system.cpu.idle_fraction 0 # Percentage of idle cycles 320system.cpu.Branches 1060 # Number of branches fetched 321system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction 322system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction 323system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction 324system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction 325system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 348system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction 349system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction 350system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction 351system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction 352system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction 353system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 354system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 355system.cpu.op_class::total 6463 # Class of executed instruction |
356system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
357system.cpu.dcache.tags.replacements 0 # number of replacements |
358system.cpu.dcache.tags.tagsinuse 104.399751 # Cycle average of tags in use |
359system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. 360system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 361system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. 362system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
363system.cpu.dcache.tags.occ_blocks::cpu.data 104.399751 # Average occupied blocks per requestor 364system.cpu.dcache.tags.occ_percent::cpu.data 0.101953 # Average percentage of cache occupancy 365system.cpu.dcache.tags.occ_percent::total 0.101953 # Average percentage of cache occupancy |
366system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 367system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 368system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 369system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id 370system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses 371system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses |
372system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
373system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits 374system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits 375system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 376system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 377system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits 378system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits 379system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits 380system.cpu.dcache.overall_hits::total 1887 # number of overall hits 381system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 382system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 383system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 384system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 385system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 386system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 387system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 388system.cpu.dcache.overall_misses::total 168 # number of overall misses |
389system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261000 # number of ReadReq miss cycles 390system.cpu.dcache.ReadReq_miss_latency::total 10261000 # number of ReadReq miss cycles 391system.cpu.dcache.WriteReq_miss_latency::cpu.data 7802000 # number of WriteReq miss cycles 392system.cpu.dcache.WriteReq_miss_latency::total 7802000 # number of WriteReq miss cycles 393system.cpu.dcache.demand_miss_latency::cpu.data 18063000 # number of demand (read+write) miss cycles 394system.cpu.dcache.demand_miss_latency::total 18063000 # number of demand (read+write) miss cycles 395system.cpu.dcache.overall_miss_latency::cpu.data 18063000 # number of overall miss cycles 396system.cpu.dcache.overall_miss_latency::total 18063000 # number of overall miss cycles |
397system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) 398system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) 399system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 400system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 401system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses 402system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses 403system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses 404system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses 405system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses 406system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses 407system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 408system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 409system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses 410system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses 411system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses 412system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses |
413system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316 # average ReadReq miss latency 414system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316 # average ReadReq miss latency 415system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329 # average WriteReq miss latency 416system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329 # average WriteReq miss latency 417system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency 418system.cpu.dcache.demand_avg_miss_latency::total 107517.857143 # average overall miss latency 419system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency 420system.cpu.dcache.overall_avg_miss_latency::total 107517.857143 # average overall miss latency |
421system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 422system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 423system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 424system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 425system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 426system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 427system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 428system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 429system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 430system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 431system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 432system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 433system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 434system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses |
435system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10071000 # number of ReadReq MSHR miss cycles 436system.cpu.dcache.ReadReq_mshr_miss_latency::total 10071000 # number of ReadReq MSHR miss cycles 437system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7656000 # number of WriteReq MSHR miss cycles 438system.cpu.dcache.WriteReq_mshr_miss_latency::total 7656000 # number of WriteReq MSHR miss cycles 439system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17727000 # number of demand (read+write) MSHR miss cycles 440system.cpu.dcache.demand_mshr_miss_latency::total 17727000 # number of demand (read+write) MSHR miss cycles 441system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17727000 # number of overall MSHR miss cycles 442system.cpu.dcache.overall_mshr_miss_latency::total 17727000 # number of overall MSHR miss cycles |
443system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses 444system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses 445system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 446system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 447system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses 448system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses 449system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses 450system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses |
451system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316 # average ReadReq mshr miss latency 452system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316 # average ReadReq mshr miss latency 453system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329 # average WriteReq mshr miss latency 454system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329 # average WriteReq mshr miss latency 455system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency 456system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency 457system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency 458system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency 459system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
460system.cpu.icache.tags.replacements 62 # number of replacements |
461system.cpu.icache.tags.tagsinuse 113.445692 # Cycle average of tags in use |
462system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 463system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 464system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 465system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
466system.cpu.icache.tags.occ_blocks::cpu.inst 113.445692 # Average occupied blocks per requestor 467system.cpu.icache.tags.occ_percent::cpu.inst 0.443147 # Average percentage of cache occupancy 468system.cpu.icache.tags.occ_percent::total 0.443147 # Average percentage of cache occupancy |
469system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id 470system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 471system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 472system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id 473system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses 474system.cpu.icache.tags.data_accesses 13209 # Number of data accesses |
475system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
476system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits 477system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits 478system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits 479system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits 480system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits 481system.cpu.icache.overall_hits::total 6183 # number of overall hits 482system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses 483system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses 484system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses 485system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses 486system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses 487system.cpu.icache.overall_misses::total 281 # number of overall misses |
488system.cpu.icache.ReadReq_miss_latency::cpu.inst 30557000 # number of ReadReq miss cycles 489system.cpu.icache.ReadReq_miss_latency::total 30557000 # number of ReadReq miss cycles 490system.cpu.icache.demand_miss_latency::cpu.inst 30557000 # number of demand (read+write) miss cycles 491system.cpu.icache.demand_miss_latency::total 30557000 # number of demand (read+write) miss cycles 492system.cpu.icache.overall_miss_latency::cpu.inst 30557000 # number of overall miss cycles 493system.cpu.icache.overall_miss_latency::total 30557000 # number of overall miss cycles |
494system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) 495system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) 496system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses 497system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses 498system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses 499system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses 500system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses 501system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses 502system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses 503system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses 504system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses 505system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses |
506system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242 # average ReadReq miss latency 507system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242 # average ReadReq miss latency 508system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency 509system.cpu.icache.demand_avg_miss_latency::total 108743.772242 # average overall miss latency 510system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency 511system.cpu.icache.overall_avg_miss_latency::total 108743.772242 # average overall miss latency |
512system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 513system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 514system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 515system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 516system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 517system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 518system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses 519system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses 520system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses 521system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses 522system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses 523system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses |
524system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29995000 # number of ReadReq MSHR miss cycles 525system.cpu.icache.ReadReq_mshr_miss_latency::total 29995000 # number of ReadReq MSHR miss cycles 526system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29995000 # number of demand (read+write) MSHR miss cycles 527system.cpu.icache.demand_mshr_miss_latency::total 29995000 # number of demand (read+write) MSHR miss cycles 528system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29995000 # number of overall MSHR miss cycles 529system.cpu.icache.overall_mshr_miss_latency::total 29995000 # number of overall MSHR miss cycles |
530system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses 531system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses 532system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses 533system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses 534system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses 535system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses |
536system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242 # average ReadReq mshr miss latency 537system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242 # average ReadReq mshr miss latency 538system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency 539system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency 540system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency 541system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency |
542system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 543system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 544system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 545system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 546system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 547system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
548system.l2bus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
549system.l2bus.trans_dist::ReadResp 376 # Transaction distribution 550system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution 551system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution 552system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution 553system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution 554system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) 555system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 556system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) --- 11 unchanged lines hidden (view full) --- 568system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 569system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 570system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 571system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 572system.l2bus.snoop_fanout::total 449 # Request fanout histogram 573system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) 574system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 575system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) |
576system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) |
577system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) 578system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) |
579system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
580system.l2cache.tags.replacements 0 # number of replacements |
581system.l2cache.tags.tagsinuse 232.606847 # Cycle average of tags in use |
582system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. 583system.l2cache.tags.sampled_refs 446 # Sample count of references to valid blocks. 584system.l2cache.tags.avg_refs 0.145740 # Average number of references to valid blocks. 585system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
586system.l2cache.tags.occ_blocks::cpu.inst 128.152617 # Average occupied blocks per requestor 587system.l2cache.tags.occ_blocks::cpu.data 104.454231 # Average occupied blocks per requestor 588system.l2cache.tags.occ_percent::cpu.inst 0.031287 # Average percentage of cache occupancy 589system.l2cache.tags.occ_percent::cpu.data 0.025502 # Average percentage of cache occupancy 590system.l2cache.tags.occ_percent::total 0.056789 # Average percentage of cache occupancy |
591system.l2cache.tags.occ_task_id_blocks::1024 446 # Occupied blocks per task id 592system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 593system.l2cache.tags.age_task_id_blocks_1024::1 384 # Occupied blocks per task id 594system.l2cache.tags.occ_task_id_percent::1024 0.108887 # Percentage of cache occupancy per task id 595system.l2cache.tags.tag_accesses 4534 # Number of tag accesses 596system.l2cache.tags.data_accesses 4534 # Number of data accesses |
597system.l2cache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
598system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits 599system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 600system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 601system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 602system.l2cache.overall_hits::cpu.inst 3 # number of overall hits 603system.l2cache.overall_hits::total 3 # number of overall hits 604system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 605system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 606system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses 607system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses 608system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses 609system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 610system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 611system.l2cache.demand_misses::total 446 # number of demand (read+write) misses 612system.l2cache.overall_misses::cpu.inst 278 # number of overall misses 613system.l2cache.overall_misses::cpu.data 168 # number of overall misses 614system.l2cache.overall_misses::total 446 # number of overall misses |
615system.l2cache.ReadExReq_miss_latency::cpu.data 7437000 # number of ReadExReq miss cycles 616system.l2cache.ReadExReq_miss_latency::total 7437000 # number of ReadExReq miss cycles 617system.l2cache.ReadSharedReq_miss_latency::cpu.inst 29087000 # number of ReadSharedReq miss cycles 618system.l2cache.ReadSharedReq_miss_latency::cpu.data 9786000 # number of ReadSharedReq miss cycles 619system.l2cache.ReadSharedReq_miss_latency::total 38873000 # number of ReadSharedReq miss cycles 620system.l2cache.demand_miss_latency::cpu.inst 29087000 # number of demand (read+write) miss cycles 621system.l2cache.demand_miss_latency::cpu.data 17223000 # number of demand (read+write) miss cycles 622system.l2cache.demand_miss_latency::total 46310000 # number of demand (read+write) miss cycles 623system.l2cache.overall_miss_latency::cpu.inst 29087000 # number of overall miss cycles 624system.l2cache.overall_miss_latency::cpu.data 17223000 # number of overall miss cycles 625system.l2cache.overall_miss_latency::total 46310000 # number of overall miss cycles |
626system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 627system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 628system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) 629system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) 630system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses) 631system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses 632system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 633system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 640system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 641system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses 642system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses 643system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 644system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses 645system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses 646system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 647system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses |
648system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329 # average ReadExReq miss latency 649system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329 # average ReadExReq miss latency 650system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403 # average ReadSharedReq miss latency 651system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316 # average ReadSharedReq miss latency 652system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177 # average ReadSharedReq miss latency 653system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency 654system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency 655system.l2cache.demand_avg_miss_latency::total 103834.080717 # average overall miss latency 656system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency 657system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency 658system.l2cache.overall_avg_miss_latency::total 103834.080717 # average overall miss latency |
659system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 660system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 661system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 662system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 663system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 664system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 665system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 666system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 667system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses 668system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 669system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses 670system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 671system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 672system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 673system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 674system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 675system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses |
676system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5977000 # number of ReadExReq MSHR miss cycles 677system.l2cache.ReadExReq_mshr_miss_latency::total 5977000 # number of ReadExReq MSHR miss cycles 678system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 23527000 # number of ReadSharedReq MSHR miss cycles 679system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7886000 # number of ReadSharedReq MSHR miss cycles 680system.l2cache.ReadSharedReq_mshr_miss_latency::total 31413000 # number of ReadSharedReq MSHR miss cycles 681system.l2cache.demand_mshr_miss_latency::cpu.inst 23527000 # number of demand (read+write) MSHR miss cycles 682system.l2cache.demand_mshr_miss_latency::cpu.data 13863000 # number of demand (read+write) MSHR miss cycles 683system.l2cache.demand_mshr_miss_latency::total 37390000 # number of demand (read+write) MSHR miss cycles 684system.l2cache.overall_mshr_miss_latency::cpu.inst 23527000 # number of overall MSHR miss cycles 685system.l2cache.overall_mshr_miss_latency::cpu.data 13863000 # number of overall MSHR miss cycles 686system.l2cache.overall_mshr_miss_latency::total 37390000 # number of overall MSHR miss cycles |
687system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 688system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 689system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses 690system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 691system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses 692system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses 693system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 694system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses 695system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses 696system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 697system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses |
698system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329 # average ReadExReq mshr miss latency 699system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329 # average ReadExReq mshr miss latency 700system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403 # average ReadSharedReq mshr miss latency 701system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316 # average ReadSharedReq mshr miss latency 702system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177 # average ReadSharedReq mshr miss latency 703system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency 704system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency 705system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency 706system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency 707system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency 708system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency |
709system.membus.snoop_filter.tot_requests 446 # Total number of requests made to the snoop filter. 710system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 711system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 712system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 713system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 714system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
715system.membus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states |
716system.membus.trans_dist::ReadResp 373 # Transaction distribution 717system.membus.trans_dist::ReadExReq 73 # Transaction distribution 718system.membus.trans_dist::ReadExResp 73 # Transaction distribution 719system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 720system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 721system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 722system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 723system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 730system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 731system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 732system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 733system.membus.snoop_fanout::min_value 0 # Request fanout histogram 734system.membus.snoop_fanout::max_value 0 # Request fanout histogram 735system.membus.snoop_fanout::total 446 # Request fanout histogram 736system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 737system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) |
738system.membus.respLayer0.occupancy 2377500 # Layer occupancy (ticks) 739system.membus.respLayer0.utilization 3.7 # Layer utilization (%) |
740 741---------- End Simulation Statistics ---------- |