3,5c3,5
< sim_seconds 0.000062 # Number of seconds simulated
< sim_ticks 62213000 # Number of ticks simulated
< final_tick 62213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000065 # Number of seconds simulated
> sim_ticks 64758000 # Number of ticks simulated
> final_tick 64758000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 276862 # Simulator instruction rate (inst/s)
< host_op_rate 276760 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2667377590 # Simulator tick rate (ticks/s)
< host_mem_usage 639424 # Number of bytes of host memory used
< host_seconds 0.02 # Real time elapsed on the host
---
> host_inst_rate 560678 # Simulator instruction rate (inst/s)
> host_op_rate 559951 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5612828222 # Simulator tick rate (ticks/s)
> host_mem_usage 638096 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 285985244 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 172825615 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 458810859 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 285985244 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 285985244 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 285985244 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 172825615 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 458810859 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 274745977 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 166033540 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 440779518 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 274745977 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 274745977 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 274745977 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 166033540 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 440779518 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 61962000 # Total gap between requests
---
> system.mem_ctrl.totGap 64501000 # Total gap between requests
190,204c190,204
< system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 185.768755 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 255.860208 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 22 23.16% 23.16% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 36 37.89% 61.05% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 14 14.74% 75.79% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 5 5.26% 81.05% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3590750 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 11953250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 105 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 264.533333 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 181.831163 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 249.307389 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 27 25.71% 25.71% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 40 38.10% 63.81% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 10 9.52% 73.33% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 9 8.57% 81.90% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 7 6.67% 88.57% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 6 5.71% 94.29% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 1 0.95% 95.24% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 105 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 6134000 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 14496500 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.mem_ctrl.avgQLat 8051.01 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 13753.36 # Average queueing delay per DRAM burst
208,209c208,209
< system.mem_ctrl.avgMemAccLat 26801.01 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 458.81 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 32503.36 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 440.78 # Average DRAM read bandwidth in MiByte/s
211c211
< system.mem_ctrl.avgRdBWSys 458.81 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 440.78 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.mem_ctrl.busUtil 3.58 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.58 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.44 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.44 # Data bus utilization in percentage for reads
219c219
< system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 337 # Number of row buffer hits during reads
221c221
< system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 75.56 # Row buffer hit rate for reads
223,227c223,227
< system.mem_ctrl.avgGap 138928.25 # Average gap between requests
< system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl.avgGap 144621.08 # Average gap between requests
> system.mem_ctrl.pageHitRate 75.56 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 314160 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_0.preEnergy 163185 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_0.readEnergy 1542240 # Energy for read commands per rank (pJ)
229,241c229,246
< system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_0.actBackEnergy 37021500 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 383250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 43027155 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 785.686791 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 966000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT 52514000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.mem_ctrl_1.actEnergy 370440 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 202125 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_1.readEnergy 1466400 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_0.actBackEnergy 3812160 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 131040 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.actPowerDownEnergy 22575420 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_0.prePowerDownEnergy 2515200 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_0.totalEnergy 35970525 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 555.454282 # Core power per rank (mW)
> system.mem_ctrl_0.totalIdleTime 55623250 # Total Idle time Per DRAM Rank
> system.mem_ctrl_0.memoryStateTime::IDLE 77000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::REF 2080000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::PRE_PDN 6549500 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT 6531250 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT_PDN 49520250 # Time in different power states
> system.mem_ctrl_1.actEnergy 464100 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 235290 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_1.readEnergy 1642200 # Energy for read commands per rank (pJ)
243,253c248,263
< system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_1.actBackEnergy 35989515 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 1288500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 42876900 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 782.943096 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 1815750 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT 51141750 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_1.actBackEnergy 4174680 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 251520 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.actPowerDownEnergy 24338430 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_1.prePowerDownEnergy 604800 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_1.totalEnergy 36628140 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 565.609126 # Core power per rank (mW)
> system.mem_ctrl_1.totalIdleTime 54728750 # Total Idle time Per DRAM Rank
> system.mem_ctrl_1.memoryStateTime::IDLE 283000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::REF 2080000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::PRE_PDN 1573250 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT 7457000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT_PDN 53364750 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
287,288c297,298
< system.cpu.pwrStateResidencyTicks::ON 62213000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 62213 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 64758000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 64758 # number of cpu cycles simulated
307c317
< system.cpu.num_busy_cycles 62213 # Number of busy cycles
---
> system.cpu.num_busy_cycles 64758 # Number of busy cycles
346c356
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
348c358
< system.cpu.dcache.tags.tagsinuse 104.646393 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 104.399751 # Cycle average of tags in use
353,355c363,365
< system.cpu.dcache.tags.occ_blocks::cpu.data 104.646393 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.102194 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.102194 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 104.399751 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.101953 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.101953 # Average percentage of cache occupancy
362c372
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
379,386c389,396
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9887000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9887000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 7630000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 7630000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 17517000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17517000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 17517000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17517000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10261000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 7802000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 7802000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 18063000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 18063000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 18063000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 18063000 # number of overall miss cycles
403,410c413,420
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 104073.684211 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 104073.684211 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104520.547945 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 104520.547945 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 104267.857143 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 104267.857143 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 107517.857143 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 107517.857143 # average overall miss latency
425,432c435,442
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9697000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 9697000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7484000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 7484000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17181000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 17181000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17181000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 17181000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10071000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10071000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7656000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 7656000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17727000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 17727000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17727000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 17727000 # number of overall MSHR miss cycles
441,449c451,459
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 102073.684211 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 102073.684211 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102520.547945 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102520.547945 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
451c461
< system.cpu.icache.tags.tagsinuse 113.718871 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 113.445692 # Cycle average of tags in use
456,458c466,468
< system.cpu.icache.tags.occ_blocks::cpu.inst 113.718871 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.444214 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.444214 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 113.445692 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.443147 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.443147 # Average percentage of cache occupancy
465c475
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
478,483c488,493
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 28558000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 28558000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 28558000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 28558000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 28558000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 28558000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 30557000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 30557000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 30557000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 30557000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 30557000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 30557000 # number of overall miss cycles
496,501c506,511
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101629.893238 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 101629.893238 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 101629.893238 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 101629.893238 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 108743.772242 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 108743.772242 # average overall miss latency
514,519c524,529
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27996000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 27996000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27996000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 27996000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27996000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 27996000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29995000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 29995000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29995000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 29995000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29995000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 29995000 # number of overall MSHR miss cycles
526,531c536,541
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99629.893238 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99629.893238 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency
538c548
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
566c576
< system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
---
> system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%)
569c579
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
571c581
< system.l2cache.tags.tagsinuse 233.175851 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 232.606847 # Cycle average of tags in use
576,580c586,590
< system.l2cache.tags.occ_blocks::cpu.inst 128.472749 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 104.703102 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.031365 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.025562 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.056928 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_blocks::cpu.inst 128.152617 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 104.454231 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.031287 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.025502 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.056789 # Average percentage of cache occupancy
587c597
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
605,615c615,625
< system.l2cache.ReadExReq_miss_latency::cpu.data 7265000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 7265000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 27088000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 9412000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 36500000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 27088000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 16677000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 43765000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 27088000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 16677000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 43765000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 7437000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 7437000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 29087000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 9786000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 38873000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 29087000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 17223000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 46310000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 29087000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 17223000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 46310000 # number of overall miss cycles
638,648c648,658
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99520.547945 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 99520.547945 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97438.848921 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99073.684211 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 97855.227882 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 98127.802691 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 98127.802691 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 103834.080717 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 103834.080717 # average overall miss latency
666,676c676,686
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5805000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 5805000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21528000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7512000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 29040000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 21528000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 13317000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 34845000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 21528000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 13317000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 34845000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5977000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 5977000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 23527000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7886000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 31413000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 23527000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 13863000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 37390000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 23527000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 13863000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 37390000 # number of overall MSHR miss cycles
688,698c698,708
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79520.547945 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79520.547945 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77438.848921 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79073.684211 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77855.227882 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency
705c715
< system.membus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
728,729c738,739
< system.membus.respLayer0.occupancy 2375750 # Layer occupancy (ticks)
< system.membus.respLayer0.utilization 3.8 # Layer utilization (%)
---
> system.membus.respLayer0.occupancy 2377500 # Layer occupancy (ticks)
> system.membus.respLayer0.utilization 3.7 # Layer utilization (%)
< sim_seconds 0.000062 # Number of seconds simulated
< sim_ticks 62213000 # Number of ticks simulated
< final_tick 62213000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000065 # Number of seconds simulated
> sim_ticks 64758000 # Number of ticks simulated
> final_tick 64758000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 276862 # Simulator instruction rate (inst/s)
< host_op_rate 276760 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2667377590 # Simulator tick rate (ticks/s)
< host_mem_usage 639424 # Number of bytes of host memory used
< host_seconds 0.02 # Real time elapsed on the host
---
> host_inst_rate 560678 # Simulator instruction rate (inst/s)
> host_op_rate 559951 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 5612828222 # Simulator tick rate (ticks/s)
> host_mem_usage 638096 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
16c16
< system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.mem_ctrl.bw_read::cpu.inst 285985244 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 172825615 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 458810859 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 285985244 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 285985244 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 285985244 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 172825615 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 458810859 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 274745977 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 166033540 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 440779518 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 274745977 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 274745977 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 274745977 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 166033540 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 440779518 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.mem_ctrl.totGap 61962000 # Total gap between requests
---
> system.mem_ctrl.totGap 64501000 # Total gap between requests
190,204c190,204
< system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::gmean 185.768755 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::stdev 255.860208 # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::0-127 22 23.16% 23.16% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::128-255 36 37.89% 61.05% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::256-383 14 14.74% 75.79% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::384-511 5 5.26% 81.05% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation
< system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation
< system.mem_ctrl.totQLat 3590750 # Total ticks spent queuing
< system.mem_ctrl.totMemAccLat 11953250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.mem_ctrl.bytesPerActivate::samples 105 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::mean 264.533333 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::gmean 181.831163 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::stdev 249.307389 # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::0-127 27 25.71% 25.71% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::128-255 40 38.10% 63.81% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::256-383 10 9.52% 73.33% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::384-511 9 8.57% 81.90% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::512-639 7 6.67% 88.57% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::640-767 6 5.71% 94.29% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::768-895 1 0.95% 95.24% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation
> system.mem_ctrl.bytesPerActivate::total 105 # Bytes accessed per row activation
> system.mem_ctrl.totQLat 6134000 # Total ticks spent queuing
> system.mem_ctrl.totMemAccLat 14496500 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.mem_ctrl.avgQLat 8051.01 # Average queueing delay per DRAM burst
---
> system.mem_ctrl.avgQLat 13753.36 # Average queueing delay per DRAM burst
208,209c208,209
< system.mem_ctrl.avgMemAccLat 26801.01 # Average memory access latency per DRAM burst
< system.mem_ctrl.avgRdBW 458.81 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgMemAccLat 32503.36 # Average memory access latency per DRAM burst
> system.mem_ctrl.avgRdBW 440.78 # Average DRAM read bandwidth in MiByte/s
211c211
< system.mem_ctrl.avgRdBWSys 458.81 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 440.78 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.mem_ctrl.busUtil 3.58 # Data bus utilization in percentage
< system.mem_ctrl.busUtilRead 3.58 # Data bus utilization in percentage for reads
---
> system.mem_ctrl.busUtil 3.44 # Data bus utilization in percentage
> system.mem_ctrl.busUtilRead 3.44 # Data bus utilization in percentage for reads
219c219
< system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads
---
> system.mem_ctrl.readRowHits 337 # Number of row buffer hits during reads
221c221
< system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads
---
> system.mem_ctrl.readRowHitRate 75.56 # Row buffer hit rate for reads
223,227c223,227
< system.mem_ctrl.avgGap 138928.25 # Average gap between requests
< system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined
< system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl.avgGap 144621.08 # Average gap between requests
> system.mem_ctrl.pageHitRate 75.56 # Row buffer hit rate, read and write combined
> system.mem_ctrl_0.actEnergy 314160 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_0.preEnergy 163185 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_0.readEnergy 1542240 # Energy for read commands per rank (pJ)
229,241c229,246
< system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_0.actBackEnergy 37021500 # Energy for active background per rank (pJ)
< system.mem_ctrl_0.preBackEnergy 383250 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_0.totalEnergy 43027155 # Total energy per rank (pJ)
< system.mem_ctrl_0.averagePower 785.686791 # Core power per rank (mW)
< system.mem_ctrl_0.memoryStateTime::IDLE 966000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT 52514000 # Time in different power states
< system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.mem_ctrl_1.actEnergy 370440 # Energy for activate commands per rank (pJ)
< system.mem_ctrl_1.preEnergy 202125 # Energy for precharge commands per rank (pJ)
< system.mem_ctrl_1.readEnergy 1466400 # Energy for read commands per rank (pJ)
---
> system.mem_ctrl_0.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_0.actBackEnergy 3812160 # Energy for active background per rank (pJ)
> system.mem_ctrl_0.preBackEnergy 131040 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_0.actPowerDownEnergy 22575420 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_0.prePowerDownEnergy 2515200 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_0.totalEnergy 35970525 # Total energy per rank (pJ)
> system.mem_ctrl_0.averagePower 555.454282 # Core power per rank (mW)
> system.mem_ctrl_0.totalIdleTime 55623250 # Total Idle time Per DRAM Rank
> system.mem_ctrl_0.memoryStateTime::IDLE 77000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::REF 2080000 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::PRE_PDN 6549500 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT 6531250 # Time in different power states
> system.mem_ctrl_0.memoryStateTime::ACT_PDN 49520250 # Time in different power states
> system.mem_ctrl_1.actEnergy 464100 # Energy for activate commands per rank (pJ)
> system.mem_ctrl_1.preEnergy 235290 # Energy for precharge commands per rank (pJ)
> system.mem_ctrl_1.readEnergy 1642200 # Energy for read commands per rank (pJ)
243,253c248,263
< system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
< system.mem_ctrl_1.actBackEnergy 35989515 # Energy for active background per rank (pJ)
< system.mem_ctrl_1.preBackEnergy 1288500 # Energy for precharge background per rank (pJ)
< system.mem_ctrl_1.totalEnergy 42876900 # Total energy per rank (pJ)
< system.mem_ctrl_1.averagePower 782.943096 # Core power per rank (mW)
< system.mem_ctrl_1.memoryStateTime::IDLE 1815750 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT 51141750 # Time in different power states
< system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.mem_ctrl_1.refreshEnergy 4917120.000000 # Energy for refresh commands per rank (pJ)
> system.mem_ctrl_1.actBackEnergy 4174680 # Energy for active background per rank (pJ)
> system.mem_ctrl_1.preBackEnergy 251520 # Energy for precharge background per rank (pJ)
> system.mem_ctrl_1.actPowerDownEnergy 24338430 # Energy for active power-down per rank (pJ)
> system.mem_ctrl_1.prePowerDownEnergy 604800 # Energy for precharge power-down per rank (pJ)
> system.mem_ctrl_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.mem_ctrl_1.totalEnergy 36628140 # Total energy per rank (pJ)
> system.mem_ctrl_1.averagePower 565.609126 # Core power per rank (mW)
> system.mem_ctrl_1.totalIdleTime 54728750 # Total Idle time Per DRAM Rank
> system.mem_ctrl_1.memoryStateTime::IDLE 283000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::REF 2080000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::SREF 0 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::PRE_PDN 1573250 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT 7457000 # Time in different power states
> system.mem_ctrl_1.memoryStateTime::ACT_PDN 53364750 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
287,288c297,298
< system.cpu.pwrStateResidencyTicks::ON 62213000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 62213 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 64758000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 64758 # number of cpu cycles simulated
307c317
< system.cpu.num_busy_cycles 62213 # Number of busy cycles
---
> system.cpu.num_busy_cycles 64758 # Number of busy cycles
346c356
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
348c358
< system.cpu.dcache.tags.tagsinuse 104.646393 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 104.399751 # Cycle average of tags in use
353,355c363,365
< system.cpu.dcache.tags.occ_blocks::cpu.data 104.646393 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.102194 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.102194 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 104.399751 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.101953 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.101953 # Average percentage of cache occupancy
362c372
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
379,386c389,396
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 9887000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 9887000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 7630000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 7630000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 17517000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 17517000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 17517000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 17517000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10261000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 7802000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 7802000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 18063000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 18063000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 18063000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 18063000 # number of overall miss cycles
403,410c413,420
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 104073.684211 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 104073.684211 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104520.547945 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 104520.547945 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 104267.857143 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 104267.857143 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 104267.857143 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 108010.526316 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 108010.526316 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 106876.712329 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 106876.712329 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 107517.857143 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 107517.857143 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 107517.857143 # average overall miss latency
425,432c435,442
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9697000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 9697000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7484000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 7484000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17181000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 17181000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17181000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 17181000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10071000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 10071000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7656000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 7656000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17727000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 17727000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17727000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 17727000 # number of overall MSHR miss cycles
441,449c451,459
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 102073.684211 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 102073.684211 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102520.547945 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102520.547945 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 102267.857143 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 102267.857143 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 106010.526316 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 106010.526316 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 104876.712329 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 104876.712329 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 105517.857143 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 105517.857143 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
451c461
< system.cpu.icache.tags.tagsinuse 113.718871 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 113.445692 # Cycle average of tags in use
456,458c466,468
< system.cpu.icache.tags.occ_blocks::cpu.inst 113.718871 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.444214 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.444214 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 113.445692 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.443147 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.443147 # Average percentage of cache occupancy
465c475
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
478,483c488,493
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 28558000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 28558000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 28558000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 28558000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 28558000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 28558000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 30557000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 30557000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 30557000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 30557000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 30557000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 30557000 # number of overall miss cycles
496,501c506,511
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101629.893238 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 101629.893238 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 101629.893238 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 101629.893238 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 101629.893238 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 108743.772242 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 108743.772242 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 108743.772242 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 108743.772242 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 108743.772242 # average overall miss latency
514,519c524,529
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27996000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 27996000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27996000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 27996000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27996000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 27996000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29995000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 29995000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29995000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 29995000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29995000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 29995000 # number of overall MSHR miss cycles
526,531c536,541
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99629.893238 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99629.893238 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99629.893238 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 99629.893238 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 106743.772242 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 106743.772242 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 106743.772242 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 106743.772242 # average overall mshr miss latency
538c548
< system.l2bus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.l2bus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
566c576
< system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
---
> system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%)
569c579
< system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
571c581
< system.l2cache.tags.tagsinuse 233.175851 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 232.606847 # Cycle average of tags in use
576,580c586,590
< system.l2cache.tags.occ_blocks::cpu.inst 128.472749 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 104.703102 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.031365 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::cpu.data 0.025562 # Average percentage of cache occupancy
< system.l2cache.tags.occ_percent::total 0.056928 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_blocks::cpu.inst 128.152617 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 104.454231 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.031287 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::cpu.data 0.025502 # Average percentage of cache occupancy
> system.l2cache.tags.occ_percent::total 0.056789 # Average percentage of cache occupancy
587c597
< system.l2cache.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.l2cache.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
605,615c615,625
< system.l2cache.ReadExReq_miss_latency::cpu.data 7265000 # number of ReadExReq miss cycles
< system.l2cache.ReadExReq_miss_latency::total 7265000 # number of ReadExReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.inst 27088000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::cpu.data 9412000 # number of ReadSharedReq miss cycles
< system.l2cache.ReadSharedReq_miss_latency::total 36500000 # number of ReadSharedReq miss cycles
< system.l2cache.demand_miss_latency::cpu.inst 27088000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::cpu.data 16677000 # number of demand (read+write) miss cycles
< system.l2cache.demand_miss_latency::total 43765000 # number of demand (read+write) miss cycles
< system.l2cache.overall_miss_latency::cpu.inst 27088000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::cpu.data 16677000 # number of overall miss cycles
< system.l2cache.overall_miss_latency::total 43765000 # number of overall miss cycles
---
> system.l2cache.ReadExReq_miss_latency::cpu.data 7437000 # number of ReadExReq miss cycles
> system.l2cache.ReadExReq_miss_latency::total 7437000 # number of ReadExReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.inst 29087000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::cpu.data 9786000 # number of ReadSharedReq miss cycles
> system.l2cache.ReadSharedReq_miss_latency::total 38873000 # number of ReadSharedReq miss cycles
> system.l2cache.demand_miss_latency::cpu.inst 29087000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::cpu.data 17223000 # number of demand (read+write) miss cycles
> system.l2cache.demand_miss_latency::total 46310000 # number of demand (read+write) miss cycles
> system.l2cache.overall_miss_latency::cpu.inst 29087000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::cpu.data 17223000 # number of overall miss cycles
> system.l2cache.overall_miss_latency::total 46310000 # number of overall miss cycles
638,648c648,658
< system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99520.547945 # average ReadExReq miss latency
< system.l2cache.ReadExReq_avg_miss_latency::total 99520.547945 # average ReadExReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97438.848921 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99073.684211 # average ReadSharedReq miss latency
< system.l2cache.ReadSharedReq_avg_miss_latency::total 97855.227882 # average ReadSharedReq miss latency
< system.l2cache.demand_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency
< system.l2cache.demand_avg_miss_latency::total 98127.802691 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.inst 97438.848921 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::cpu.data 99267.857143 # average overall miss latency
< system.l2cache.overall_avg_miss_latency::total 98127.802691 # average overall miss latency
---
> system.l2cache.ReadExReq_avg_miss_latency::cpu.data 101876.712329 # average ReadExReq miss latency
> system.l2cache.ReadExReq_avg_miss_latency::total 101876.712329 # average ReadExReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 104629.496403 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103010.526316 # average ReadSharedReq miss latency
> system.l2cache.ReadSharedReq_avg_miss_latency::total 104217.158177 # average ReadSharedReq miss latency
> system.l2cache.demand_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency
> system.l2cache.demand_avg_miss_latency::total 103834.080717 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.inst 104629.496403 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::cpu.data 102517.857143 # average overall miss latency
> system.l2cache.overall_avg_miss_latency::total 103834.080717 # average overall miss latency
666,676c676,686
< system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5805000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadExReq_mshr_miss_latency::total 5805000 # number of ReadExReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21528000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7512000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.ReadSharedReq_mshr_miss_latency::total 29040000 # number of ReadSharedReq MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.inst 21528000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::cpu.data 13317000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.demand_mshr_miss_latency::total 34845000 # number of demand (read+write) MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.inst 21528000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::cpu.data 13317000 # number of overall MSHR miss cycles
< system.l2cache.overall_mshr_miss_latency::total 34845000 # number of overall MSHR miss cycles
---
> system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5977000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadExReq_mshr_miss_latency::total 5977000 # number of ReadExReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 23527000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7886000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.ReadSharedReq_mshr_miss_latency::total 31413000 # number of ReadSharedReq MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.inst 23527000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::cpu.data 13863000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.demand_mshr_miss_latency::total 37390000 # number of demand (read+write) MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.inst 23527000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::cpu.data 13863000 # number of overall MSHR miss cycles
> system.l2cache.overall_mshr_miss_latency::total 37390000 # number of overall MSHR miss cycles
688,698c698,708
< system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79520.547945 # average ReadExReq mshr miss latency
< system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79520.547945 # average ReadExReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77438.848921 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79073.684211 # average ReadSharedReq mshr miss latency
< system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77855.227882 # average ReadSharedReq mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency
< system.l2cache.demand_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77438.848921 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::cpu.data 79267.857143 # average overall mshr miss latency
< system.l2cache.overall_avg_mshr_miss_latency::total 78127.802691 # average overall mshr miss latency
---
> system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 81876.712329 # average ReadExReq mshr miss latency
> system.l2cache.ReadExReq_avg_mshr_miss_latency::total 81876.712329 # average ReadExReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 84629.496403 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 83010.526316 # average ReadSharedReq mshr miss latency
> system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84217.158177 # average ReadSharedReq mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency
> system.l2cache.demand_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 84629.496403 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::cpu.data 82517.857143 # average overall mshr miss latency
> system.l2cache.overall_avg_mshr_miss_latency::total 83834.080717 # average overall mshr miss latency
705c715
< system.membus.pwrStateResidencyTicks::UNDEFINED 62213000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 64758000 # Cumulative time (in ticks) in various power states
728,729c738,739
< system.membus.respLayer0.occupancy 2375750 # Layer occupancy (ticks)
< system.membus.respLayer0.utilization 3.8 # Layer utilization (%)
---
> system.membus.respLayer0.occupancy 2377500 # Layer occupancy (ticks)
> system.membus.respLayer0.utilization 3.7 # Layer utilization (%)