4,5c4,5
< sim_ticks 61608000 # Number of ticks simulated
< final_tick 61608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 61610000 # Number of ticks simulated
> final_tick 61610000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 214452 # Simulator instruction rate (inst/s)
< host_op_rate 214360 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2049936831 # Simulator tick rate (ticks/s)
< host_mem_usage 674692 # Number of bytes of host memory used
< host_seconds 0.03 # Real time elapsed on the host
---
> host_inst_rate 402374 # Simulator instruction rate (inst/s)
> host_op_rate 402048 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 3843418590 # Simulator tick rate (ticks/s)
> host_mem_usage 682268 # Number of bytes of host memory used
> host_seconds 0.02 # Real time elapsed on the host
24,31c24,31
< system.mem_ctrl.bw_read::cpu.inst 288793663 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::cpu.data 174522789 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_read::total 463316452 # Total read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::cpu.inst 288793663 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_inst_read::total 288793663 # Instruction read bandwidth from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.inst 288793663 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::cpu.data 174522789 # Total bandwidth to/from this memory (bytes/s)
< system.mem_ctrl.bw_total::total 463316452 # Total bandwidth to/from this memory (bytes/s)
---
> system.mem_ctrl.bw_read::cpu.inst 288784288 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::cpu.data 174517124 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_read::total 463301412 # Total read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::cpu.inst 288784288 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_inst_read::total 288784288 # Instruction read bandwidth from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.inst 288784288 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::cpu.data 174517124 # Total bandwidth to/from this memory (bytes/s)
> system.mem_ctrl.bw_total::total 463301412 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.mem_ctrl.totGap 61358000 # Total gap between requests
---
> system.mem_ctrl.totGap 61360000 # Total gap between requests
208c208
< system.mem_ctrl.avgRdBW 463.32 # Average DRAM read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBW 463.30 # Average DRAM read bandwidth in MiByte/s
210c210
< system.mem_ctrl.avgRdBWSys 463.32 # Average system read bandwidth in MiByte/s
---
> system.mem_ctrl.avgRdBWSys 463.30 # Average system read bandwidth in MiByte/s
222c222
< system.mem_ctrl.avgGap 137573.99 # Average gap between requests
---
> system.mem_ctrl.avgGap 137578.48 # Average gap between requests
285c285
< system.cpu.numCycles 61608 # number of cpu cycles simulated
---
> system.cpu.numCycles 61610 # number of cpu cycles simulated
304c304
< system.cpu.num_busy_cycles 61608 # Number of busy cycles
---
> system.cpu.num_busy_cycles 61610 # Number of busy cycles
344c344
< system.cpu.dcache.tags.tagsinuse 104.300595 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 104.302306 # Cycle average of tags in use
349,351c349,351
< system.cpu.dcache.tags.occ_blocks::cpu.data 104.300595 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.101856 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.101856 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 104.302306 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.101858 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.101858 # Average percentage of cache occupancy
448c448
< system.cpu.icache.tags.tagsinuse 113.923956 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 113.926978 # Cycle average of tags in use
453,455c453,455
< system.cpu.icache.tags.occ_blocks::cpu.inst 113.923956 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.445015 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.445015 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 113.926978 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.445027 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.445027 # Average percentage of cache occupancy
474,479c474,479
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 28179000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 28179000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 28179000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 28179000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 28179000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 28179000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 28181000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 28181000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 28181000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 28181000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 28181000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 28181000 # number of overall miss cycles
492,497c492,497
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100281.138790 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 100281.138790 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 100281.138790 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 100281.138790 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100288.256228 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 100288.256228 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 100288.256228 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 100288.256228 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 100288.256228 # average overall miss latency
512,517c512,517
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27617000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 27617000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27617000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 27617000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27617000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 27617000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27619000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 27619000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27619000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 27619000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27619000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 27619000 # number of overall MSHR miss cycles
524,529c524,529
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98281.138790 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98281.138790 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98288.256228 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98288.256228 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98288.256228 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 98288.256228 # average overall mshr miss latency
530a531,536
> system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
> system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
544,545c550,551
< system.l2bus.snoop_fanout::mean 1 # Request fanout histogram
< system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.l2bus.snoop_fanout::mean 0.001957 # Request fanout histogram
> system.l2bus.snoop_fanout::stdev 0.044237 # Request fanout histogram
547,548c553,554
< system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.l2bus.snoop_fanout::1 511 100.00% 100.00% # Request fanout histogram
---
> system.l2bus.snoop_fanout::0 510 99.80% 99.80% # Request fanout histogram
> system.l2bus.snoop_fanout::1 1 0.20% 100.00% # Request fanout histogram
551c557
< system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
561c567
< system.l2cache.tags.tagsinuse 185.387550 # Cycle average of tags in use
---
> system.l2cache.tags.tagsinuse 185.392407 # Cycle average of tags in use
566,568c572,574
< system.l2cache.tags.occ_blocks::cpu.inst 128.677366 # Average occupied blocks per requestor
< system.l2cache.tags.occ_blocks::cpu.data 56.710184 # Average occupied blocks per requestor
< system.l2cache.tags.occ_percent::cpu.inst 0.031415 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_blocks::cpu.inst 128.681337 # Average occupied blocks per requestor
> system.l2cache.tags.occ_blocks::cpu.data 56.711070 # Average occupied blocks per requestor
> system.l2cache.tags.occ_percent::cpu.inst 0.031416 # Average percentage of cache occupancy
570c576
< system.l2cache.tags.occ_percent::total 0.045261 # Average percentage of cache occupancy
---
> system.l2cache.tags.occ_percent::total 0.045262 # Average percentage of cache occupancy