Cross Reference: /gem5/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt

stats.txt (11390:f40859930028)	stats.txt (11456:c0fb4435b80f)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000061 # Number of seconds simulated 4sim_ticks 61470000 # Number of ticks simulated 5final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000061 # Number of seconds simulated 4sim_ticks 61470000 # Number of ticks simulated 5final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 62593 # Simulator instruction rate (inst/s) 8host_op_rate 62569 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 595804848 # Simulator tick rate (ticks/s) 10host_mem_usage 614668 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host	7host_inst_rate 583425 # Simulator instruction rate (inst/s) 8host_op_rate 580281 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 5518802940 # Simulator tick rate (ticks/s) 10host_mem_usage 637904 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 6453 # Number of instructions simulated 13sim_ops 6453 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 21system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 22system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory 24system.mem_ctrl.bw_read::cpu.inst 289442004 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrl.bw_read::cpu.data 174914592 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::total 464356597 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_inst_read::cpu.inst 289442004 # Instruction read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::total 289442004 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_total::cpu.inst 289442004 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.data 174914592 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::total 464356597 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.readReqs 446 # Number of read requests accepted 33system.mem_ctrl.writeReqs 0 # Number of write requests accepted 34system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue 35system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM 37system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 39system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side 40system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.mem_ctrl.perBankRdBursts::0 62 # Per bank write bursts 45system.mem_ctrl.perBankRdBursts::1 26 # Per bank write bursts 46system.mem_ctrl.perBankRdBursts::2 24 # Per bank write bursts 47system.mem_ctrl.perBankRdBursts::3 43 # Per bank write bursts 48system.mem_ctrl.perBankRdBursts::4 40 # Per bank write bursts 49system.mem_ctrl.perBankRdBursts::5 17 # Per bank write bursts 50system.mem_ctrl.perBankRdBursts::6 1 # Per bank write bursts 51system.mem_ctrl.perBankRdBursts::7 3 # Per bank write bursts 52system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts 53system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts 54system.mem_ctrl.perBankRdBursts::10 19 # Per bank write bursts 55system.mem_ctrl.perBankRdBursts::11 23 # Per bank write bursts 56system.mem_ctrl.perBankRdBursts::12 14 # Per bank write bursts 57system.mem_ctrl.perBankRdBursts::13 116 # Per bank write bursts 58system.mem_ctrl.perBankRdBursts::14 45 # Per bank write bursts 59system.mem_ctrl.perBankRdBursts::15 12 # Per bank write bursts 60system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts 61system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts 62system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts 63system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts 64system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts 65system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts 66system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts 67system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts 68system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts 69system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts 70system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 76system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 77system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry 78system.mem_ctrl.totGap 61220000 # Total gap between requests 79system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 80system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2) 86system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) 87system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) 88system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) 89system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) 90system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) 91system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) 92system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) 93system.mem_ctrl.rdQLenPdf::0 446 # What read queue length does an incoming req see 94system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see 95system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see 96system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation 190system.mem_ctrl.bytesPerActivate::mean 270.821053 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::gmean 180.792132 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::stdev 259.793616 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::0-127 28 29.47% 29.47% # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::128-255 29 30.53% 60.00% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::256-383 12 12.63% 72.63% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::384-511 9 9.47% 82.11% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::512-639 5 5.26% 87.37% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation 202system.mem_ctrl.totQLat 3294500 # Total ticks spent queuing 203system.mem_ctrl.totMemAccLat 11657000 # Total ticks spent from burst creation until serviced by the DRAM 204system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers 205system.mem_ctrl.avgQLat 7386.77 # Average queueing delay per DRAM burst 206system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst 207system.mem_ctrl.avgMemAccLat 26136.77 # Average memory access latency per DRAM burst 208system.mem_ctrl.avgRdBW 464.36 # Average DRAM read bandwidth in MiByte/s 209system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.mem_ctrl.avgRdBWSys 464.36 # Average system read bandwidth in MiByte/s 211system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.mem_ctrl.busUtil 3.63 # Data bus utilization in percentage 214system.mem_ctrl.busUtilRead 3.63 # Data bus utilization in percentage for reads 215system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 216system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 217system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.mem_ctrl.readRowHits 341 # Number of row buffer hits during reads 219system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 220system.mem_ctrl.readRowHitRate 76.46 # Row buffer hit rate for reads 221system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 222system.mem_ctrl.avgGap 137264.57 # Average gap between requests 223system.mem_ctrl.pageHitRate 76.46 # Row buffer hit rate, read and write combined 224system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 225system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 226system.mem_ctrl_0.readEnergy 1591200 # Energy for read commands per rank (pJ) 227system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 229system.mem_ctrl_0.actBackEnergy 37059120 # Energy for active background per rank (pJ) 230system.mem_ctrl_0.preBackEnergy 350250 # Energy for precharge background per rank (pJ) 231system.mem_ctrl_0.totalEnergy 43039575 # Total energy per rank (pJ) 232system.mem_ctrl_0.averagePower 785.913583 # Core power per rank (mW) 233system.mem_ctrl_0.memoryStateTime::IDLE 388750 # Time in different power states 234system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states 235system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states 236system.mem_ctrl_0.memoryStateTime::ACT 52568750 # Time in different power states 237system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 238system.mem_ctrl_1.actEnergy 385560 # Energy for activate commands per rank (pJ) 239system.mem_ctrl_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) 240system.mem_ctrl_1.readEnergy 1489800 # Energy for read commands per rank (pJ) 241system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 243system.mem_ctrl_1.actBackEnergy 35948475 # Energy for active background per rank (pJ) 244system.mem_ctrl_1.preBackEnergy 1324500 # Energy for precharge background per rank (pJ) 245system.mem_ctrl_1.totalEnergy 42918630 # Total energy per rank (pJ) 246system.mem_ctrl_1.averagePower 783.705097 # Core power per rank (mW) 247system.mem_ctrl_1.memoryStateTime::IDLE 2128500 # Time in different power states 248system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 252system.cpu.dtb.fetch_hits 0 # ITB hits 253system.cpu.dtb.fetch_misses 0 # ITB misses 254system.cpu.dtb.fetch_acv 0 # ITB acv 255system.cpu.dtb.fetch_accesses 0 # ITB accesses 256system.cpu.dtb.read_hits 1190 # DTB read hits 257system.cpu.dtb.read_misses 7 # DTB read misses 258system.cpu.dtb.read_acv 0 # DTB read access violations 259system.cpu.dtb.read_accesses 1197 # DTB read accesses 260system.cpu.dtb.write_hits 865 # DTB write hits 261system.cpu.dtb.write_misses 3 # DTB write misses 262system.cpu.dtb.write_acv 0 # DTB write access violations 263system.cpu.dtb.write_accesses 868 # DTB write accesses 264system.cpu.dtb.data_hits 2055 # DTB hits 265system.cpu.dtb.data_misses 10 # DTB misses 266system.cpu.dtb.data_acv 0 # DTB access violations 267system.cpu.dtb.data_accesses 2065 # DTB accesses 268system.cpu.itb.fetch_hits 6464 # ITB hits 269system.cpu.itb.fetch_misses 17 # ITB misses 270system.cpu.itb.fetch_acv 0 # ITB acv 271system.cpu.itb.fetch_accesses 6481 # ITB accesses 272system.cpu.itb.read_hits 0 # DTB read hits 273system.cpu.itb.read_misses 0 # DTB read misses 274system.cpu.itb.read_acv 0 # DTB read access violations 275system.cpu.itb.read_accesses 0 # DTB read accesses 276system.cpu.itb.write_hits 0 # DTB write hits 277system.cpu.itb.write_misses 0 # DTB write misses 278system.cpu.itb.write_acv 0 # DTB write access violations 279system.cpu.itb.write_accesses 0 # DTB write accesses 280system.cpu.itb.data_hits 0 # DTB hits 281system.cpu.itb.data_misses 0 # DTB misses 282system.cpu.itb.data_acv 0 # DTB access violations 283system.cpu.itb.data_accesses 0 # DTB accesses 284system.cpu.workload.num_syscalls 17 # Number of system calls 285system.cpu.numCycles 61470 # number of cpu cycles simulated 286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 288system.cpu.committedInsts 6453 # Number of instructions committed 289system.cpu.committedOps 6453 # Number of ops (including micro ops) committed 290system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses 291system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 292system.cpu.num_func_calls 251 # number of times a function call or return occured 293system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls 294system.cpu.num_int_insts 6380 # number of integer instructions 295system.cpu.num_fp_insts 10 # number of float instructions 296system.cpu.num_int_register_reads 8392 # number of times the integer registers were read 297system.cpu.num_int_register_writes 4621 # number of times the integer registers were written 298system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 299system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 300system.cpu.num_mem_refs 2065 # number of memory refs 301system.cpu.num_load_insts 1197 # Number of load instructions 302system.cpu.num_store_insts 868 # Number of store instructions 303system.cpu.num_idle_cycles 0 # Number of idle cycles 304system.cpu.num_busy_cycles 61470 # Number of busy cycles 305system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 306system.cpu.idle_fraction 0 # Percentage of idle cycles 307system.cpu.Branches 1060 # Number of branches fetched 308system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction 309system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction 310system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction 311system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction 312system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction 313system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction 314system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction 315system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction 316system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction 317system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction 318system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction 319system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction 320system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction 321system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction 322system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction 323system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction 324system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction 325system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction 326system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction 327system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction 328system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction 329system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction 330system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction 331system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction 332system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction 333system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction 334system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction 335system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction 336system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction 337system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction 338system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction 339system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction 340system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 341system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 342system.cpu.op_class::total 6463 # Class of executed instruction 343system.cpu.dcache.tags.replacements 0 # number of replacements 344system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use 345system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. 346system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 347system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. 348system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 349system.cpu.dcache.tags.occ_blocks::cpu.data 104.645861 # Average occupied blocks per requestor 350system.cpu.dcache.tags.occ_percent::cpu.data 0.102193 # Average percentage of cache occupancy 351system.cpu.dcache.tags.occ_percent::total 0.102193 # Average percentage of cache occupancy 352system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 353system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 354system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 355system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id 356system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses 357system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses 358system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits 359system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits 360system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 361system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 362system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits 363system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits 364system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits 365system.cpu.dcache.overall_hits::total 1887 # number of overall hits 366system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 367system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 368system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 369system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 370system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 371system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 372system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 373system.cpu.dcache.overall_misses::total 168 # number of overall misses 374system.cpu.dcache.ReadReq_miss_latency::cpu.data 10102000 # number of ReadReq miss cycles 375system.cpu.dcache.ReadReq_miss_latency::total 10102000 # number of ReadReq miss cycles 376system.cpu.dcache.WriteReq_miss_latency::cpu.data 7278000 # number of WriteReq miss cycles 377system.cpu.dcache.WriteReq_miss_latency::total 7278000 # number of WriteReq miss cycles 378system.cpu.dcache.demand_miss_latency::cpu.data 17380000 # number of demand (read+write) miss cycles 379system.cpu.dcache.demand_miss_latency::total 17380000 # number of demand (read+write) miss cycles 380system.cpu.dcache.overall_miss_latency::cpu.data 17380000 # number of overall miss cycles 381system.cpu.dcache.overall_miss_latency::total 17380000 # number of overall miss cycles 382system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) 383system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) 384system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 385system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 386system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses 387system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses 388system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses 389system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses 390system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses 391system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses 392system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 393system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 394system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses 395system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses 396system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses 397system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses 398system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 106336.842105 # average ReadReq miss latency 399system.cpu.dcache.ReadReq_avg_miss_latency::total 106336.842105 # average ReadReq miss latency 400system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99698.630137 # average WriteReq miss latency 401system.cpu.dcache.WriteReq_avg_miss_latency::total 99698.630137 # average WriteReq miss latency 402system.cpu.dcache.demand_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency 403system.cpu.dcache.demand_avg_miss_latency::total 103452.380952 # average overall miss latency 404system.cpu.dcache.overall_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency 405system.cpu.dcache.overall_avg_miss_latency::total 103452.380952 # average overall miss latency 406system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 407system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 408system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 409system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 410system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 411system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	12sim_insts 6453 # Number of instructions simulated 13sim_ops 6453 # Number of ops (including micro ops) simulated 14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory 17system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory 18system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory 19system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory 20system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory 21system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory 22system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory 23system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory 24system.mem_ctrl.bw_read::cpu.inst 289442004 # Total read bandwidth from this memory (bytes/s) 25system.mem_ctrl.bw_read::cpu.data 174914592 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrl.bw_read::total 464356597 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrl.bw_inst_read::cpu.inst 289442004 # Instruction read bandwidth from this memory (bytes/s) 28system.mem_ctrl.bw_inst_read::total 289442004 # Instruction read bandwidth from this memory (bytes/s) 29system.mem_ctrl.bw_total::cpu.inst 289442004 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrl.bw_total::cpu.data 174914592 # Total bandwidth to/from this memory (bytes/s) 31system.mem_ctrl.bw_total::total 464356597 # Total bandwidth to/from this memory (bytes/s) 32system.mem_ctrl.readReqs 446 # Number of read requests accepted 33system.mem_ctrl.writeReqs 0 # Number of write requests accepted 34system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue 35system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM 37system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM 39system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side 40system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.mem_ctrl.perBankRdBursts::0 62 # Per bank write bursts 45system.mem_ctrl.perBankRdBursts::1 26 # Per bank write bursts 46system.mem_ctrl.perBankRdBursts::2 24 # Per bank write bursts 47system.mem_ctrl.perBankRdBursts::3 43 # Per bank write bursts 48system.mem_ctrl.perBankRdBursts::4 40 # Per bank write bursts 49system.mem_ctrl.perBankRdBursts::5 17 # Per bank write bursts 50system.mem_ctrl.perBankRdBursts::6 1 # Per bank write bursts 51system.mem_ctrl.perBankRdBursts::7 3 # Per bank write bursts 52system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts 53system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts 54system.mem_ctrl.perBankRdBursts::10 19 # Per bank write bursts 55system.mem_ctrl.perBankRdBursts::11 23 # Per bank write bursts 56system.mem_ctrl.perBankRdBursts::12 14 # Per bank write bursts 57system.mem_ctrl.perBankRdBursts::13 116 # Per bank write bursts 58system.mem_ctrl.perBankRdBursts::14 45 # Per bank write bursts 59system.mem_ctrl.perBankRdBursts::15 12 # Per bank write bursts 60system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts 61system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts 62system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts 63system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts 64system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts 65system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts 66system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts 67system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts 68system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts 69system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts 70system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts 71system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts 72system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts 73system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts 74system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts 75system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts 76system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry 77system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry 78system.mem_ctrl.totGap 61220000 # Total gap between requests 79system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) 80system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) 81system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) 82system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) 83system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) 84system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) 85system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2) 86system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) 87system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) 88system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) 89system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) 90system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) 91system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) 92system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) 93system.mem_ctrl.rdQLenPdf::0 446 # What read queue length does an incoming req see 94system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see 95system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see 96system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see 97system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see 98system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation 190system.mem_ctrl.bytesPerActivate::mean 270.821053 # Bytes accessed per row activation 191system.mem_ctrl.bytesPerActivate::gmean 180.792132 # Bytes accessed per row activation 192system.mem_ctrl.bytesPerActivate::stdev 259.793616 # Bytes accessed per row activation 193system.mem_ctrl.bytesPerActivate::0-127 28 29.47% 29.47% # Bytes accessed per row activation 194system.mem_ctrl.bytesPerActivate::128-255 29 30.53% 60.00% # Bytes accessed per row activation 195system.mem_ctrl.bytesPerActivate::256-383 12 12.63% 72.63% # Bytes accessed per row activation 196system.mem_ctrl.bytesPerActivate::384-511 9 9.47% 82.11% # Bytes accessed per row activation 197system.mem_ctrl.bytesPerActivate::512-639 5 5.26% 87.37% # Bytes accessed per row activation 198system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation 199system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation 200system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation 201system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation 202system.mem_ctrl.totQLat 3294500 # Total ticks spent queuing 203system.mem_ctrl.totMemAccLat 11657000 # Total ticks spent from burst creation until serviced by the DRAM 204system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers 205system.mem_ctrl.avgQLat 7386.77 # Average queueing delay per DRAM burst 206system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst 207system.mem_ctrl.avgMemAccLat 26136.77 # Average memory access latency per DRAM burst 208system.mem_ctrl.avgRdBW 464.36 # Average DRAM read bandwidth in MiByte/s 209system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.mem_ctrl.avgRdBWSys 464.36 # Average system read bandwidth in MiByte/s 211system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.mem_ctrl.busUtil 3.63 # Data bus utilization in percentage 214system.mem_ctrl.busUtilRead 3.63 # Data bus utilization in percentage for reads 215system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes 216system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing 217system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing 218system.mem_ctrl.readRowHits 341 # Number of row buffer hits during reads 219system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes 220system.mem_ctrl.readRowHitRate 76.46 # Row buffer hit rate for reads 221system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes 222system.mem_ctrl.avgGap 137264.57 # Average gap between requests 223system.mem_ctrl.pageHitRate 76.46 # Row buffer hit rate, read and write combined 224system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ) 225system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) 226system.mem_ctrl_0.readEnergy 1591200 # Energy for read commands per rank (pJ) 227system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) 228system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 229system.mem_ctrl_0.actBackEnergy 37059120 # Energy for active background per rank (pJ) 230system.mem_ctrl_0.preBackEnergy 350250 # Energy for precharge background per rank (pJ) 231system.mem_ctrl_0.totalEnergy 43039575 # Total energy per rank (pJ) 232system.mem_ctrl_0.averagePower 785.913583 # Core power per rank (mW) 233system.mem_ctrl_0.memoryStateTime::IDLE 388750 # Time in different power states 234system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states 235system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states 236system.mem_ctrl_0.memoryStateTime::ACT 52568750 # Time in different power states 237system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states 238system.mem_ctrl_1.actEnergy 385560 # Energy for activate commands per rank (pJ) 239system.mem_ctrl_1.preEnergy 210375 # Energy for precharge commands per rank (pJ) 240system.mem_ctrl_1.readEnergy 1489800 # Energy for read commands per rank (pJ) 241system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) 242system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) 243system.mem_ctrl_1.actBackEnergy 35948475 # Energy for active background per rank (pJ) 244system.mem_ctrl_1.preBackEnergy 1324500 # Energy for precharge background per rank (pJ) 245system.mem_ctrl_1.totalEnergy 42918630 # Total energy per rank (pJ) 246system.mem_ctrl_1.averagePower 783.705097 # Core power per rank (mW) 247system.mem_ctrl_1.memoryStateTime::IDLE 2128500 # Time in different power states 248system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states 249system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states 251system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states 252system.cpu.dtb.fetch_hits 0 # ITB hits 253system.cpu.dtb.fetch_misses 0 # ITB misses 254system.cpu.dtb.fetch_acv 0 # ITB acv 255system.cpu.dtb.fetch_accesses 0 # ITB accesses 256system.cpu.dtb.read_hits 1190 # DTB read hits 257system.cpu.dtb.read_misses 7 # DTB read misses 258system.cpu.dtb.read_acv 0 # DTB read access violations 259system.cpu.dtb.read_accesses 1197 # DTB read accesses 260system.cpu.dtb.write_hits 865 # DTB write hits 261system.cpu.dtb.write_misses 3 # DTB write misses 262system.cpu.dtb.write_acv 0 # DTB write access violations 263system.cpu.dtb.write_accesses 868 # DTB write accesses 264system.cpu.dtb.data_hits 2055 # DTB hits 265system.cpu.dtb.data_misses 10 # DTB misses 266system.cpu.dtb.data_acv 0 # DTB access violations 267system.cpu.dtb.data_accesses 2065 # DTB accesses 268system.cpu.itb.fetch_hits 6464 # ITB hits 269system.cpu.itb.fetch_misses 17 # ITB misses 270system.cpu.itb.fetch_acv 0 # ITB acv 271system.cpu.itb.fetch_accesses 6481 # ITB accesses 272system.cpu.itb.read_hits 0 # DTB read hits 273system.cpu.itb.read_misses 0 # DTB read misses 274system.cpu.itb.read_acv 0 # DTB read access violations 275system.cpu.itb.read_accesses 0 # DTB read accesses 276system.cpu.itb.write_hits 0 # DTB write hits 277system.cpu.itb.write_misses 0 # DTB write misses 278system.cpu.itb.write_acv 0 # DTB write access violations 279system.cpu.itb.write_accesses 0 # DTB write accesses 280system.cpu.itb.data_hits 0 # DTB hits 281system.cpu.itb.data_misses 0 # DTB misses 282system.cpu.itb.data_acv 0 # DTB access violations 283system.cpu.itb.data_accesses 0 # DTB accesses 284system.cpu.workload.num_syscalls 17 # Number of system calls 285system.cpu.numCycles 61470 # number of cpu cycles simulated 286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 288system.cpu.committedInsts 6453 # Number of instructions committed 289system.cpu.committedOps 6453 # Number of ops (including micro ops) committed 290system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses 291system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses 292system.cpu.num_func_calls 251 # number of times a function call or return occured 293system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls 294system.cpu.num_int_insts 6380 # number of integer instructions 295system.cpu.num_fp_insts 10 # number of float instructions 296system.cpu.num_int_register_reads 8392 # number of times the integer registers were read 297system.cpu.num_int_register_writes 4621 # number of times the integer registers were written 298system.cpu.num_fp_register_reads 8 # number of times the floating registers were read 299system.cpu.num_fp_register_writes 2 # number of times the floating registers were written 300system.cpu.num_mem_refs 2065 # number of memory refs 301system.cpu.num_load_insts 1197 # Number of load instructions 302system.cpu.num_store_insts 868 # Number of store instructions 303system.cpu.num_idle_cycles 0 # Number of idle cycles 304system.cpu.num_busy_cycles 61470 # Number of busy cycles 305system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 306system.cpu.idle_fraction 0 # Percentage of idle cycles 307system.cpu.Branches 1060 # Number of branches fetched 308system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction 309system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction 310system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction 311system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction 312system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction 313system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction 314system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction 315system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction 316system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction 317system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction 318system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction 319system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction 320system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction 321system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction 322system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction 323system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction 324system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction 325system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction 326system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction 327system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction 328system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction 329system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction 330system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction 331system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction 332system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction 333system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction 334system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction 335system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction 336system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction 337system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction 338system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction 339system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction 340system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 341system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 342system.cpu.op_class::total 6463 # Class of executed instruction 343system.cpu.dcache.tags.replacements 0 # number of replacements 344system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use 345system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks. 346system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. 347system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks. 348system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 349system.cpu.dcache.tags.occ_blocks::cpu.data 104.645861 # Average occupied blocks per requestor 350system.cpu.dcache.tags.occ_percent::cpu.data 0.102193 # Average percentage of cache occupancy 351system.cpu.dcache.tags.occ_percent::total 0.102193 # Average percentage of cache occupancy 352system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id 353system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id 354system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id 355system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id 356system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses 357system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses 358system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits 359system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits 360system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits 361system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits 362system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits 363system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits 364system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits 365system.cpu.dcache.overall_hits::total 1887 # number of overall hits 366system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses 367system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses 368system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses 369system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses 370system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses 371system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses 372system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses 373system.cpu.dcache.overall_misses::total 168 # number of overall misses 374system.cpu.dcache.ReadReq_miss_latency::cpu.data 10102000 # number of ReadReq miss cycles 375system.cpu.dcache.ReadReq_miss_latency::total 10102000 # number of ReadReq miss cycles 376system.cpu.dcache.WriteReq_miss_latency::cpu.data 7278000 # number of WriteReq miss cycles 377system.cpu.dcache.WriteReq_miss_latency::total 7278000 # number of WriteReq miss cycles 378system.cpu.dcache.demand_miss_latency::cpu.data 17380000 # number of demand (read+write) miss cycles 379system.cpu.dcache.demand_miss_latency::total 17380000 # number of demand (read+write) miss cycles 380system.cpu.dcache.overall_miss_latency::cpu.data 17380000 # number of overall miss cycles 381system.cpu.dcache.overall_miss_latency::total 17380000 # number of overall miss cycles 382system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses) 383system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses) 384system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 385system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 386system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses 387system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses 388system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses 389system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses 390system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses 391system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses 392system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses 393system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses 394system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses 395system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses 396system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses 397system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses 398system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 106336.842105 # average ReadReq miss latency 399system.cpu.dcache.ReadReq_avg_miss_latency::total 106336.842105 # average ReadReq miss latency 400system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99698.630137 # average WriteReq miss latency 401system.cpu.dcache.WriteReq_avg_miss_latency::total 99698.630137 # average WriteReq miss latency 402system.cpu.dcache.demand_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency 403system.cpu.dcache.demand_avg_miss_latency::total 103452.380952 # average overall miss latency 404system.cpu.dcache.overall_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency 405system.cpu.dcache.overall_avg_miss_latency::total 103452.380952 # average overall miss latency 406system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 407system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 408system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 409system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 410system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 411system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
412system.cpu.dcache.fast_writes 0 # number of fast writes performed 413system.cpu.dcache.cache_copies 0 # number of cache copies performed
414system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 415system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 416system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 417system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 418system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 419system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 420system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 421system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 422system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9912000 # number of ReadReq MSHR miss cycles 423system.cpu.dcache.ReadReq_mshr_miss_latency::total 9912000 # number of ReadReq MSHR miss cycles 424system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7132000 # number of WriteReq MSHR miss cycles 425system.cpu.dcache.WriteReq_mshr_miss_latency::total 7132000 # number of WriteReq MSHR miss cycles 426system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17044000 # number of demand (read+write) MSHR miss cycles 427system.cpu.dcache.demand_mshr_miss_latency::total 17044000 # number of demand (read+write) MSHR miss cycles 428system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17044000 # number of overall MSHR miss cycles 429system.cpu.dcache.overall_mshr_miss_latency::total 17044000 # number of overall MSHR miss cycles 430system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses 431system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses 432system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 433system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 434system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses 435system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses 436system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses 437system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses 438system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency 439system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency 440system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency 441system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency 442system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 443system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency 444system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 445system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency	412system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses 413system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses 414system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 415system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 416system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 417system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses 418system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 419system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses 420system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9912000 # number of ReadReq MSHR miss cycles 421system.cpu.dcache.ReadReq_mshr_miss_latency::total 9912000 # number of ReadReq MSHR miss cycles 422system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7132000 # number of WriteReq MSHR miss cycles 423system.cpu.dcache.WriteReq_mshr_miss_latency::total 7132000 # number of WriteReq MSHR miss cycles 424system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17044000 # number of demand (read+write) MSHR miss cycles 425system.cpu.dcache.demand_mshr_miss_latency::total 17044000 # number of demand (read+write) MSHR miss cycles 426system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17044000 # number of overall MSHR miss cycles 427system.cpu.dcache.overall_mshr_miss_latency::total 17044000 # number of overall MSHR miss cycles 428system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses 429system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses 430system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses 431system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses 432system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses 433system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses 434system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses 435system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses 436system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency 437system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency 438system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency 439system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency 440system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 441system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency 442system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency 443system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
446system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
447system.cpu.icache.tags.replacements 62 # number of replacements 448system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use 449system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 450system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 451system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 452system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 453system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor 454system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy 455system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy 456system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id 457system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 458system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 459system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id 460system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses 461system.cpu.icache.tags.data_accesses 13209 # Number of data accesses 462system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits 463system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits 464system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits 465system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits 466system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits 467system.cpu.icache.overall_hits::total 6183 # number of overall hits 468system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses 469system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses 470system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses 471system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses 472system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses 473system.cpu.icache.overall_misses::total 281 # number of overall misses 474system.cpu.icache.ReadReq_miss_latency::cpu.inst 27952000 # number of ReadReq miss cycles 475system.cpu.icache.ReadReq_miss_latency::total 27952000 # number of ReadReq miss cycles 476system.cpu.icache.demand_miss_latency::cpu.inst 27952000 # number of demand (read+write) miss cycles 477system.cpu.icache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles 478system.cpu.icache.overall_miss_latency::cpu.inst 27952000 # number of overall miss cycles 479system.cpu.icache.overall_miss_latency::total 27952000 # number of overall miss cycles 480system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) 481system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) 482system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses 483system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses 484system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses 485system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses 486system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses 487system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses 488system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses 489system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses 490system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses 491system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses 492system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 99473.309609 # average ReadReq miss latency 493system.cpu.icache.ReadReq_avg_miss_latency::total 99473.309609 # average ReadReq miss latency 494system.cpu.icache.demand_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency 495system.cpu.icache.demand_avg_miss_latency::total 99473.309609 # average overall miss latency 496system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency 497system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency 498system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 499system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 500system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 501system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 502system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 503system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	444system.cpu.icache.tags.replacements 62 # number of replacements 445system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use 446system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks. 447system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. 448system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks. 449system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 450system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor 451system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy 452system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy 453system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id 454system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 455system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id 456system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id 457system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses 458system.cpu.icache.tags.data_accesses 13209 # Number of data accesses 459system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits 460system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits 461system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits 462system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits 463system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits 464system.cpu.icache.overall_hits::total 6183 # number of overall hits 465system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses 466system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses 467system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses 468system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses 469system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses 470system.cpu.icache.overall_misses::total 281 # number of overall misses 471system.cpu.icache.ReadReq_miss_latency::cpu.inst 27952000 # number of ReadReq miss cycles 472system.cpu.icache.ReadReq_miss_latency::total 27952000 # number of ReadReq miss cycles 473system.cpu.icache.demand_miss_latency::cpu.inst 27952000 # number of demand (read+write) miss cycles 474system.cpu.icache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles 475system.cpu.icache.overall_miss_latency::cpu.inst 27952000 # number of overall miss cycles 476system.cpu.icache.overall_miss_latency::total 27952000 # number of overall miss cycles 477system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses) 478system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses) 479system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses 480system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses 481system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses 482system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses 483system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses 484system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses 485system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses 486system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses 487system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses 488system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses 489system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 99473.309609 # average ReadReq miss latency 490system.cpu.icache.ReadReq_avg_miss_latency::total 99473.309609 # average ReadReq miss latency 491system.cpu.icache.demand_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency 492system.cpu.icache.demand_avg_miss_latency::total 99473.309609 # average overall miss latency 493system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency 494system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency 495system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 496system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 497system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 498system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 499system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 500system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
504system.cpu.icache.fast_writes 0 # number of fast writes performed 505system.cpu.icache.cache_copies 0 # number of cache copies performed
506system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses 507system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses 508system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses 509system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses 510system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses 511system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses 512system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles 513system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles 514system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27390000 # number of demand (read+write) MSHR miss cycles 515system.cpu.icache.demand_mshr_miss_latency::total 27390000 # number of demand (read+write) MSHR miss cycles 516system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27390000 # number of overall MSHR miss cycles 517system.cpu.icache.overall_mshr_miss_latency::total 27390000 # number of overall MSHR miss cycles 518system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses 519system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses 520system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses 521system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses 522system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses 523system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses 524system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency 525system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency 526system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency 527system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency 528system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency 529system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency	501system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses 502system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses 503system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses 504system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses 505system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses 506system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses 507system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles 508system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles 509system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27390000 # number of demand (read+write) MSHR miss cycles 510system.cpu.icache.demand_mshr_miss_latency::total 27390000 # number of demand (read+write) MSHR miss cycles 511system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27390000 # number of overall MSHR miss cycles 512system.cpu.icache.overall_mshr_miss_latency::total 27390000 # number of overall MSHR miss cycles 513system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses 514system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses 515system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses 516system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses 517system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses 518system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses 519system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency 520system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency 521system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency 522system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency 523system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency 524system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency
530system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
531system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 532system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 533system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 534system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 535system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 536system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 537system.l2bus.trans_dist::ReadResp 376 # Transaction distribution 538system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution 539system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution 540system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution 541system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution 542system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) 543system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 544system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 545system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes) 546system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 547system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) 548system.l2bus.snoops 0 # Total snoops (count) 549system.l2bus.snoop_fanout::samples 449 # Request fanout histogram 550system.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram 551system.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram 552system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 553system.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram 554system.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram 555system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 556system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 557system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 558system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 559system.l2bus.snoop_fanout::total 449 # Request fanout histogram 560system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) 561system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 562system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) 563system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) 564system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) 565system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) 566system.l2cache.tags.replacements 0 # number of replacements 567system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use 568system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. 569system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 570system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks. 571system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 572system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor 573system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor 574system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy 575system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy 576system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy 577system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 578system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 579system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 580system.l2cache.tags.occ_task_id_percent::1024 0.091064 # Percentage of cache occupancy per task id 581system.l2cache.tags.tag_accesses 4534 # Number of tag accesses 582system.l2cache.tags.data_accesses 4534 # Number of data accesses 583system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits 584system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 585system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 586system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 587system.l2cache.overall_hits::cpu.inst 3 # number of overall hits 588system.l2cache.overall_hits::total 3 # number of overall hits 589system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 590system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 591system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses 592system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses 593system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses 594system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 595system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 596system.l2cache.demand_misses::total 446 # number of demand (read+write) misses 597system.l2cache.overall_misses::cpu.inst 278 # number of overall misses 598system.l2cache.overall_misses::cpu.data 168 # number of overall misses 599system.l2cache.overall_misses::total 446 # number of overall misses 600system.l2cache.ReadExReq_miss_latency::cpu.data 6913000 # number of ReadExReq miss cycles 601system.l2cache.ReadExReq_miss_latency::total 6913000 # number of ReadExReq miss cycles 602system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26482000 # number of ReadSharedReq miss cycles 603system.l2cache.ReadSharedReq_miss_latency::cpu.data 9627000 # number of ReadSharedReq miss cycles 604system.l2cache.ReadSharedReq_miss_latency::total 36109000 # number of ReadSharedReq miss cycles 605system.l2cache.demand_miss_latency::cpu.inst 26482000 # number of demand (read+write) miss cycles 606system.l2cache.demand_miss_latency::cpu.data 16540000 # number of demand (read+write) miss cycles 607system.l2cache.demand_miss_latency::total 43022000 # number of demand (read+write) miss cycles 608system.l2cache.overall_miss_latency::cpu.inst 26482000 # number of overall miss cycles 609system.l2cache.overall_miss_latency::cpu.data 16540000 # number of overall miss cycles 610system.l2cache.overall_miss_latency::total 43022000 # number of overall miss cycles 611system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 612system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 613system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) 614system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) 615system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses) 616system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses 617system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 618system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses 619system.l2cache.overall_accesses::cpu.inst 281 # number of overall (read+write) accesses 620system.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 621system.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses 622system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 623system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 624system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.989324 # miss rate for ReadSharedReq accesses 625system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 626system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses 627system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses 628system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 629system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses 630system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses 631system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 632system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses 633system.l2cache.ReadExReq_avg_miss_latency::cpu.data 94698.630137 # average ReadExReq miss latency 634system.l2cache.ReadExReq_avg_miss_latency::total 94698.630137 # average ReadExReq miss latency 635system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 95258.992806 # average ReadSharedReq miss latency 636system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101336.842105 # average ReadSharedReq miss latency 637system.l2cache.ReadSharedReq_avg_miss_latency::total 96806.970509 # average ReadSharedReq miss latency 638system.l2cache.demand_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency 639system.l2cache.demand_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency 640system.l2cache.demand_avg_miss_latency::total 96461.883408 # average overall miss latency 641system.l2cache.overall_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency 642system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency 643system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency 644system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 645system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 647system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 648system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 649system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked	525system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter. 526system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data. 527system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 528system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 529system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 530system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 531system.l2bus.trans_dist::ReadResp 376 # Transaction distribution 532system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution 533system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution 534system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution 535system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution 536system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) 537system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) 538system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 539system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes) 540system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) 541system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) 542system.l2bus.snoops 0 # Total snoops (count) 543system.l2bus.snoop_fanout::samples 449 # Request fanout histogram 544system.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram 545system.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram 546system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 547system.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram 548system.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram 549system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 550system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 551system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram 552system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram 553system.l2bus.snoop_fanout::total 449 # Request fanout histogram 554system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) 555system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) 556system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) 557system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) 558system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) 559system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) 560system.l2cache.tags.replacements 0 # number of replacements 561system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use 562system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. 563system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. 564system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks. 565system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 566system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor 567system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor 568system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy 569system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy 570system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy 571system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id 572system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id 573system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id 574system.l2cache.tags.occ_task_id_percent::1024 0.091064 # Percentage of cache occupancy per task id 575system.l2cache.tags.tag_accesses 4534 # Number of tag accesses 576system.l2cache.tags.data_accesses 4534 # Number of data accesses 577system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits 578system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits 579system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 580system.l2cache.demand_hits::total 3 # number of demand (read+write) hits 581system.l2cache.overall_hits::cpu.inst 3 # number of overall hits 582system.l2cache.overall_hits::total 3 # number of overall hits 583system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 584system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 585system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses 586system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses 587system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses 588system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses 589system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses 590system.l2cache.demand_misses::total 446 # number of demand (read+write) misses 591system.l2cache.overall_misses::cpu.inst 278 # number of overall misses 592system.l2cache.overall_misses::cpu.data 168 # number of overall misses 593system.l2cache.overall_misses::total 446 # number of overall misses 594system.l2cache.ReadExReq_miss_latency::cpu.data 6913000 # number of ReadExReq miss cycles 595system.l2cache.ReadExReq_miss_latency::total 6913000 # number of ReadExReq miss cycles 596system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26482000 # number of ReadSharedReq miss cycles 597system.l2cache.ReadSharedReq_miss_latency::cpu.data 9627000 # number of ReadSharedReq miss cycles 598system.l2cache.ReadSharedReq_miss_latency::total 36109000 # number of ReadSharedReq miss cycles 599system.l2cache.demand_miss_latency::cpu.inst 26482000 # number of demand (read+write) miss cycles 600system.l2cache.demand_miss_latency::cpu.data 16540000 # number of demand (read+write) miss cycles 601system.l2cache.demand_miss_latency::total 43022000 # number of demand (read+write) miss cycles 602system.l2cache.overall_miss_latency::cpu.inst 26482000 # number of overall miss cycles 603system.l2cache.overall_miss_latency::cpu.data 16540000 # number of overall miss cycles 604system.l2cache.overall_miss_latency::total 43022000 # number of overall miss cycles 605system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 606system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 607system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) 608system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) 609system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses) 610system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses 611system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses 612system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses 613system.l2cache.overall_accesses::cpu.inst 281 # number of overall (read+write) accesses 614system.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses 615system.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses 616system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 617system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 618system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.989324 # miss rate for ReadSharedReq accesses 619system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 620system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses 621system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses 622system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 623system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses 624system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses 625system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 626system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses 627system.l2cache.ReadExReq_avg_miss_latency::cpu.data 94698.630137 # average ReadExReq miss latency 628system.l2cache.ReadExReq_avg_miss_latency::total 94698.630137 # average ReadExReq miss latency 629system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 95258.992806 # average ReadSharedReq miss latency 630system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101336.842105 # average ReadSharedReq miss latency 631system.l2cache.ReadSharedReq_avg_miss_latency::total 96806.970509 # average ReadSharedReq miss latency 632system.l2cache.demand_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency 633system.l2cache.demand_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency 634system.l2cache.demand_avg_miss_latency::total 96461.883408 # average overall miss latency 635system.l2cache.overall_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency 636system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency 637system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency 638system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 639system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 640system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 641system.l2cache.blocked::no_targets 0 # number of cycles access was blocked 642system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 643system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
650system.l2cache.fast_writes 0 # number of fast writes performed 651system.l2cache.cache_copies 0 # number of cache copies performed
652system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 653system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 654system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses 655system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 656system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses 657system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 658system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 659system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 660system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 661system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 662system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 663system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5453000 # number of ReadExReq MSHR miss cycles 664system.l2cache.ReadExReq_mshr_miss_latency::total 5453000 # number of ReadExReq MSHR miss cycles 665system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 20922000 # number of ReadSharedReq MSHR miss cycles 666system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7727000 # number of ReadSharedReq MSHR miss cycles 667system.l2cache.ReadSharedReq_mshr_miss_latency::total 28649000 # number of ReadSharedReq MSHR miss cycles 668system.l2cache.demand_mshr_miss_latency::cpu.inst 20922000 # number of demand (read+write) MSHR miss cycles 669system.l2cache.demand_mshr_miss_latency::cpu.data 13180000 # number of demand (read+write) MSHR miss cycles 670system.l2cache.demand_mshr_miss_latency::total 34102000 # number of demand (read+write) MSHR miss cycles 671system.l2cache.overall_mshr_miss_latency::cpu.inst 20922000 # number of overall MSHR miss cycles 672system.l2cache.overall_mshr_miss_latency::cpu.data 13180000 # number of overall MSHR miss cycles 673system.l2cache.overall_mshr_miss_latency::total 34102000 # number of overall MSHR miss cycles 674system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 675system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 676system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses 677system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 678system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses 679system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses 680system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 681system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses 682system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses 683system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 684system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses 685system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74698.630137 # average ReadExReq mshr miss latency 686system.l2cache.ReadExReq_avg_mshr_miss_latency::total 74698.630137 # average ReadExReq mshr miss latency 687system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 75258.992806 # average ReadSharedReq mshr miss latency 688system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency 689system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency 690system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 691system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 692system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency 693system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 694system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 695system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency	644system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 645system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 646system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses 647system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses 648system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses 649system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses 650system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses 651system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses 652system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses 653system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses 654system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses 655system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5453000 # number of ReadExReq MSHR miss cycles 656system.l2cache.ReadExReq_mshr_miss_latency::total 5453000 # number of ReadExReq MSHR miss cycles 657system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 20922000 # number of ReadSharedReq MSHR miss cycles 658system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7727000 # number of ReadSharedReq MSHR miss cycles 659system.l2cache.ReadSharedReq_mshr_miss_latency::total 28649000 # number of ReadSharedReq MSHR miss cycles 660system.l2cache.demand_mshr_miss_latency::cpu.inst 20922000 # number of demand (read+write) MSHR miss cycles 661system.l2cache.demand_mshr_miss_latency::cpu.data 13180000 # number of demand (read+write) MSHR miss cycles 662system.l2cache.demand_mshr_miss_latency::total 34102000 # number of demand (read+write) MSHR miss cycles 663system.l2cache.overall_mshr_miss_latency::cpu.inst 20922000 # number of overall MSHR miss cycles 664system.l2cache.overall_mshr_miss_latency::cpu.data 13180000 # number of overall MSHR miss cycles 665system.l2cache.overall_mshr_miss_latency::total 34102000 # number of overall MSHR miss cycles 666system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 667system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 668system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses 669system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 670system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses 671system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses 672system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 673system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses 674system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses 675system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 676system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses 677system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74698.630137 # average ReadExReq mshr miss latency 678system.l2cache.ReadExReq_avg_mshr_miss_latency::total 74698.630137 # average ReadExReq mshr miss latency 679system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 75258.992806 # average ReadSharedReq mshr miss latency 680system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency 681system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency 682system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 683system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 684system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency 685system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency 686system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency 687system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency
696system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
697system.membus.trans_dist::ReadResp 373 # Transaction distribution 698system.membus.trans_dist::ReadExReq 73 # Transaction distribution 699system.membus.trans_dist::ReadExResp 73 # Transaction distribution 700system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 701system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 702system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 703system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 704system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 705system.membus.snoops 0 # Total snoops (count) 706system.membus.snoop_fanout::samples 446 # Request fanout histogram 707system.membus.snoop_fanout::mean 0 # Request fanout histogram 708system.membus.snoop_fanout::stdev 0 # Request fanout histogram 709system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 710system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 711system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 712system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 713system.membus.snoop_fanout::min_value 0 # Request fanout histogram 714system.membus.snoop_fanout::max_value 0 # Request fanout histogram 715system.membus.snoop_fanout::total 446 # Request fanout histogram 716system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 717system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 718system.membus.respLayer0.occupancy 2375000 # Layer occupancy (ticks) 719system.membus.respLayer0.utilization 3.9 # Layer utilization (%) 720 721---------- End Simulation Statistics ----------	688system.membus.trans_dist::ReadResp 373 # Transaction distribution 689system.membus.trans_dist::ReadExReq 73 # Transaction distribution 690system.membus.trans_dist::ReadExResp 73 # Transaction distribution 691system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution 692system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) 693system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) 694system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) 695system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) 696system.membus.snoops 0 # Total snoops (count) 697system.membus.snoop_fanout::samples 446 # Request fanout histogram 698system.membus.snoop_fanout::mean 0 # Request fanout histogram 699system.membus.snoop_fanout::stdev 0 # Request fanout histogram 700system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 701system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram 702system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 703system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 704system.membus.snoop_fanout::min_value 0 # Request fanout histogram 705system.membus.snoop_fanout::max_value 0 # Request fanout histogram 706system.membus.snoop_fanout::total 446 # Request fanout histogram 707system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) 708system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) 709system.membus.respLayer0.occupancy 2375000 # Layer occupancy (ticks) 710system.membus.respLayer0.utilization 3.9 # Layer utilization (%) 711 712---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000061 # Number of seconds simulated
4sim_ticks 61470000 # Number of ticks simulated
5final_tick 61470000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 62593 # Simulator instruction rate (inst/s)
8host_op_rate 62569 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 595804848 # Simulator tick rate (ticks/s)
10host_mem_usage 614668 # Number of bytes of host memory used
11host_seconds 0.10 # Real time elapsed on the host

7host_inst_rate 583425 # Simulator instruction rate (inst/s)
8host_op_rate 580281 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 5518802940 # Simulator tick rate (ticks/s)
10host_mem_usage 637904 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host

12sim_insts 6453 # Number of instructions simulated
13sim_ops 6453 # Number of ops (including micro ops) simulated
14system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory
17system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory
18system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory
19system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory
20system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory
21system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory
22system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory
23system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory
24system.mem_ctrl.bw_read::cpu.inst 289442004 # Total read bandwidth from this memory (bytes/s)
25system.mem_ctrl.bw_read::cpu.data 174914592 # Total read bandwidth from this memory (bytes/s)
26system.mem_ctrl.bw_read::total 464356597 # Total read bandwidth from this memory (bytes/s)
27system.mem_ctrl.bw_inst_read::cpu.inst 289442004 # Instruction read bandwidth from this memory (bytes/s)
28system.mem_ctrl.bw_inst_read::total 289442004 # Instruction read bandwidth from this memory (bytes/s)
29system.mem_ctrl.bw_total::cpu.inst 289442004 # Total bandwidth to/from this memory (bytes/s)
30system.mem_ctrl.bw_total::cpu.data 174914592 # Total bandwidth to/from this memory (bytes/s)
31system.mem_ctrl.bw_total::total 464356597 # Total bandwidth to/from this memory (bytes/s)
32system.mem_ctrl.readReqs 446 # Number of read requests accepted
33system.mem_ctrl.writeReqs 0 # Number of write requests accepted
34system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue
35system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM
37system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM
39system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side
40system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44system.mem_ctrl.perBankRdBursts::0 62 # Per bank write bursts
45system.mem_ctrl.perBankRdBursts::1 26 # Per bank write bursts
46system.mem_ctrl.perBankRdBursts::2 24 # Per bank write bursts
47system.mem_ctrl.perBankRdBursts::3 43 # Per bank write bursts
48system.mem_ctrl.perBankRdBursts::4 40 # Per bank write bursts
49system.mem_ctrl.perBankRdBursts::5 17 # Per bank write bursts
50system.mem_ctrl.perBankRdBursts::6 1 # Per bank write bursts
51system.mem_ctrl.perBankRdBursts::7 3 # Per bank write bursts
52system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts
53system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts
54system.mem_ctrl.perBankRdBursts::10 19 # Per bank write bursts
55system.mem_ctrl.perBankRdBursts::11 23 # Per bank write bursts
56system.mem_ctrl.perBankRdBursts::12 14 # Per bank write bursts
57system.mem_ctrl.perBankRdBursts::13 116 # Per bank write bursts
58system.mem_ctrl.perBankRdBursts::14 45 # Per bank write bursts
59system.mem_ctrl.perBankRdBursts::15 12 # Per bank write bursts
60system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts
61system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts
62system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts
63system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts
64system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts
65system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts
66system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts
67system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts
68system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts
69system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts
70system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts
71system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts
72system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts
73system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts
74system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts
75system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts
76system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry
77system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry
78system.mem_ctrl.totGap 61220000 # Total gap between requests
79system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2)
80system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2)
81system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2)
82system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2)
83system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2)
84system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2)
85system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2)
86system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2)
87system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2)
88system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2)
89system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2)
90system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2)
91system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2)
92system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2)
93system.mem_ctrl.rdQLenPdf::0 446 # What read queue length does an incoming req see
94system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see
95system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see
96system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see
97system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see
98system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see
99system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see
105system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see
106system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see
107system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see
108system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see
109system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see
110system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see
111system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see
112system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see
113system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see
114system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see
115system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see
116system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see
117system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see
118system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see
119system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see
120system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see
121system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see
122system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see
123system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see
124system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see
125system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see
126system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see
127system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see
128system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see
129system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see
130system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see
131system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see
132system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see
133system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see
134system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see
135system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see
136system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see
137system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see
138system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see
139system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see
140system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see
141system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see
142system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see
143system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see
144system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see
145system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see
146system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see
147system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see
148system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see
149system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see
150system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see
151system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see
152system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see
153system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see
154system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see
155system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see
156system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see
157system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see
158system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see
159system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see
160system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see
161system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see
162system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see
163system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see
164system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see
165system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see
166system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see
167system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see
168system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see
169system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see
170system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see
171system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see
172system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see
173system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see
174system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see
175system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see
176system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see
177system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see
178system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see
179system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see
180system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see
181system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation
190system.mem_ctrl.bytesPerActivate::mean 270.821053 # Bytes accessed per row activation
191system.mem_ctrl.bytesPerActivate::gmean 180.792132 # Bytes accessed per row activation
192system.mem_ctrl.bytesPerActivate::stdev 259.793616 # Bytes accessed per row activation
193system.mem_ctrl.bytesPerActivate::0-127 28 29.47% 29.47% # Bytes accessed per row activation
194system.mem_ctrl.bytesPerActivate::128-255 29 30.53% 60.00% # Bytes accessed per row activation
195system.mem_ctrl.bytesPerActivate::256-383 12 12.63% 72.63% # Bytes accessed per row activation
196system.mem_ctrl.bytesPerActivate::384-511 9 9.47% 82.11% # Bytes accessed per row activation
197system.mem_ctrl.bytesPerActivate::512-639 5 5.26% 87.37% # Bytes accessed per row activation
198system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation
199system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation
200system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation
201system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation
202system.mem_ctrl.totQLat 3294500 # Total ticks spent queuing
203system.mem_ctrl.totMemAccLat 11657000 # Total ticks spent from burst creation until serviced by the DRAM
204system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers
205system.mem_ctrl.avgQLat 7386.77 # Average queueing delay per DRAM burst
206system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst
207system.mem_ctrl.avgMemAccLat 26136.77 # Average memory access latency per DRAM burst
208system.mem_ctrl.avgRdBW 464.36 # Average DRAM read bandwidth in MiByte/s
209system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
210system.mem_ctrl.avgRdBWSys 464.36 # Average system read bandwidth in MiByte/s
211system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
212system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
213system.mem_ctrl.busUtil 3.63 # Data bus utilization in percentage
214system.mem_ctrl.busUtilRead 3.63 # Data bus utilization in percentage for reads
215system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes
216system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing
217system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing
218system.mem_ctrl.readRowHits 341 # Number of row buffer hits during reads
219system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes
220system.mem_ctrl.readRowHitRate 76.46 # Row buffer hit rate for reads
221system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes
222system.mem_ctrl.avgGap 137264.57 # Average gap between requests
223system.mem_ctrl.pageHitRate 76.46 # Row buffer hit rate, read and write combined
224system.mem_ctrl_0.actEnergy 309960 # Energy for activate commands per rank (pJ)
225system.mem_ctrl_0.preEnergy 169125 # Energy for precharge commands per rank (pJ)
226system.mem_ctrl_0.readEnergy 1591200 # Energy for read commands per rank (pJ)
227system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ)
228system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
229system.mem_ctrl_0.actBackEnergy 37059120 # Energy for active background per rank (pJ)
230system.mem_ctrl_0.preBackEnergy 350250 # Energy for precharge background per rank (pJ)
231system.mem_ctrl_0.totalEnergy 43039575 # Total energy per rank (pJ)
232system.mem_ctrl_0.averagePower 785.913583 # Core power per rank (mW)
233system.mem_ctrl_0.memoryStateTime::IDLE 388750 # Time in different power states
234system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states
235system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states
236system.mem_ctrl_0.memoryStateTime::ACT 52568750 # Time in different power states
237system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states
238system.mem_ctrl_1.actEnergy 385560 # Energy for activate commands per rank (pJ)
239system.mem_ctrl_1.preEnergy 210375 # Energy for precharge commands per rank (pJ)
240system.mem_ctrl_1.readEnergy 1489800 # Energy for read commands per rank (pJ)
241system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ)
242system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ)
243system.mem_ctrl_1.actBackEnergy 35948475 # Energy for active background per rank (pJ)
244system.mem_ctrl_1.preBackEnergy 1324500 # Energy for precharge background per rank (pJ)
245system.mem_ctrl_1.totalEnergy 42918630 # Total energy per rank (pJ)
246system.mem_ctrl_1.averagePower 783.705097 # Core power per rank (mW)
247system.mem_ctrl_1.memoryStateTime::IDLE 2128500 # Time in different power states
248system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states
249system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states
250system.mem_ctrl_1.memoryStateTime::ACT 51068500 # Time in different power states
251system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states
252system.cpu.dtb.fetch_hits 0 # ITB hits
253system.cpu.dtb.fetch_misses 0 # ITB misses
254system.cpu.dtb.fetch_acv 0 # ITB acv
255system.cpu.dtb.fetch_accesses 0 # ITB accesses
256system.cpu.dtb.read_hits 1190 # DTB read hits
257system.cpu.dtb.read_misses 7 # DTB read misses
258system.cpu.dtb.read_acv 0 # DTB read access violations
259system.cpu.dtb.read_accesses 1197 # DTB read accesses
260system.cpu.dtb.write_hits 865 # DTB write hits
261system.cpu.dtb.write_misses 3 # DTB write misses
262system.cpu.dtb.write_acv 0 # DTB write access violations
263system.cpu.dtb.write_accesses 868 # DTB write accesses
264system.cpu.dtb.data_hits 2055 # DTB hits
265system.cpu.dtb.data_misses 10 # DTB misses
266system.cpu.dtb.data_acv 0 # DTB access violations
267system.cpu.dtb.data_accesses 2065 # DTB accesses
268system.cpu.itb.fetch_hits 6464 # ITB hits
269system.cpu.itb.fetch_misses 17 # ITB misses
270system.cpu.itb.fetch_acv 0 # ITB acv
271system.cpu.itb.fetch_accesses 6481 # ITB accesses
272system.cpu.itb.read_hits 0 # DTB read hits
273system.cpu.itb.read_misses 0 # DTB read misses
274system.cpu.itb.read_acv 0 # DTB read access violations
275system.cpu.itb.read_accesses 0 # DTB read accesses
276system.cpu.itb.write_hits 0 # DTB write hits
277system.cpu.itb.write_misses 0 # DTB write misses
278system.cpu.itb.write_acv 0 # DTB write access violations
279system.cpu.itb.write_accesses 0 # DTB write accesses
280system.cpu.itb.data_hits 0 # DTB hits
281system.cpu.itb.data_misses 0 # DTB misses
282system.cpu.itb.data_acv 0 # DTB access violations
283system.cpu.itb.data_accesses 0 # DTB accesses
284system.cpu.workload.num_syscalls 17 # Number of system calls
285system.cpu.numCycles 61470 # number of cpu cycles simulated
286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
288system.cpu.committedInsts 6453 # Number of instructions committed
289system.cpu.committedOps 6453 # Number of ops (including micro ops) committed
290system.cpu.num_int_alu_accesses 6380 # Number of integer alu accesses
291system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
292system.cpu.num_func_calls 251 # number of times a function call or return occured
293system.cpu.num_conditional_control_insts 759 # number of instructions that are conditional controls
294system.cpu.num_int_insts 6380 # number of integer instructions
295system.cpu.num_fp_insts 10 # number of float instructions
296system.cpu.num_int_register_reads 8392 # number of times the integer registers were read
297system.cpu.num_int_register_writes 4621 # number of times the integer registers were written
298system.cpu.num_fp_register_reads 8 # number of times the floating registers were read
299system.cpu.num_fp_register_writes 2 # number of times the floating registers were written
300system.cpu.num_mem_refs 2065 # number of memory refs
301system.cpu.num_load_insts 1197 # Number of load instructions
302system.cpu.num_store_insts 868 # Number of store instructions
303system.cpu.num_idle_cycles 0 # Number of idle cycles
304system.cpu.num_busy_cycles 61470 # Number of busy cycles
305system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
306system.cpu.idle_fraction 0 # Percentage of idle cycles
307system.cpu.Branches 1060 # Number of branches fetched
308system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction
309system.cpu.op_class::IntAlu 4376 67.71% 68.00% # Class of executed instruction
310system.cpu.op_class::IntMult 1 0.02% 68.02% # Class of executed instruction
311system.cpu.op_class::IntDiv 0 0.00% 68.02% # Class of executed instruction
312system.cpu.op_class::FloatAdd 2 0.03% 68.05% # Class of executed instruction
313system.cpu.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction
314system.cpu.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction
315system.cpu.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction
316system.cpu.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction
317system.cpu.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction
318system.cpu.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction
319system.cpu.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction
320system.cpu.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction
321system.cpu.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction
322system.cpu.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction
323system.cpu.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction
324system.cpu.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction
325system.cpu.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction
326system.cpu.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction
327system.cpu.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction
328system.cpu.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction
329system.cpu.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction
330system.cpu.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction
331system.cpu.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction
332system.cpu.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction
333system.cpu.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction
334system.cpu.op_class::SimdFloatMisc 0 0.00% 68.05% # Class of executed instruction
335system.cpu.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction
336system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction
337system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction
338system.cpu.op_class::MemRead 1197 18.52% 86.57% # Class of executed instruction
339system.cpu.op_class::MemWrite 868 13.43% 100.00% # Class of executed instruction
340system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
341system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
342system.cpu.op_class::total 6463 # Class of executed instruction
343system.cpu.dcache.tags.replacements 0 # number of replacements
344system.cpu.dcache.tags.tagsinuse 104.645861 # Cycle average of tags in use
345system.cpu.dcache.tags.total_refs 1887 # Total number of references to valid blocks.
346system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
347system.cpu.dcache.tags.avg_refs 11.232143 # Average number of references to valid blocks.
348system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
349system.cpu.dcache.tags.occ_blocks::cpu.data 104.645861 # Average occupied blocks per requestor
350system.cpu.dcache.tags.occ_percent::cpu.data 0.102193 # Average percentage of cache occupancy
351system.cpu.dcache.tags.occ_percent::total 0.102193 # Average percentage of cache occupancy
352system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
353system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id
354system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id
355system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id
356system.cpu.dcache.tags.tag_accesses 4278 # Number of tag accesses
357system.cpu.dcache.tags.data_accesses 4278 # Number of data accesses
358system.cpu.dcache.ReadReq_hits::cpu.data 1095 # number of ReadReq hits
359system.cpu.dcache.ReadReq_hits::total 1095 # number of ReadReq hits
360system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits
361system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits
362system.cpu.dcache.demand_hits::cpu.data 1887 # number of demand (read+write) hits
363system.cpu.dcache.demand_hits::total 1887 # number of demand (read+write) hits
364system.cpu.dcache.overall_hits::cpu.data 1887 # number of overall hits
365system.cpu.dcache.overall_hits::total 1887 # number of overall hits
366system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
367system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses
368system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses
369system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses
370system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses
371system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses
372system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses
373system.cpu.dcache.overall_misses::total 168 # number of overall misses
374system.cpu.dcache.ReadReq_miss_latency::cpu.data 10102000 # number of ReadReq miss cycles
375system.cpu.dcache.ReadReq_miss_latency::total 10102000 # number of ReadReq miss cycles
376system.cpu.dcache.WriteReq_miss_latency::cpu.data 7278000 # number of WriteReq miss cycles
377system.cpu.dcache.WriteReq_miss_latency::total 7278000 # number of WriteReq miss cycles
378system.cpu.dcache.demand_miss_latency::cpu.data 17380000 # number of demand (read+write) miss cycles
379system.cpu.dcache.demand_miss_latency::total 17380000 # number of demand (read+write) miss cycles
380system.cpu.dcache.overall_miss_latency::cpu.data 17380000 # number of overall miss cycles
381system.cpu.dcache.overall_miss_latency::total 17380000 # number of overall miss cycles
382system.cpu.dcache.ReadReq_accesses::cpu.data 1190 # number of ReadReq accesses(hits+misses)
383system.cpu.dcache.ReadReq_accesses::total 1190 # number of ReadReq accesses(hits+misses)
384system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
385system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
386system.cpu.dcache.demand_accesses::cpu.data 2055 # number of demand (read+write) accesses
387system.cpu.dcache.demand_accesses::total 2055 # number of demand (read+write) accesses
388system.cpu.dcache.overall_accesses::cpu.data 2055 # number of overall (read+write) accesses
389system.cpu.dcache.overall_accesses::total 2055 # number of overall (read+write) accesses
390system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079832 # miss rate for ReadReq accesses
391system.cpu.dcache.ReadReq_miss_rate::total 0.079832 # miss rate for ReadReq accesses
392system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses
393system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses
394system.cpu.dcache.demand_miss_rate::cpu.data 0.081752 # miss rate for demand accesses
395system.cpu.dcache.demand_miss_rate::total 0.081752 # miss rate for demand accesses
396system.cpu.dcache.overall_miss_rate::cpu.data 0.081752 # miss rate for overall accesses
397system.cpu.dcache.overall_miss_rate::total 0.081752 # miss rate for overall accesses
398system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 106336.842105 # average ReadReq miss latency
399system.cpu.dcache.ReadReq_avg_miss_latency::total 106336.842105 # average ReadReq miss latency
400system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99698.630137 # average WriteReq miss latency
401system.cpu.dcache.WriteReq_avg_miss_latency::total 99698.630137 # average WriteReq miss latency
402system.cpu.dcache.demand_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency
403system.cpu.dcache.demand_avg_miss_latency::total 103452.380952 # average overall miss latency
404system.cpu.dcache.overall_avg_miss_latency::cpu.data 103452.380952 # average overall miss latency
405system.cpu.dcache.overall_avg_miss_latency::total 103452.380952 # average overall miss latency
406system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
407system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
408system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
409system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
410system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
411system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

412system.cpu.dcache.fast_writes 0 # number of fast writes performed
413system.cpu.dcache.cache_copies 0 # number of cache copies performed

414system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
415system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
416system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
417system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
418system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
419system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
420system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
421system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
422system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9912000 # number of ReadReq MSHR miss cycles
423system.cpu.dcache.ReadReq_mshr_miss_latency::total 9912000 # number of ReadReq MSHR miss cycles
424system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7132000 # number of WriteReq MSHR miss cycles
425system.cpu.dcache.WriteReq_mshr_miss_latency::total 7132000 # number of WriteReq MSHR miss cycles
426system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17044000 # number of demand (read+write) MSHR miss cycles
427system.cpu.dcache.demand_mshr_miss_latency::total 17044000 # number of demand (read+write) MSHR miss cycles
428system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17044000 # number of overall MSHR miss cycles
429system.cpu.dcache.overall_mshr_miss_latency::total 17044000 # number of overall MSHR miss cycles
430system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses
431system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses
432system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
433system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
434system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses
435system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses
436system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses
437system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses
438system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency
439system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency
440system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency
441system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency
442system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
443system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
444system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
445system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency

412system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
413system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
414system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
415system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
416system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
417system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
418system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
419system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
420system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9912000 # number of ReadReq MSHR miss cycles
421system.cpu.dcache.ReadReq_mshr_miss_latency::total 9912000 # number of ReadReq MSHR miss cycles
422system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7132000 # number of WriteReq MSHR miss cycles
423system.cpu.dcache.WriteReq_mshr_miss_latency::total 7132000 # number of WriteReq MSHR miss cycles
424system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17044000 # number of demand (read+write) MSHR miss cycles
425system.cpu.dcache.demand_mshr_miss_latency::total 17044000 # number of demand (read+write) MSHR miss cycles
426system.cpu.dcache.overall_mshr_miss_latency::cpu.data 17044000 # number of overall MSHR miss cycles
427system.cpu.dcache.overall_mshr_miss_latency::total 17044000 # number of overall MSHR miss cycles
428system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079832 # mshr miss rate for ReadReq accesses
429system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079832 # mshr miss rate for ReadReq accesses
430system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
431system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
432system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for demand accesses
433system.cpu.dcache.demand_mshr_miss_rate::total 0.081752 # mshr miss rate for demand accesses
434system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081752 # mshr miss rate for overall accesses
435system.cpu.dcache.overall_mshr_miss_rate::total 0.081752 # mshr miss rate for overall accesses
436system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 104336.842105 # average ReadReq mshr miss latency
437system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 104336.842105 # average ReadReq mshr miss latency
438system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97698.630137 # average WriteReq mshr miss latency
439system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97698.630137 # average WriteReq mshr miss latency
440system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
441system.cpu.dcache.demand_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency
442system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101452.380952 # average overall mshr miss latency
443system.cpu.dcache.overall_avg_mshr_miss_latency::total 101452.380952 # average overall mshr miss latency

446system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

447system.cpu.icache.tags.replacements 62 # number of replacements
448system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use
449system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks.
450system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks.
451system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks.
452system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
453system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor
454system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy
455system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy
456system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id
457system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
458system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
459system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id
460system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses
461system.cpu.icache.tags.data_accesses 13209 # Number of data accesses
462system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits
463system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits
464system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits
465system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits
466system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits
467system.cpu.icache.overall_hits::total 6183 # number of overall hits
468system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses
469system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses
470system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses
471system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses
472system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses
473system.cpu.icache.overall_misses::total 281 # number of overall misses
474system.cpu.icache.ReadReq_miss_latency::cpu.inst 27952000 # number of ReadReq miss cycles
475system.cpu.icache.ReadReq_miss_latency::total 27952000 # number of ReadReq miss cycles
476system.cpu.icache.demand_miss_latency::cpu.inst 27952000 # number of demand (read+write) miss cycles
477system.cpu.icache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles
478system.cpu.icache.overall_miss_latency::cpu.inst 27952000 # number of overall miss cycles
479system.cpu.icache.overall_miss_latency::total 27952000 # number of overall miss cycles
480system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses)
481system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses)
482system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses
483system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses
484system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses
485system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses
486system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses
487system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses
488system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses
489system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses
490system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses
491system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses
492system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 99473.309609 # average ReadReq miss latency
493system.cpu.icache.ReadReq_avg_miss_latency::total 99473.309609 # average ReadReq miss latency
494system.cpu.icache.demand_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency
495system.cpu.icache.demand_avg_miss_latency::total 99473.309609 # average overall miss latency
496system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency
497system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency
498system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
499system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
500system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
501system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
502system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
503system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

444system.cpu.icache.tags.replacements 62 # number of replacements
445system.cpu.icache.tags.tagsinuse 113.715440 # Cycle average of tags in use
446system.cpu.icache.tags.total_refs 6183 # Total number of references to valid blocks.
447system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks.
448system.cpu.icache.tags.avg_refs 22.003559 # Average number of references to valid blocks.
449system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
450system.cpu.icache.tags.occ_blocks::cpu.inst 113.715440 # Average occupied blocks per requestor
451system.cpu.icache.tags.occ_percent::cpu.inst 0.444201 # Average percentage of cache occupancy
452system.cpu.icache.tags.occ_percent::total 0.444201 # Average percentage of cache occupancy
453system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id
454system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id
455system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id
456system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id
457system.cpu.icache.tags.tag_accesses 13209 # Number of tag accesses
458system.cpu.icache.tags.data_accesses 13209 # Number of data accesses
459system.cpu.icache.ReadReq_hits::cpu.inst 6183 # number of ReadReq hits
460system.cpu.icache.ReadReq_hits::total 6183 # number of ReadReq hits
461system.cpu.icache.demand_hits::cpu.inst 6183 # number of demand (read+write) hits
462system.cpu.icache.demand_hits::total 6183 # number of demand (read+write) hits
463system.cpu.icache.overall_hits::cpu.inst 6183 # number of overall hits
464system.cpu.icache.overall_hits::total 6183 # number of overall hits
465system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses
466system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses
467system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses
468system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses
469system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses
470system.cpu.icache.overall_misses::total 281 # number of overall misses
471system.cpu.icache.ReadReq_miss_latency::cpu.inst 27952000 # number of ReadReq miss cycles
472system.cpu.icache.ReadReq_miss_latency::total 27952000 # number of ReadReq miss cycles
473system.cpu.icache.demand_miss_latency::cpu.inst 27952000 # number of demand (read+write) miss cycles
474system.cpu.icache.demand_miss_latency::total 27952000 # number of demand (read+write) miss cycles
475system.cpu.icache.overall_miss_latency::cpu.inst 27952000 # number of overall miss cycles
476system.cpu.icache.overall_miss_latency::total 27952000 # number of overall miss cycles
477system.cpu.icache.ReadReq_accesses::cpu.inst 6464 # number of ReadReq accesses(hits+misses)
478system.cpu.icache.ReadReq_accesses::total 6464 # number of ReadReq accesses(hits+misses)
479system.cpu.icache.demand_accesses::cpu.inst 6464 # number of demand (read+write) accesses
480system.cpu.icache.demand_accesses::total 6464 # number of demand (read+write) accesses
481system.cpu.icache.overall_accesses::cpu.inst 6464 # number of overall (read+write) accesses
482system.cpu.icache.overall_accesses::total 6464 # number of overall (read+write) accesses
483system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043472 # miss rate for ReadReq accesses
484system.cpu.icache.ReadReq_miss_rate::total 0.043472 # miss rate for ReadReq accesses
485system.cpu.icache.demand_miss_rate::cpu.inst 0.043472 # miss rate for demand accesses
486system.cpu.icache.demand_miss_rate::total 0.043472 # miss rate for demand accesses
487system.cpu.icache.overall_miss_rate::cpu.inst 0.043472 # miss rate for overall accesses
488system.cpu.icache.overall_miss_rate::total 0.043472 # miss rate for overall accesses
489system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 99473.309609 # average ReadReq miss latency
490system.cpu.icache.ReadReq_avg_miss_latency::total 99473.309609 # average ReadReq miss latency
491system.cpu.icache.demand_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency
492system.cpu.icache.demand_avg_miss_latency::total 99473.309609 # average overall miss latency
493system.cpu.icache.overall_avg_miss_latency::cpu.inst 99473.309609 # average overall miss latency
494system.cpu.icache.overall_avg_miss_latency::total 99473.309609 # average overall miss latency
495system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
496system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
497system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
498system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
499system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
500system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

504system.cpu.icache.fast_writes 0 # number of fast writes performed
505system.cpu.icache.cache_copies 0 # number of cache copies performed

506system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses
507system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses
508system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses
509system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses
510system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses
511system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses
512system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles
513system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles
514system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27390000 # number of demand (read+write) MSHR miss cycles
515system.cpu.icache.demand_mshr_miss_latency::total 27390000 # number of demand (read+write) MSHR miss cycles
516system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27390000 # number of overall MSHR miss cycles
517system.cpu.icache.overall_mshr_miss_latency::total 27390000 # number of overall MSHR miss cycles
518system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses
519system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses
520system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses
521system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses
522system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses
523system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses
524system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency
525system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency
526system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency
527system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency
528system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency
529system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency

501system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses
502system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses
503system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses
504system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses
505system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses
506system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses
507system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27390000 # number of ReadReq MSHR miss cycles
508system.cpu.icache.ReadReq_mshr_miss_latency::total 27390000 # number of ReadReq MSHR miss cycles
509system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27390000 # number of demand (read+write) MSHR miss cycles
510system.cpu.icache.demand_mshr_miss_latency::total 27390000 # number of demand (read+write) MSHR miss cycles
511system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27390000 # number of overall MSHR miss cycles
512system.cpu.icache.overall_mshr_miss_latency::total 27390000 # number of overall MSHR miss cycles
513system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for ReadReq accesses
514system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043472 # mshr miss rate for ReadReq accesses
515system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for demand accesses
516system.cpu.icache.demand_mshr_miss_rate::total 0.043472 # mshr miss rate for demand accesses
517system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043472 # mshr miss rate for overall accesses
518system.cpu.icache.overall_mshr_miss_rate::total 0.043472 # mshr miss rate for overall accesses
519system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 97473.309609 # average ReadReq mshr miss latency
520system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97473.309609 # average ReadReq mshr miss latency
521system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency
522system.cpu.icache.demand_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency
523system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 97473.309609 # average overall mshr miss latency
524system.cpu.icache.overall_avg_mshr_miss_latency::total 97473.309609 # average overall mshr miss latency

530system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

531system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
532system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data.
533system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
534system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
535system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
536system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
537system.l2bus.trans_dist::ReadResp 376 # Transaction distribution
538system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution
539system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution
540system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution
541system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution
542system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes)
543system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
544system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes)
545system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes)
546system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
547system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes)
548system.l2bus.snoops 0 # Total snoops (count)
549system.l2bus.snoop_fanout::samples 449 # Request fanout histogram
550system.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram
551system.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram
552system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
553system.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram
554system.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram
555system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
556system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
557system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
558system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
559system.l2bus.snoop_fanout::total 449 # Request fanout histogram
560system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks)
561system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
562system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks)
563system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
564system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks)
565system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
566system.l2cache.tags.replacements 0 # number of replacements
567system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use
568system.l2cache.tags.total_refs 65 # Total number of references to valid blocks.
569system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
570system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks.
571system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
572system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor
573system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor
574system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy
575system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy
576system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy
577system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
578system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
579system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
580system.l2cache.tags.occ_task_id_percent::1024 0.091064 # Percentage of cache occupancy per task id
581system.l2cache.tags.tag_accesses 4534 # Number of tag accesses
582system.l2cache.tags.data_accesses 4534 # Number of data accesses
583system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits
584system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits
585system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
586system.l2cache.demand_hits::total 3 # number of demand (read+write) hits
587system.l2cache.overall_hits::cpu.inst 3 # number of overall hits
588system.l2cache.overall_hits::total 3 # number of overall hits
589system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
590system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
591system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses
592system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses
593system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses
594system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
595system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
596system.l2cache.demand_misses::total 446 # number of demand (read+write) misses
597system.l2cache.overall_misses::cpu.inst 278 # number of overall misses
598system.l2cache.overall_misses::cpu.data 168 # number of overall misses
599system.l2cache.overall_misses::total 446 # number of overall misses
600system.l2cache.ReadExReq_miss_latency::cpu.data 6913000 # number of ReadExReq miss cycles
601system.l2cache.ReadExReq_miss_latency::total 6913000 # number of ReadExReq miss cycles
602system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26482000 # number of ReadSharedReq miss cycles
603system.l2cache.ReadSharedReq_miss_latency::cpu.data 9627000 # number of ReadSharedReq miss cycles
604system.l2cache.ReadSharedReq_miss_latency::total 36109000 # number of ReadSharedReq miss cycles
605system.l2cache.demand_miss_latency::cpu.inst 26482000 # number of demand (read+write) miss cycles
606system.l2cache.demand_miss_latency::cpu.data 16540000 # number of demand (read+write) miss cycles
607system.l2cache.demand_miss_latency::total 43022000 # number of demand (read+write) miss cycles
608system.l2cache.overall_miss_latency::cpu.inst 26482000 # number of overall miss cycles
609system.l2cache.overall_miss_latency::cpu.data 16540000 # number of overall miss cycles
610system.l2cache.overall_miss_latency::total 43022000 # number of overall miss cycles
611system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
612system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
613system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses)
614system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses)
615system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses)
616system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses
617system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
618system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses
619system.l2cache.overall_accesses::cpu.inst 281 # number of overall (read+write) accesses
620system.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
621system.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses
622system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
623system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
624system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.989324 # miss rate for ReadSharedReq accesses
625system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
626system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses
627system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses
628system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
629system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses
630system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses
631system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
632system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses
633system.l2cache.ReadExReq_avg_miss_latency::cpu.data 94698.630137 # average ReadExReq miss latency
634system.l2cache.ReadExReq_avg_miss_latency::total 94698.630137 # average ReadExReq miss latency
635system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 95258.992806 # average ReadSharedReq miss latency
636system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101336.842105 # average ReadSharedReq miss latency
637system.l2cache.ReadSharedReq_avg_miss_latency::total 96806.970509 # average ReadSharedReq miss latency
638system.l2cache.demand_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency
639system.l2cache.demand_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency
640system.l2cache.demand_avg_miss_latency::total 96461.883408 # average overall miss latency
641system.l2cache.overall_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency
642system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency
643system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency
644system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
645system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
646system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
647system.l2cache.blocked::no_targets 0 # number of cycles access was blocked
648system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
649system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

525system.l2bus.snoop_filter.tot_requests 511 # Total number of requests made to the snoop filter.
526system.l2bus.snoop_filter.hit_single_requests 63 # Number of requests hitting in the snoop filter with a single holder of the requested data.
527system.l2bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
528system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
529system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
530system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
531system.l2bus.trans_dist::ReadResp 376 # Transaction distribution
532system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution
533system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution
534system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution
535system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution
536system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes)
537system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
538system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes)
539system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes)
540system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
541system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes)
542system.l2bus.snoops 0 # Total snoops (count)
543system.l2bus.snoop_fanout::samples 449 # Request fanout histogram
544system.l2bus.snoop_fanout::mean 0.002227 # Request fanout histogram
545system.l2bus.snoop_fanout::stdev 0.047193 # Request fanout histogram
546system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
547system.l2bus.snoop_fanout::0 448 99.78% 99.78% # Request fanout histogram
548system.l2bus.snoop_fanout::1 1 0.22% 100.00% # Request fanout histogram
549system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
550system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
551system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram
552system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram
553system.l2bus.snoop_fanout::total 449 # Request fanout histogram
554system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks)
555system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%)
556system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks)
557system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%)
558system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks)
559system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%)
560system.l2cache.tags.replacements 0 # number of replacements
561system.l2cache.tags.tagsinuse 185.619069 # Cycle average of tags in use
562system.l2cache.tags.total_refs 65 # Total number of references to valid blocks.
563system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks.
564system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks.
565system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
566system.l2cache.tags.occ_blocks::cpu.inst 128.455542 # Average occupied blocks per requestor
567system.l2cache.tags.occ_blocks::cpu.data 57.163528 # Average occupied blocks per requestor
568system.l2cache.tags.occ_percent::cpu.inst 0.031361 # Average percentage of cache occupancy
569system.l2cache.tags.occ_percent::cpu.data 0.013956 # Average percentage of cache occupancy
570system.l2cache.tags.occ_percent::total 0.045317 # Average percentage of cache occupancy
571system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id
572system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
573system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id
574system.l2cache.tags.occ_task_id_percent::1024 0.091064 # Percentage of cache occupancy per task id
575system.l2cache.tags.tag_accesses 4534 # Number of tag accesses
576system.l2cache.tags.data_accesses 4534 # Number of data accesses
577system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits
578system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits
579system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
580system.l2cache.demand_hits::total 3 # number of demand (read+write) hits
581system.l2cache.overall_hits::cpu.inst 3 # number of overall hits
582system.l2cache.overall_hits::total 3 # number of overall hits
583system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
584system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
585system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses
586system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses
587system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses
588system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
589system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
590system.l2cache.demand_misses::total 446 # number of demand (read+write) misses
591system.l2cache.overall_misses::cpu.inst 278 # number of overall misses
592system.l2cache.overall_misses::cpu.data 168 # number of overall misses
593system.l2cache.overall_misses::total 446 # number of overall misses
594system.l2cache.ReadExReq_miss_latency::cpu.data 6913000 # number of ReadExReq miss cycles
595system.l2cache.ReadExReq_miss_latency::total 6913000 # number of ReadExReq miss cycles
596system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26482000 # number of ReadSharedReq miss cycles
597system.l2cache.ReadSharedReq_miss_latency::cpu.data 9627000 # number of ReadSharedReq miss cycles
598system.l2cache.ReadSharedReq_miss_latency::total 36109000 # number of ReadSharedReq miss cycles
599system.l2cache.demand_miss_latency::cpu.inst 26482000 # number of demand (read+write) miss cycles
600system.l2cache.demand_miss_latency::cpu.data 16540000 # number of demand (read+write) miss cycles
601system.l2cache.demand_miss_latency::total 43022000 # number of demand (read+write) miss cycles
602system.l2cache.overall_miss_latency::cpu.inst 26482000 # number of overall miss cycles
603system.l2cache.overall_miss_latency::cpu.data 16540000 # number of overall miss cycles
604system.l2cache.overall_miss_latency::total 43022000 # number of overall miss cycles
605system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
606system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
607system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses)
608system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses)
609system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses)
610system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses
611system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
612system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses
613system.l2cache.overall_accesses::cpu.inst 281 # number of overall (read+write) accesses
614system.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
615system.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses
616system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
617system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
618system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.989324 # miss rate for ReadSharedReq accesses
619system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
620system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses
621system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses
622system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
623system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses
624system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses
625system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
626system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses
627system.l2cache.ReadExReq_avg_miss_latency::cpu.data 94698.630137 # average ReadExReq miss latency
628system.l2cache.ReadExReq_avg_miss_latency::total 94698.630137 # average ReadExReq miss latency
629system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 95258.992806 # average ReadSharedReq miss latency
630system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 101336.842105 # average ReadSharedReq miss latency
631system.l2cache.ReadSharedReq_avg_miss_latency::total 96806.970509 # average ReadSharedReq miss latency
632system.l2cache.demand_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency
633system.l2cache.demand_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency
634system.l2cache.demand_avg_miss_latency::total 96461.883408 # average overall miss latency
635system.l2cache.overall_avg_miss_latency::cpu.inst 95258.992806 # average overall miss latency
636system.l2cache.overall_avg_miss_latency::cpu.data 98452.380952 # average overall miss latency
637system.l2cache.overall_avg_miss_latency::total 96461.883408 # average overall miss latency
638system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
639system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
640system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
641system.l2cache.blocked::no_targets 0 # number of cycles access was blocked
642system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
643system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked

650system.l2cache.fast_writes 0 # number of fast writes performed
651system.l2cache.cache_copies 0 # number of cache copies performed

652system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
653system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
654system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses
655system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses
656system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses
657system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
658system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
659system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
660system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
661system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
662system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
663system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5453000 # number of ReadExReq MSHR miss cycles
664system.l2cache.ReadExReq_mshr_miss_latency::total 5453000 # number of ReadExReq MSHR miss cycles
665system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 20922000 # number of ReadSharedReq MSHR miss cycles
666system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7727000 # number of ReadSharedReq MSHR miss cycles
667system.l2cache.ReadSharedReq_mshr_miss_latency::total 28649000 # number of ReadSharedReq MSHR miss cycles
668system.l2cache.demand_mshr_miss_latency::cpu.inst 20922000 # number of demand (read+write) MSHR miss cycles
669system.l2cache.demand_mshr_miss_latency::cpu.data 13180000 # number of demand (read+write) MSHR miss cycles
670system.l2cache.demand_mshr_miss_latency::total 34102000 # number of demand (read+write) MSHR miss cycles
671system.l2cache.overall_mshr_miss_latency::cpu.inst 20922000 # number of overall MSHR miss cycles
672system.l2cache.overall_mshr_miss_latency::cpu.data 13180000 # number of overall MSHR miss cycles
673system.l2cache.overall_mshr_miss_latency::total 34102000 # number of overall MSHR miss cycles
674system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
675system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
676system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses
677system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
678system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses
679system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses
680system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
681system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses
682system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses
683system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
684system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses
685system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74698.630137 # average ReadExReq mshr miss latency
686system.l2cache.ReadExReq_avg_mshr_miss_latency::total 74698.630137 # average ReadExReq mshr miss latency
687system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 75258.992806 # average ReadSharedReq mshr miss latency
688system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency
689system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency
690system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
691system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
692system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency
693system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
694system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
695system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency

644system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
645system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
646system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses
647system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses
648system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses
649system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
650system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
651system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
652system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
653system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
654system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
655system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5453000 # number of ReadExReq MSHR miss cycles
656system.l2cache.ReadExReq_mshr_miss_latency::total 5453000 # number of ReadExReq MSHR miss cycles
657system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 20922000 # number of ReadSharedReq MSHR miss cycles
658system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7727000 # number of ReadSharedReq MSHR miss cycles
659system.l2cache.ReadSharedReq_mshr_miss_latency::total 28649000 # number of ReadSharedReq MSHR miss cycles
660system.l2cache.demand_mshr_miss_latency::cpu.inst 20922000 # number of demand (read+write) MSHR miss cycles
661system.l2cache.demand_mshr_miss_latency::cpu.data 13180000 # number of demand (read+write) MSHR miss cycles
662system.l2cache.demand_mshr_miss_latency::total 34102000 # number of demand (read+write) MSHR miss cycles
663system.l2cache.overall_mshr_miss_latency::cpu.inst 20922000 # number of overall MSHR miss cycles
664system.l2cache.overall_mshr_miss_latency::cpu.data 13180000 # number of overall MSHR miss cycles
665system.l2cache.overall_mshr_miss_latency::total 34102000 # number of overall MSHR miss cycles
666system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
667system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
668system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses
669system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
670system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses
671system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses
672system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
673system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses
674system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses
675system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
676system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses
677system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74698.630137 # average ReadExReq mshr miss latency
678system.l2cache.ReadExReq_avg_mshr_miss_latency::total 74698.630137 # average ReadExReq mshr miss latency
679system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 75258.992806 # average ReadSharedReq mshr miss latency
680system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81336.842105 # average ReadSharedReq mshr miss latency
681system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76806.970509 # average ReadSharedReq mshr miss latency
682system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
683system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
684system.l2cache.demand_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency
685system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75258.992806 # average overall mshr miss latency
686system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78452.380952 # average overall mshr miss latency
687system.l2cache.overall_avg_mshr_miss_latency::total 76461.883408 # average overall mshr miss latency

696system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate