| stats.txt (11731:c473ca7cc650) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000027 # Number of seconds simulated 4sim_ticks 26661500 # Number of ticks simulated 5final_tick 26661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25563000 # Number of ticks simulated 5final_tick 25563000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 29979 # Simulator instruction rate (inst/s) 8host_op_rate 29977 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 62584510 # Simulator tick rate (ticks/s) 10host_mem_usage 237004 # Number of bytes of host memory used 11host_seconds 0.43 # Real time elapsed on the host 12sim_insts 12770 # Number of instructions simulated 13sim_ops 12770 # Number of ops (including micro ops) simulated | 7host_inst_rate 149418 # Simulator instruction rate (inst/s) 8host_op_rate 149401 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 290951659 # Simulator tick rate (ticks/s) 10host_mem_usage 254508 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 13125 # Number of instructions simulated 13sim_ops 13125 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 21888 # Number of bytes read from this memory 19system.physmem.bytes_read::total 61888 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 342 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 967 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 1500290681 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 820959061 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 2321249742 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 1500290681 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 1500290681 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 1500290681 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 820959061 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 2321249742 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 968 # Number of read requests accepted | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 11200 # Number of bytes read from this memory 19system.physmem.bytes_read::total 31488 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 20288 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 20288 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 175 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 492 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 793647068 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 438133239 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1231780307 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 793647068 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 793647068 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 793647068 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 438133239 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1231780307 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 492 # Number of read requests accepted |
| 34system.physmem.writeReqs 0 # Number of write requests accepted | 34system.physmem.writeReqs 0 # Number of write requests accepted |
| 35system.physmem.readBursts 968 # Number of DRAM read bursts, including those serviced by the write queue | 35system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue |
| 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 37system.physmem.bytesReadDRAM 61952 # Total number of bytes read from DRAM | 37system.physmem.bytesReadDRAM 31488 # Total number of bytes read from DRAM |
| 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 40system.physmem.bytesReadSys 61952 # Total read bytes from the system interface side | 40system.physmem.bytesReadSys 31488 # Total read bytes from the system interface side |
| 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 45system.physmem.perBankRdBursts::0 84 # Per bank write bursts 46system.physmem.perBankRdBursts::1 150 # Per bank write bursts 47system.physmem.perBankRdBursts::2 77 # Per bank write bursts 48system.physmem.perBankRdBursts::3 58 # Per bank write bursts 49system.physmem.perBankRdBursts::4 90 # Per bank write bursts 50system.physmem.perBankRdBursts::5 45 # Per bank write bursts 51system.physmem.perBankRdBursts::6 33 # Per bank write bursts 52system.physmem.perBankRdBursts::7 50 # Per bank write bursts 53system.physmem.perBankRdBursts::8 42 # Per bank write bursts 54system.physmem.perBankRdBursts::9 38 # Per bank write bursts 55system.physmem.perBankRdBursts::10 28 # Per bank write bursts 56system.physmem.perBankRdBursts::11 34 # Per bank write bursts 57system.physmem.perBankRdBursts::12 15 # Per bank write bursts 58system.physmem.perBankRdBursts::13 120 # Per bank write bursts 59system.physmem.perBankRdBursts::14 67 # Per bank write bursts 60system.physmem.perBankRdBursts::15 37 # Per bank write bursts | 45system.physmem.perBankRdBursts::0 14 # Per bank write bursts 46system.physmem.perBankRdBursts::1 155 # Per bank write bursts 47system.physmem.perBankRdBursts::2 30 # Per bank write bursts 48system.physmem.perBankRdBursts::3 55 # Per bank write bursts 49system.physmem.perBankRdBursts::4 70 # Per bank write bursts 50system.physmem.perBankRdBursts::5 0 # Per bank write bursts 51system.physmem.perBankRdBursts::6 6 # Per bank write bursts 52system.physmem.perBankRdBursts::7 3 # Per bank write bursts 53system.physmem.perBankRdBursts::8 43 # Per bank write bursts 54system.physmem.perBankRdBursts::9 15 # Per bank write bursts 55system.physmem.perBankRdBursts::10 26 # Per bank write bursts 56system.physmem.perBankRdBursts::11 0 # Per bank write bursts 57system.physmem.perBankRdBursts::12 0 # Per bank write bursts 58system.physmem.perBankRdBursts::13 2 # Per bank write bursts 59system.physmem.perBankRdBursts::14 44 # Per bank write bursts 60system.physmem.perBankRdBursts::15 29 # Per bank write bursts |
| 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts 63system.physmem.perBankWrBursts::2 0 # Per bank write bursts 64system.physmem.perBankWrBursts::3 0 # Per bank write bursts 65system.physmem.perBankWrBursts::4 0 # Per bank write bursts 66system.physmem.perBankWrBursts::5 0 # Per bank write bursts 67system.physmem.perBankWrBursts::6 0 # Per bank write bursts 68system.physmem.perBankWrBursts::7 0 # Per bank write bursts 69system.physmem.perBankWrBursts::8 0 # Per bank write bursts 70system.physmem.perBankWrBursts::9 0 # Per bank write bursts 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 26630500 # Total gap between requests | 79system.physmem.totGap 25412500 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 86system.physmem.readPktSize::6 968 # Read request sizes (log2) | 86system.physmem.readPktSize::6 492 # Read request sizes (log2) |
| 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) | 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 94system.physmem.rdQLenPdf::0 332 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 313 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 185 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 94 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 74 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 74 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 202 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 289.584158 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 180.299588 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 295.891915 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 69 34.16% 34.16% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 55 27.23% 61.39% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 20 9.90% 71.29% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 16 7.92% 79.21% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 9 4.46% 83.66% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 7 3.47% 87.13% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 9 4.46% 91.58% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 1.49% 93.07% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 14 6.93% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 202 # Bytes accessed per row activation 204system.physmem.totQLat 15941250 # Total ticks spent queuing 205system.physmem.totMemAccLat 34091250 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 4840000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 16468.23 # Average queueing delay per DRAM burst | 190system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 284.647619 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 175.785516 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 296.753264 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 38 36.19% 36.19% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 31 29.52% 65.71% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 6 5.71% 71.43% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 9 8.57% 80.00% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 3 2.86% 82.86% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 4 3.81% 86.67% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 5 4.76% 91.43% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 2.86% 94.29% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation 204system.physmem.totQLat 8936250 # Total ticks spent queuing 205system.physmem.totMemAccLat 18161250 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 18163.11 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 35218.23 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 2323.65 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 36913.11 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1231.78 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 2323.65 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 1231.78 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 18.15 # Data bus utilization in percentage 216system.physmem.busUtilRead 18.15 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 9.62 # Data bus utilization in percentage 216system.physmem.busUtilRead 9.62 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 218system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing | 218system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing |
| 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 755 # Number of row buffer hits during reads | 220system.physmem.readRowHits 382 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 78.00 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 77.64 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 27510.85 # Average gap between requests 225system.physmem.pageHitRate 78.00 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 849660 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 436425 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 4191180 # Energy for read commands per rank (pJ) | 224system.physmem.avgGap 51651.42 # Average gap between requests 225system.physmem.pageHitRate 77.64 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 564060 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 288420 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 2377620 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) |
| 231system.physmem_0.actBackEnergy 6126930 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 5973030 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) | 231system.physmem_0.actBackEnergy 4052700 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 52800 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 7250970 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 244800 # Energy for precharge power-down per rank (pJ) |
| 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 236system.physmem_0.totalEnergy 19470105 # Total energy per rank (pJ) 237system.physmem_0.averagePower 730.243038 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 12953500 # Total Idle time Per DRAM Rank | 236system.physmem_0.totalEnergy 16675290 # Total energy per rank (pJ) 237system.physmem_0.averagePower 652.302186 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 16451750 # Total Idle time Per DRAM Rank |
| 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states | 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states |
| 242system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 12735000 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 13102250 # Time in different power states 245system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 330165 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 2720340 # Energy for read commands per rank (pJ) | 242system.physmem_0.memoryStateTime::PRE_PDN 637500 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 8201250 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 15903750 # Time in different power states 245system.physmem_1.actEnergy 221340 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 110055 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 1135260 # Energy for read commands per rank (pJ) |
| 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) | 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) |
| 250system.physmem_1.actBackEnergy 4611870 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 162240 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 6909540 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 373920 # Energy for precharge power-down per rank (pJ) | 250system.physmem_1.actBackEnergy 2074800 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 239040 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 8714160 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 492000 # Energy for precharge power-down per rank (pJ) |
| 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 255system.physmem_1.totalEnergy 17623155 # Total energy per rank (pJ) 256system.physmem_1.averagePower 660.971589 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 16131250 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 312000 # Time in different power states | 255system.physmem_1.totalEnergy 14830575 # Total energy per rank (pJ) 256system.physmem_1.averagePower 580.140824 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 20195750 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 443500 # Time in different power states |
| 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states | 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states |
| 261system.physmem_1.memoryStateTime::PRE_PDN 973000 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 9438250 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 15158250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 4864 # Number of BP lookups 266system.cpu.branchPred.condPredicted 2895 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 795 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 3714 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 1183 # Number of BTB hits | 261system.physmem_1.memoryStateTime::PRE_PDN 1279500 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 3943500 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 19116500 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 5883 # Number of BP lookups 266system.cpu.branchPred.condPredicted 3464 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 1044 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 4417 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 1219 # Number of BTB hits |
| 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 271system.cpu.branchPred.BTBHitPct 31.852450 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 710 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 762 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 147 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 615 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 133 # Number of mispredicted indirect branches. | 271system.cpu.branchPred.BTBHitPct 27.597917 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 791 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 1012 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 40 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 972 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 246 # Number of mispredicted indirect branches. |
| 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.fetch_hits 0 # ITB hits 280system.cpu.dtb.fetch_misses 0 # ITB misses 281system.cpu.dtb.fetch_acv 0 # ITB acv 282system.cpu.dtb.fetch_accesses 0 # ITB accesses | 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.fetch_hits 0 # ITB hits 280system.cpu.dtb.fetch_misses 0 # ITB misses 281system.cpu.dtb.fetch_acv 0 # ITB acv 282system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 283system.cpu.dtb.read_hits 4131 # DTB read hits 284system.cpu.dtb.read_misses 76 # DTB read misses | 283system.cpu.dtb.read_hits 4167 # DTB read hits 284system.cpu.dtb.read_misses 88 # DTB read misses |
| 285system.cpu.dtb.read_acv 0 # DTB read access violations | 285system.cpu.dtb.read_acv 0 # DTB read access violations |
| 286system.cpu.dtb.read_accesses 4207 # DTB read accesses 287system.cpu.dtb.write_hits 2011 # DTB write hits 288system.cpu.dtb.write_misses 48 # DTB write misses | 286system.cpu.dtb.read_accesses 4255 # DTB read accesses 287system.cpu.dtb.write_hits 2106 # DTB write hits 288system.cpu.dtb.write_misses 58 # DTB write misses |
| 289system.cpu.dtb.write_acv 0 # DTB write access violations | 289system.cpu.dtb.write_acv 0 # DTB write access violations |
| 290system.cpu.dtb.write_accesses 2059 # DTB write accesses 291system.cpu.dtb.data_hits 6142 # DTB hits 292system.cpu.dtb.data_misses 124 # DTB misses | 290system.cpu.dtb.write_accesses 2164 # DTB write accesses 291system.cpu.dtb.data_hits 6273 # DTB hits 292system.cpu.dtb.data_misses 146 # DTB misses |
| 293system.cpu.dtb.data_acv 0 # DTB access violations | 293system.cpu.dtb.data_acv 0 # DTB access violations |
| 294system.cpu.dtb.data_accesses 6266 # DTB accesses 295system.cpu.itb.fetch_hits 3836 # ITB hits 296system.cpu.itb.fetch_misses 50 # ITB misses | 294system.cpu.dtb.data_accesses 6419 # DTB accesses 295system.cpu.itb.fetch_hits 4394 # ITB hits 296system.cpu.itb.fetch_misses 52 # ITB misses |
| 297system.cpu.itb.fetch_acv 0 # ITB acv | 297system.cpu.itb.fetch_acv 0 # ITB acv |
| 298system.cpu.itb.fetch_accesses 3886 # ITB accesses | 298system.cpu.itb.fetch_accesses 4446 # ITB accesses |
| 299system.cpu.itb.read_hits 0 # DTB read hits 300system.cpu.itb.read_misses 0 # DTB read misses 301system.cpu.itb.read_acv 0 # DTB read access violations 302system.cpu.itb.read_accesses 0 # DTB read accesses 303system.cpu.itb.write_hits 0 # DTB write hits 304system.cpu.itb.write_misses 0 # DTB write misses 305system.cpu.itb.write_acv 0 # DTB write access violations 306system.cpu.itb.write_accesses 0 # DTB write accesses 307system.cpu.itb.data_hits 0 # DTB hits 308system.cpu.itb.data_misses 0 # DTB misses 309system.cpu.itb.data_acv 0 # DTB access violations 310system.cpu.itb.data_accesses 0 # DTB accesses | 299system.cpu.itb.read_hits 0 # DTB read hits 300system.cpu.itb.read_misses 0 # DTB read misses 301system.cpu.itb.read_acv 0 # DTB read access violations 302system.cpu.itb.read_accesses 0 # DTB read accesses 303system.cpu.itb.write_hits 0 # DTB write hits 304system.cpu.itb.write_misses 0 # DTB write misses 305system.cpu.itb.write_acv 0 # DTB write access violations 306system.cpu.itb.write_accesses 0 # DTB write accesses 307system.cpu.itb.data_hits 0 # DTB hits 308system.cpu.itb.data_misses 0 # DTB misses 309system.cpu.itb.data_acv 0 # DTB access violations 310system.cpu.itb.data_accesses 0 # DTB accesses |
| 311system.cpu.workload0.num_syscalls 17 # Number of system calls 312system.cpu.workload1.num_syscalls 17 # Number of system calls 313system.cpu.pwrStateResidencyTicks::ON 26661500 # Cumulative time (in ticks) in various power states 314system.cpu.numCycles 53324 # number of cpu cycles simulated | 311system.cpu.workload0.num_syscalls 18 # Number of system calls 312system.cpu.workload1.num_syscalls 18 # Number of system calls 313system.cpu.pwrStateResidencyTicks::ON 25563000 # Cumulative time (in ticks) in various power states 314system.cpu.numCycles 51127 # number of cpu cycles simulated |
| 315system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 316system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 315system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 316system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 317system.cpu.fetch.icacheStallCycles 748 # Number of cycles fetch is stalled on an Icache miss 318system.cpu.fetch.Insts 27869 # Number of instructions fetch has processed 319system.cpu.fetch.Branches 4864 # Number of branches that fetch encountered 320system.cpu.fetch.predictedBranches 2040 # Number of branches that fetch has predicted taken 321system.cpu.fetch.Cycles 9408 # Number of cycles fetch has run and was not squashing or blocked 322system.cpu.fetch.SquashCycles 875 # Number of cycles fetch has spent squashing 323system.cpu.fetch.MiscStallCycles 344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 324system.cpu.fetch.CacheLines 3836 # Number of cache lines fetched 325system.cpu.fetch.IcacheSquashes 566 # Number of outstanding Icache misses that were squashed 326system.cpu.fetch.rateDist::samples 26305 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::mean 1.059456 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::stdev 2.449327 # Number of instructions fetched each cycle (Total) | 317system.cpu.fetch.icacheStallCycles 960 # Number of cycles fetch is stalled on an Icache miss 318system.cpu.fetch.Insts 33549 # Number of instructions fetch has processed 319system.cpu.fetch.Branches 5883 # Number of branches that fetch encountered 320system.cpu.fetch.predictedBranches 2050 # Number of branches that fetch has predicted taken 321system.cpu.fetch.Cycles 9426 # Number of cycles fetch has run and was not squashing or blocked 322system.cpu.fetch.SquashCycles 1118 # Number of cycles fetch has spent squashing 323system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 324system.cpu.fetch.CacheLines 4394 # Number of cache lines fetched 325system.cpu.fetch.IcacheSquashes 660 # Number of outstanding Icache misses that were squashed 326system.cpu.fetch.rateDist::samples 17609 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::mean 1.905219 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::stdev 3.084149 # Number of instructions fetched each cycle (Total) |
| 329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 330system.cpu.fetch.rateDist::0 21280 80.90% 80.90% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::1 504 1.92% 82.81% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::2 391 1.49% 84.30% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::3 446 1.70% 86.00% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::4 478 1.82% 87.81% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::5 367 1.40% 89.21% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::6 469 1.78% 90.99% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::7 276 1.05% 92.04% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::8 2094 7.96% 100.00% # Number of instructions fetched each cycle (Total) | 330system.cpu.fetch.rateDist::0 11843 67.26% 67.26% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::1 481 2.73% 69.99% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::2 427 2.42% 72.41% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::3 478 2.71% 75.13% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::4 423 2.40% 77.53% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::5 397 2.25% 79.78% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::6 518 2.94% 82.72% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::7 341 1.94% 84.66% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::8 2701 15.34% 100.00% # Number of instructions fetched each cycle (Total) |
| 339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 342system.cpu.fetch.rateDist::total 26305 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.branchRate 0.091216 # Number of branch fetches per cycle 344system.cpu.fetch.rate 0.522635 # Number of inst fetches per cycle 345system.cpu.decode.IdleCycles 36539 # Number of cycles decode is idle 346system.cpu.decode.BlockedCycles 10373 # Number of cycles decode is blocked 347system.cpu.decode.RunCycles 3958 # Number of cycles decode is running 348system.cpu.decode.UnblockCycles 496 # Number of cycles decode is unblocking 349system.cpu.decode.SquashCycles 725 # Number of cycles decode is squashing 350system.cpu.decode.BranchResolved 405 # Number of times decode resolved a branch 351system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction 352system.cpu.decode.DecodedInsts 24588 # Number of instructions handled by decode 353system.cpu.decode.SquashedInsts 377 # Number of squashed instructions handled by decode 354system.cpu.rename.SquashCycles 725 # Number of cycles rename is squashing 355system.cpu.rename.IdleCycles 36883 # Number of cycles rename is idle 356system.cpu.rename.BlockCycles 3499 # Number of cycles rename is blocking 357system.cpu.rename.serializeStallCycles 1435 # count of cycles rename stalled for serializing inst 358system.cpu.rename.RunCycles 4115 # Number of cycles rename is running 359system.cpu.rename.UnblockCycles 5434 # Number of cycles rename is unblocking 360system.cpu.rename.RenamedInsts 23584 # Number of instructions processed by rename 361system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full 362system.cpu.rename.IQFullEvents 222 # Number of times rename has blocked due to IQ full 363system.cpu.rename.LQFullEvents 329 # Number of times rename has blocked due to LQ full 364system.cpu.rename.SQFullEvents 4703 # Number of times rename has blocked due to SQ full 365system.cpu.rename.RenamedOperands 17574 # Number of destination operands rename has renamed 366system.cpu.rename.RenameLookups 29532 # Number of register rename lookups that rename has made 367system.cpu.rename.int_rename_lookups 29514 # Number of integer rename lookups | 342system.cpu.fetch.rateDist::total 17609 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.branchRate 0.115066 # Number of branch fetches per cycle 344system.cpu.fetch.rate 0.656189 # Number of inst fetches per cycle 345system.cpu.decode.IdleCycles 18146 # Number of cycles decode is idle 346system.cpu.decode.BlockedCycles 10408 # Number of cycles decode is blocked 347system.cpu.decode.RunCycles 5085 # Number of cycles decode is running 348system.cpu.decode.UnblockCycles 609 # Number of cycles decode is unblocking 349system.cpu.decode.SquashCycles 960 # Number of cycles decode is squashing 350system.cpu.decode.BranchResolved 1283 # Number of times decode resolved a branch 351system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction 352system.cpu.decode.DecodedInsts 29203 # Number of instructions handled by decode 353system.cpu.decode.SquashedInsts 227 # Number of squashed instructions handled by decode 354system.cpu.rename.SquashCycles 960 # Number of cycles rename is squashing 355system.cpu.rename.IdleCycles 18571 # Number of cycles rename is idle 356system.cpu.rename.BlockCycles 3611 # Number of cycles rename is blocking 357system.cpu.rename.serializeStallCycles 1447 # count of cycles rename stalled for serializing inst 358system.cpu.rename.RunCycles 5248 # Number of cycles rename is running 359system.cpu.rename.UnblockCycles 5371 # Number of cycles rename is unblocking 360system.cpu.rename.RenamedInsts 27754 # Number of instructions processed by rename 361system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full 362system.cpu.rename.IQFullEvents 466 # Number of times rename has blocked due to IQ full 363system.cpu.rename.LQFullEvents 832 # Number of times rename has blocked due to LQ full 364system.cpu.rename.SQFullEvents 4294 # Number of times rename has blocked due to SQ full 365system.cpu.rename.RenamedOperands 20868 # Number of destination operands rename has renamed 366system.cpu.rename.RenameLookups 34818 # Number of register rename lookups that rename has made 367system.cpu.rename.int_rename_lookups 34800 # Number of integer rename lookups |
| 368system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups | 368system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups |
| 369system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed 370system.cpu.rename.UndoneMaps 8420 # Number of HB maps that are undone due to squashing 371system.cpu.rename.serializingInsts 57 # count of serializing insts renamed 372system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed 373system.cpu.rename.skidInsts 1617 # count of insts added to the skid buffer 374system.cpu.memDep0.insertedLoads 1925 # Number of loads inserted to the mem dependence unit. 375system.cpu.memDep0.insertedStores 1093 # Number of stores inserted to the mem dependence unit. 376system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. 377system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 378system.cpu.memDep1.insertedLoads 2578 # Number of loads inserted to the mem dependence unit. 379system.cpu.memDep1.insertedStores 1286 # Number of stores inserted to the mem dependence unit. 380system.cpu.memDep1.conflictingLoads 15 # Number of conflicting loads. 381system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores. 382system.cpu.iq.iqInstsAdded 21800 # Number of instructions added to the IQ (excludes non-spec) 383system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ 384system.cpu.iq.iqInstsIssued 19298 # Number of instructions issued 385system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued 386system.cpu.iq.iqSquashedInstsExamined 9080 # Number of squashed instructions iterated over during squash; mainly for profiling 387system.cpu.iq.iqSquashedOperandsExamined 4750 # Number of squashed operands that are examined and possibly removed from graph 388system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed 389system.cpu.iq.issued_per_cycle::samples 26305 # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::mean 0.733625 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::stdev 1.450843 # Number of insts issued each cycle | 369system.cpu.rename.CommittedMaps 9408 # Number of HB maps that are committed 370system.cpu.rename.UndoneMaps 11460 # Number of HB maps that are undone due to squashing 371system.cpu.rename.serializingInsts 54 # count of serializing insts renamed 372system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed 373system.cpu.rename.skidInsts 1221 # count of insts added to the skid buffer 374system.cpu.memDep0.insertedLoads 2635 # Number of loads inserted to the mem dependence unit. 375system.cpu.memDep0.insertedStores 1335 # Number of stores inserted to the mem dependence unit. 376system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. 377system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores. 378system.cpu.memDep1.insertedLoads 2668 # Number of loads inserted to the mem dependence unit. 379system.cpu.memDep1.insertedStores 1295 # Number of stores inserted to the mem dependence unit. 380system.cpu.memDep1.conflictingLoads 8 # Number of conflicting loads. 381system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 382system.cpu.iq.iqInstsAdded 25217 # Number of instructions added to the IQ (excludes non-spec) 383system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 384system.cpu.iq.iqInstsIssued 21059 # Number of instructions issued 385system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued 386system.cpu.iq.iqSquashedInstsExamined 12140 # Number of squashed instructions iterated over during squash; mainly for profiling 387system.cpu.iq.iqSquashedOperandsExamined 6785 # Number of squashed operands that are examined and possibly removed from graph 388system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed 389system.cpu.iq.issued_per_cycle::samples 17609 # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::mean 1.195923 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::stdev 2.068924 # Number of insts issued each cycle |
| 392system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 392system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 393system.cpu.iq.issued_per_cycle::0 18975 72.13% 72.13% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::1 2364 8.99% 81.12% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::2 1624 6.17% 87.30% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::3 1293 4.92% 92.21% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::4 1059 4.03% 96.24% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::5 566 2.15% 98.39% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::6 282 1.07% 99.46% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::7 87 0.33% 99.79% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::8 55 0.21% 100.00% # Number of insts issued each cycle | 393system.cpu.iq.issued_per_cycle::0 11762 66.80% 66.80% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::1 1075 6.10% 72.90% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::2 1081 6.14% 79.04% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::3 919 5.22% 84.26% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::4 899 5.11% 89.36% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::5 701 3.98% 93.34% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::6 574 3.26% 96.60% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::7 264 1.50% 98.10% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::8 334 1.90% 100.00% # Number of insts issued each cycle |
| 402system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 402system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 405system.cpu.iq.issued_per_cycle::total 26305 # Number of insts issued each cycle | 405system.cpu.iq.issued_per_cycle::total 17609 # Number of insts issued each cycle |
| 406system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 406system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 407system.cpu.iq.fu_full::IntAlu 29 9.60% 9.60% # attempts to use FU when none available 408system.cpu.iq.fu_full::IntMult 0 0.00% 9.60% # attempts to use FU when none available 409system.cpu.iq.fu_full::IntDiv 0 0.00% 9.60% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.60% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.60% # attempts to use FU when none available 412system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.60% # attempts to use FU when none available 413system.cpu.iq.fu_full::FloatMult 0 0.00% 9.60% # attempts to use FU when none available 414system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.60% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.60% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.60% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.60% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.60% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.60% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.60% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.60% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.60% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdMult 0 0.00% 9.60% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.60% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdShift 0 0.00% 9.60% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.60% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.60% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.60% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.60% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.60% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.60% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.60% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.60% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.60% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.60% # attempts to use FU when none available 438system.cpu.iq.fu_full::MemRead 193 63.91% 73.51% # attempts to use FU when none available 439system.cpu.iq.fu_full::MemWrite 77 25.50% 99.01% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.01% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatMemWrite 3 0.99% 100.00% # attempts to use FU when none available | 407system.cpu.iq.fu_full::IntAlu 153 31.03% 31.03% # attempts to use FU when none available 408system.cpu.iq.fu_full::IntMult 0 0.00% 31.03% # attempts to use FU when none available 409system.cpu.iq.fu_full::IntDiv 0 0.00% 31.03% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.03% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.03% # attempts to use FU when none available 412system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.03% # attempts to use FU when none available 413system.cpu.iq.fu_full::FloatMult 0 0.00% 31.03% # attempts to use FU when none available 414system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 31.03% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.03% # attempts to use FU when none available 416system.cpu.iq.fu_full::FloatMisc 0 0.00% 31.03% # attempts to use FU when none available 417system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.03% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.03% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.03% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.03% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.03% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.03% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.03% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdMult 0 0.00% 31.03% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.03% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdShift 0 0.00% 31.03% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.03% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.03% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.03% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.03% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.03% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.03% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.03% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.03% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.03% # attempts to use FU when none available 436system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.03% # attempts to use FU when none available 437system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.03% # attempts to use FU when none available 438system.cpu.iq.fu_full::MemRead 227 46.04% 77.08% # attempts to use FU when none available 439system.cpu.iq.fu_full::MemWrite 109 22.11% 99.19% # attempts to use FU when none available 440system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.19% # attempts to use FU when none available 441system.cpu.iq.fu_full::FloatMemWrite 4 0.81% 100.00% # attempts to use FU when none available |
| 442system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 443system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 444system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued | 442system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 443system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 444system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued |
| 445system.cpu.iq.FU_type_0::IntAlu 5886 66.05% 66.07% # Type of FU issued 446system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.08% # Type of FU issued 447system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.10% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.10% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued 454system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.10% # Type of FU issued 455system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued 476system.cpu.iq.FU_type_0::MemRead 2014 22.60% 88.70% # Type of FU issued 477system.cpu.iq.FU_type_0::MemWrite 999 11.21% 99.91% # Type of FU issued 478system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.92% # Type of FU issued 479system.cpu.iq.FU_type_0::FloatMemWrite 7 0.08% 100.00% # Type of FU issued | 445system.cpu.iq.FU_type_0::IntAlu 7042 67.16% 67.18% # Type of FU issued 446system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.18% # Type of FU issued 447system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.18% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.20% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued 450system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued 451system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued 452system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.20% # Type of FU issued 453system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued 454system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.20% # Type of FU issued 455system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued 470system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued 471system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued 476system.cpu.iq.FU_type_0::MemRead 2285 21.79% 88.99% # Type of FU issued 477system.cpu.iq.FU_type_0::MemWrite 1146 10.93% 99.92% # Type of FU issued 478system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.93% # Type of FU issued 479system.cpu.iq.FU_type_0::FloatMemWrite 7 0.07% 100.00% # Type of FU issued |
| 480system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 481system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 480system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 481system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 482system.cpu.iq.FU_type_0::total 8912 # Type of FU issued | 482system.cpu.iq.FU_type_0::total 10486 # Type of FU issued |
| 483system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued | 483system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued |
| 484system.cpu.iq.FU_type_1::IntAlu 6849 65.94% 65.96% # Type of FU issued 485system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued 486system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.97% # Type of FU issued 487system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Type of FU issued 488system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued 489system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued 490system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued 491system.cpu.iq.FU_type_1::FloatMultAcc 0 0.00% 65.99% # Type of FU issued 492system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued 493system.cpu.iq.FU_type_1::FloatMisc 0 0.00% 65.99% # Type of FU issued 494system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued 495system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued 496system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued 497system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.99% # Type of FU issued 498system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.99% # Type of FU issued 499system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.99% # Type of FU issued 500system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.99% # Type of FU issued 501system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.99% # Type of FU issued 502system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.99% # Type of FU issued 503system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.99% # Type of FU issued 504system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued 505system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.99% # Type of FU issued 506system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued 507system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued 508system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued 509system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued 510system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued 511system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued 512system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued 513system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued 514system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued 515system.cpu.iq.FU_type_1::MemRead 2410 23.20% 89.20% # Type of FU issued 516system.cpu.iq.FU_type_1::MemWrite 1114 10.73% 99.92% # Type of FU issued | 484system.cpu.iq.FU_type_1::IntAlu 7119 67.33% 67.35% # Type of FU issued 485system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.36% # Type of FU issued 486system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.36% # Type of FU issued 487system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.38% # Type of FU issued 488system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.38% # Type of FU issued 489system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.38% # Type of FU issued 490system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.38% # Type of FU issued 491system.cpu.iq.FU_type_1::FloatMultAcc 0 0.00% 67.38% # Type of FU issued 492system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.38% # Type of FU issued 493system.cpu.iq.FU_type_1::FloatMisc 0 0.00% 67.38% # Type of FU issued 494system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.38% # Type of FU issued 495system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.38% # Type of FU issued 496system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.38% # Type of FU issued 497system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.38% # Type of FU issued 498system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.38% # Type of FU issued 499system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.38% # Type of FU issued 500system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.38% # Type of FU issued 501system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.38% # Type of FU issued 502system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.38% # Type of FU issued 503system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.38% # Type of FU issued 504system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.38% # Type of FU issued 505system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.38% # Type of FU issued 506system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.38% # Type of FU issued 507system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.38% # Type of FU issued 508system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.38% # Type of FU issued 509system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.38% # Type of FU issued 510system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.38% # Type of FU issued 511system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.38% # Type of FU issued 512system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.38% # Type of FU issued 513system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.38% # Type of FU issued 514system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.38% # Type of FU issued 515system.cpu.iq.FU_type_1::MemRead 2310 21.85% 89.23% # Type of FU issued 516system.cpu.iq.FU_type_1::MemWrite 1131 10.70% 99.92% # Type of FU issued |
| 517system.cpu.iq.FU_type_1::FloatMemRead 1 0.01% 99.93% # Type of FU issued 518system.cpu.iq.FU_type_1::FloatMemWrite 7 0.07% 100.00% # Type of FU issued 519system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 520system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 517system.cpu.iq.FU_type_1::FloatMemRead 1 0.01% 99.93% # Type of FU issued 518system.cpu.iq.FU_type_1::FloatMemWrite 7 0.07% 100.00% # Type of FU issued 519system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 520system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 521system.cpu.iq.FU_type_1::total 10386 # Type of FU issued 522system.cpu.iq.FU_type::total 19298 0.00% 0.00% # Type of FU issued 523system.cpu.iq.rate 0.361901 # Inst issue rate 524system.cpu.iq.fu_busy_cnt::0 154 # FU busy when requested 525system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested 526system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested 527system.cpu.iq.fu_busy_rate::0 0.007980 # FU busy rate (busy events/executed inst) 528system.cpu.iq.fu_busy_rate::1 0.007669 # FU busy rate (busy events/executed inst) 529system.cpu.iq.fu_busy_rate::total 0.015649 # FU busy rate (busy events/executed inst) 530system.cpu.iq.int_inst_queue_reads 65211 # Number of integer instruction queue reads 531system.cpu.iq.int_inst_queue_writes 30942 # Number of integer instruction queue writes 532system.cpu.iq.int_inst_queue_wakeup_accesses 17509 # Number of integer instruction queue wakeup accesses 533system.cpu.iq.fp_inst_queue_reads 43 # Number of floating instruction queue reads | 521system.cpu.iq.FU_type_1::total 10573 # Type of FU issued 522system.cpu.iq.FU_type::total 21059 0.00% 0.00% # Type of FU issued 523system.cpu.iq.rate 0.411896 # Inst issue rate 524system.cpu.iq.fu_busy_cnt::0 245 # FU busy when requested 525system.cpu.iq.fu_busy_cnt::1 248 # FU busy when requested 526system.cpu.iq.fu_busy_cnt::total 493 # FU busy when requested 527system.cpu.iq.fu_busy_rate::0 0.011634 # FU busy rate (busy events/executed inst) 528system.cpu.iq.fu_busy_rate::1 0.011776 # FU busy rate (busy events/executed inst) 529system.cpu.iq.fu_busy_rate::total 0.023410 # FU busy rate (busy events/executed inst) 530system.cpu.iq.int_inst_queue_reads 60282 # Number of integer instruction queue reads 531system.cpu.iq.int_inst_queue_writes 37413 # Number of integer instruction queue writes 532system.cpu.iq.int_inst_queue_wakeup_accesses 19074 # Number of integer instruction queue wakeup accesses 533system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads |
| 534system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 535system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses | 534system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 535system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses |
| 536system.cpu.iq.int_alu_accesses 19573 # Number of integer alu accesses 537system.cpu.iq.fp_alu_accesses 23 # Number of floating point alu accesses 538system.cpu.iew.lsq.thread0.forwLoads 39 # Number of loads that had data forwarded from stores | 536system.cpu.iq.int_alu_accesses 21524 # Number of integer alu accesses 537system.cpu.iq.fp_alu_accesses 24 # Number of floating point alu accesses 538system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores |
| 539system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 539system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 540system.cpu.iew.lsq.thread0.squashedLoads 740 # Number of loads squashed | 540system.cpu.iew.lsq.thread0.squashedLoads 1418 # Number of loads squashed |
| 541system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed | 541system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed |
| 542system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations 543system.cpu.iew.lsq.thread0.squashedStores 228 # Number of stores squashed | 542system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations 543system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed |
| 544system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 545system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 546system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled | 544system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 545system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 546system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled |
| 547system.cpu.iew.lsq.thread0.cacheBlocked 290 # Number of times an access to memory failed due to the cache being blocked 548system.cpu.iew.lsq.thread1.forwLoads 97 # Number of loads that had data forwarded from stores | 547system.cpu.iew.lsq.thread0.cacheBlocked 58 # Number of times an access to memory failed due to the cache being blocked 548system.cpu.iew.lsq.thread1.forwLoads 83 # Number of loads that had data forwarded from stores |
| 549system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address | 549system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 550system.cpu.iew.lsq.thread1.squashedLoads 1393 # Number of loads squashed 551system.cpu.iew.lsq.thread1.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed 552system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations 553system.cpu.iew.lsq.thread1.squashedStores 421 # Number of stores squashed | 550system.cpu.iew.lsq.thread1.squashedLoads 1434 # Number of loads squashed 551system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed 552system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations 553system.cpu.iew.lsq.thread1.squashedStores 405 # Number of stores squashed |
| 554system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 555system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 556system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled | 554system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 555system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 556system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled |
| 557system.cpu.iew.lsq.thread1.cacheBlocked 234 # Number of times an access to memory failed due to the cache being blocked | 557system.cpu.iew.lsq.thread1.cacheBlocked 57 # Number of times an access to memory failed due to the cache being blocked |
| 558system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 558system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 559system.cpu.iew.iewSquashCycles 725 # Number of cycles IEW is squashing 560system.cpu.iew.iewBlockCycles 1992 # Number of cycles IEW is blocking 561system.cpu.iew.iewUnblockCycles 420 # Number of cycles IEW is unblocking 562system.cpu.iew.iewDispatchedInsts 21985 # Number of instructions dispatched to IQ 563system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch 564system.cpu.iew.iewDispLoadInsts 4503 # Number of dispatched load instructions 565system.cpu.iew.iewDispStoreInsts 2379 # Number of dispatched store instructions 566system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions 567system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall 568system.cpu.iew.iewLSQFullEvents 390 # Number of times the LSQ has become full, causing a stall 569system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations 570system.cpu.iew.predictedTakenIncorrect 134 # Number of branches that were predicted taken incorrectly 571system.cpu.iew.predictedNotTakenIncorrect 638 # Number of branches that were predicted not taken incorrectly 572system.cpu.iew.branchMispredicts 772 # Number of branch mispredicts detected at execute 573system.cpu.iew.iewExecutedInsts 18590 # Number of executed instructions 574system.cpu.iew.iewExecLoadInsts::0 1946 # Number of load instructions executed 575system.cpu.iew.iewExecLoadInsts::1 2264 # Number of load instructions executed 576system.cpu.iew.iewExecLoadInsts::total 4210 # Number of load instructions executed 577system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute | 559system.cpu.iew.iewSquashCycles 960 # Number of cycles IEW is squashing 560system.cpu.iew.iewBlockCycles 2021 # Number of cycles IEW is blocking 561system.cpu.iew.iewUnblockCycles 347 # Number of cycles IEW is unblocking 562system.cpu.iew.iewDispatchedInsts 25404 # Number of instructions dispatched to IQ 563system.cpu.iew.iewDispSquashedInsts 199 # Number of squashed instructions skipped by dispatch 564system.cpu.iew.iewDispLoadInsts 5303 # Number of dispatched load instructions 565system.cpu.iew.iewDispStoreInsts 2630 # Number of dispatched store instructions 566system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions 567system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 568system.cpu.iew.iewLSQFullEvents 341 # Number of times the LSQ has become full, causing a stall 569system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations 570system.cpu.iew.predictedTakenIncorrect 167 # Number of branches that were predicted taken incorrectly 571system.cpu.iew.predictedNotTakenIncorrect 860 # Number of branches that were predicted not taken incorrectly 572system.cpu.iew.branchMispredicts 1027 # Number of branch mispredicts detected at execute 573system.cpu.iew.iewExecutedInsts 19999 # Number of executed instructions 574system.cpu.iew.iewExecLoadInsts::0 2117 # Number of load instructions executed 575system.cpu.iew.iewExecLoadInsts::1 2148 # Number of load instructions executed 576system.cpu.iew.iewExecLoadInsts::total 4265 # Number of load instructions executed 577system.cpu.iew.iewExecSquashedInsts 1060 # Number of squashed instructions skipped in execute |
| 578system.cpu.iew.exec_swp::0 0 # number of swp insts executed 579system.cpu.iew.exec_swp::1 0 # number of swp insts executed 580system.cpu.iew.exec_swp::total 0 # number of swp insts executed | 578system.cpu.iew.exec_swp::0 0 # number of swp insts executed 579system.cpu.iew.exec_swp::1 0 # number of swp insts executed 580system.cpu.iew.exec_swp::total 0 # number of swp insts executed |
| 581system.cpu.iew.exec_nop::0 63 # number of nop insts executed 582system.cpu.iew.exec_nop::1 71 # number of nop insts executed 583system.cpu.iew.exec_nop::total 134 # number of nop insts executed 584system.cpu.iew.exec_refs::0 2943 # number of memory reference insts executed 585system.cpu.iew.exec_refs::1 3338 # number of memory reference insts executed 586system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed 587system.cpu.iew.exec_branches::0 1393 # Number of branches executed 588system.cpu.iew.exec_branches::1 1580 # Number of branches executed 589system.cpu.iew.exec_branches::total 2973 # Number of branches executed 590system.cpu.iew.exec_stores::0 997 # Number of stores executed 591system.cpu.iew.exec_stores::1 1074 # Number of stores executed 592system.cpu.iew.exec_stores::total 2071 # Number of stores executed 593system.cpu.iew.exec_rate 0.348624 # Inst execution rate 594system.cpu.iew.wb_sent::0 8287 # cumulative count of insts sent to commit 595system.cpu.iew.wb_sent::1 9496 # cumulative count of insts sent to commit 596system.cpu.iew.wb_sent::total 17783 # cumulative count of insts sent to commit 597system.cpu.iew.wb_count::0 8202 # cumulative count of insts written-back 598system.cpu.iew.wb_count::1 9327 # cumulative count of insts written-back 599system.cpu.iew.wb_count::total 17529 # cumulative count of insts written-back 600system.cpu.iew.wb_producers::0 4343 # num instructions producing a value 601system.cpu.iew.wb_producers::1 4920 # num instructions producing a value 602system.cpu.iew.wb_producers::total 9263 # num instructions producing a value 603system.cpu.iew.wb_consumers::0 5887 # num instructions consuming a value 604system.cpu.iew.wb_consumers::1 6620 # num instructions consuming a value 605system.cpu.iew.wb_consumers::total 12507 # num instructions consuming a value 606system.cpu.iew.wb_rate::0 0.153814 # insts written-back per cycle 607system.cpu.iew.wb_rate::1 0.174912 # insts written-back per cycle 608system.cpu.iew.wb_rate::total 0.328726 # insts written-back per cycle 609system.cpu.iew.wb_fanout::0 0.737727 # average fanout of values written-back 610system.cpu.iew.wb_fanout::1 0.743202 # average fanout of values written-back 611system.cpu.iew.wb_fanout::total 0.740625 # average fanout of values written-back 612system.cpu.commit.commitSquashedInsts 9130 # The number of squashed insts skipped by commit 613system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards 614system.cpu.commit.branchMispredicts 646 # The number of times a branch was mispredicted 615system.cpu.commit.committed_per_cycle::samples 26287 # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::mean 0.487085 # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::stdev 1.404867 # Number of insts commited each cycle | 581system.cpu.iew.exec_nop::0 69 # number of nop insts executed 582system.cpu.iew.exec_nop::1 69 # number of nop insts executed 583system.cpu.iew.exec_nop::total 138 # number of nop insts executed 584system.cpu.iew.exec_refs::0 3217 # number of memory reference insts executed 585system.cpu.iew.exec_refs::1 3234 # number of memory reference insts executed 586system.cpu.iew.exec_refs::total 6451 # number of memory reference insts executed 587system.cpu.iew.exec_branches::0 1607 # Number of branches executed 588system.cpu.iew.exec_branches::1 1627 # Number of branches executed 589system.cpu.iew.exec_branches::total 3234 # Number of branches executed 590system.cpu.iew.exec_stores::0 1100 # Number of stores executed 591system.cpu.iew.exec_stores::1 1086 # Number of stores executed 592system.cpu.iew.exec_stores::total 2186 # Number of stores executed 593system.cpu.iew.exec_rate 0.391163 # Inst execution rate 594system.cpu.iew.wb_sent::0 9679 # cumulative count of insts sent to commit 595system.cpu.iew.wb_sent::1 9769 # cumulative count of insts sent to commit 596system.cpu.iew.wb_sent::total 19448 # cumulative count of insts sent to commit 597system.cpu.iew.wb_count::0 9504 # cumulative count of insts written-back 598system.cpu.iew.wb_count::1 9590 # cumulative count of insts written-back 599system.cpu.iew.wb_count::total 19094 # cumulative count of insts written-back 600system.cpu.iew.wb_producers::0 4946 # num instructions producing a value 601system.cpu.iew.wb_producers::1 5011 # num instructions producing a value 602system.cpu.iew.wb_producers::total 9957 # num instructions producing a value 603system.cpu.iew.wb_consumers::0 6500 # num instructions consuming a value 604system.cpu.iew.wb_consumers::1 6565 # num instructions consuming a value 605system.cpu.iew.wb_consumers::total 13065 # num instructions consuming a value 606system.cpu.iew.wb_rate::0 0.185890 # insts written-back per cycle 607system.cpu.iew.wb_rate::1 0.187572 # insts written-back per cycle 608system.cpu.iew.wb_rate::total 0.373462 # insts written-back per cycle 609system.cpu.iew.wb_fanout::0 0.760923 # average fanout of values written-back 610system.cpu.iew.wb_fanout::1 0.763290 # average fanout of values written-back 611system.cpu.iew.wb_fanout::total 0.762113 # average fanout of values written-back 612system.cpu.commit.commitSquashedInsts 12156 # The number of squashed insts skipped by commit 613system.cpu.commit.commitNonSpecStalls 36 # The number of times commit has been forced to stall to communicate backwards 614system.cpu.commit.branchMispredicts 887 # The number of times a branch was mispredicted 615system.cpu.commit.committed_per_cycle::samples 17042 # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::mean 0.772151 # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::stdev 1.826014 # Number of insts commited each cycle |
| 618system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 618system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 619system.cpu.commit.committed_per_cycle::0 21303 81.04% 81.04% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::1 2500 9.51% 90.55% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::2 926 3.52% 94.07% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::3 402 1.53% 95.60% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::4 249 0.95% 96.55% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::5 154 0.59% 97.14% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::6 214 0.81% 97.95% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::7 116 0.44% 98.39% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::8 423 1.61% 100.00% # Number of insts commited each cycle | 619system.cpu.commit.committed_per_cycle::0 13049 76.57% 76.57% # Number of insts commited each cycle 620system.cpu.commit.committed_per_cycle::1 1202 7.05% 83.62% # Number of insts commited each cycle 621system.cpu.commit.committed_per_cycle::2 934 5.48% 89.10% # Number of insts commited each cycle 622system.cpu.commit.committed_per_cycle::3 454 2.66% 91.77% # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::4 336 1.97% 93.74% # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::5 195 1.14% 94.88% # Number of insts commited each cycle 625system.cpu.commit.committed_per_cycle::6 209 1.23% 96.11% # Number of insts commited each cycle 626system.cpu.commit.committed_per_cycle::7 150 0.88% 96.99% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::8 513 3.01% 100.00% # Number of insts commited each cycle |
| 628system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 628system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 631system.cpu.commit.committed_per_cycle::total 26287 # Number of insts commited each cycle 632system.cpu.commit.committedInsts::0 6402 # Number of instructions committed 633system.cpu.commit.committedInsts::1 6402 # Number of instructions committed 634system.cpu.commit.committedInsts::total 12804 # Number of instructions committed 635system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed 636system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed 637system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed | 631system.cpu.commit.committed_per_cycle::total 17042 # Number of insts commited each cycle 632system.cpu.commit.committedInsts::0 6547 # Number of instructions committed 633system.cpu.commit.committedInsts::1 6612 # Number of instructions committed 634system.cpu.commit.committedInsts::total 13159 # Number of instructions committed 635system.cpu.commit.committedOps::0 6547 # Number of ops (including micro ops) committed 636system.cpu.commit.committedOps::1 6612 # Number of ops (including micro ops) committed 637system.cpu.commit.committedOps::total 13159 # Number of ops (including micro ops) committed |
| 638system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 639system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 640system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed | 638system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 639system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed 640system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed |
| 641system.cpu.commit.refs::0 2050 # Number of memory references committed 642system.cpu.commit.refs::1 2050 # Number of memory references committed 643system.cpu.commit.refs::total 4100 # Number of memory references committed 644system.cpu.commit.loads::0 1185 # Number of loads committed 645system.cpu.commit.loads::1 1185 # Number of loads committed 646system.cpu.commit.loads::total 2370 # Number of loads committed | 641system.cpu.commit.refs::0 2102 # Number of memory references committed 642system.cpu.commit.refs::1 2124 # Number of memory references committed 643system.cpu.commit.refs::total 4226 # Number of memory references committed 644system.cpu.commit.loads::0 1217 # Number of loads committed 645system.cpu.commit.loads::1 1234 # Number of loads committed 646system.cpu.commit.loads::total 2451 # Number of loads committed |
| 647system.cpu.commit.membars::0 0 # Number of memory barriers committed 648system.cpu.commit.membars::1 0 # Number of memory barriers committed 649system.cpu.commit.membars::total 0 # Number of memory barriers committed | 647system.cpu.commit.membars::0 0 # Number of memory barriers committed 648system.cpu.commit.membars::1 0 # Number of memory barriers committed 649system.cpu.commit.membars::total 0 # Number of memory barriers committed |
| 650system.cpu.commit.branches::0 1056 # Number of branches committed 651system.cpu.commit.branches::1 1056 # Number of branches committed 652system.cpu.commit.branches::total 2112 # Number of branches committed | 650system.cpu.commit.branches::0 1082 # Number of branches committed 651system.cpu.commit.branches::1 1095 # Number of branches committed 652system.cpu.commit.branches::total 2177 # Number of branches committed |
| 653system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 654system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 655system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. | 653system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions. 654system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions. 655system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions. |
| 656system.cpu.commit.int_insts::0 6319 # Number of committed integer instructions. 657system.cpu.commit.int_insts::1 6319 # Number of committed integer instructions. 658system.cpu.commit.int_insts::total 12638 # Number of committed integer instructions. 659system.cpu.commit.function_calls::0 127 # Number of function calls committed. 660system.cpu.commit.function_calls::1 127 # Number of function calls committed. 661system.cpu.commit.function_calls::total 254 # Number of function calls committed. 662system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 663system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction 664system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction 665system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction 666system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction 667system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction 668system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction 669system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction 670system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction 671system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction 673system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 694system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction 695system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction | 656system.cpu.commit.int_insts::0 6462 # Number of committed integer instructions. 657system.cpu.commit.int_insts::1 6526 # Number of committed integer instructions. 658system.cpu.commit.int_insts::total 12988 # Number of committed integer instructions. 659system.cpu.commit.function_calls::0 132 # Number of function calls committed. 660system.cpu.commit.function_calls::1 133 # Number of function calls committed. 661system.cpu.commit.function_calls::total 265 # Number of function calls committed. 662system.cpu.commit.op_class_0::No_OpClass 19 0.29% 0.29% # Class of committed instruction 663system.cpu.commit.op_class_0::IntAlu 4423 67.56% 67.85% # Class of committed instruction 664system.cpu.commit.op_class_0::IntMult 1 0.02% 67.86% # Class of committed instruction 665system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.86% # Class of committed instruction 666system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.89% # Class of committed instruction 667system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.89% # Class of committed instruction 668system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.89% # Class of committed instruction 669system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.89% # Class of committed instruction 670system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.89% # Class of committed instruction 671system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.89% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.89% # Class of committed instruction 673system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.89% # Class of committed instruction 674system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.89% # Class of committed instruction 675system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.89% # Class of committed instruction 676system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.89% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.89% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.89% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.89% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.89% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.89% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.89% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.89% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.89% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.89% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.89% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.89% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.89% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.89% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.89% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.89% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.89% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.89% # Class of committed instruction 694system.cpu.commit.op_class_0::MemRead 1216 18.57% 86.47% # Class of committed instruction 695system.cpu.commit.op_class_0::MemWrite 878 13.41% 99.88% # Class of committed instruction |
| 696system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction 697system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction 698system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 699system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 696system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction 697system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction 698system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 699system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 700system.cpu.commit.op_class_0::total 6402 # Class of committed instruction 701system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction 702system.cpu.commit.op_class_1::IntAlu 4330 67.64% 67.93% # Class of committed instruction 703system.cpu.commit.op_class_1::IntMult 1 0.02% 67.95% # Class of committed instruction 704system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.95% # Class of committed instruction 705system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Class of committed instruction 706system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction 707system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction 708system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction 709system.cpu.commit.op_class_1::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction 710system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction 711system.cpu.commit.op_class_1::FloatMisc 0 0.00% 67.98% # Class of committed instruction 712system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction 713system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction 714system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction 715system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.98% # Class of committed instruction 716system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.98% # Class of committed instruction 717system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.98% # Class of committed instruction 718system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.98% # Class of committed instruction 719system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.98% # Class of committed instruction 720system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction 721system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.98% # Class of committed instruction 722system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction 723system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.98% # Class of committed instruction 724system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction 725system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction 726system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction 727system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction 728system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction 729system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction 730system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction 731system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 732system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 733system.cpu.commit.op_class_1::MemRead 1184 18.49% 86.47% # Class of committed instruction 734system.cpu.commit.op_class_1::MemWrite 858 13.40% 99.88% # Class of committed instruction | 700system.cpu.commit.op_class_0::total 6547 # Class of committed instruction 701system.cpu.commit.op_class_1::No_OpClass 19 0.29% 0.29% # Class of committed instruction 702system.cpu.commit.op_class_1::IntAlu 4466 67.54% 67.83% # Class of committed instruction 703system.cpu.commit.op_class_1::IntMult 1 0.02% 67.85% # Class of committed instruction 704system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.85% # Class of committed instruction 705system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.88% # Class of committed instruction 706system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.88% # Class of committed instruction 707system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.88% # Class of committed instruction 708system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.88% # Class of committed instruction 709system.cpu.commit.op_class_1::FloatMultAcc 0 0.00% 67.88% # Class of committed instruction 710system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.88% # Class of committed instruction 711system.cpu.commit.op_class_1::FloatMisc 0 0.00% 67.88% # Class of committed instruction 712system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.88% # Class of committed instruction 713system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.88% # Class of committed instruction 714system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction 715system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.88% # Class of committed instruction 716system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.88% # Class of committed instruction 717system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.88% # Class of committed instruction 718system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.88% # Class of committed instruction 719system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.88% # Class of committed instruction 720system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction 721system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.88% # Class of committed instruction 722system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction 723system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.88% # Class of committed instruction 724system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction 725system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction 726system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction 727system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction 728system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction 729system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction 730system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction 731system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction 732system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction 733system.cpu.commit.op_class_1::MemRead 1233 18.65% 86.52% # Class of committed instruction 734system.cpu.commit.op_class_1::MemWrite 883 13.35% 99.88% # Class of committed instruction |
| 735system.cpu.commit.op_class_1::FloatMemRead 1 0.02% 99.89% # Class of committed instruction 736system.cpu.commit.op_class_1::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction 737system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction 738system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction | 735system.cpu.commit.op_class_1::FloatMemRead 1 0.02% 99.89% # Class of committed instruction 736system.cpu.commit.op_class_1::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction 737system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction 738system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| 739system.cpu.commit.op_class_1::total 6402 # Class of committed instruction 740system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction 741system.cpu.commit.bw_lim_events 423 # number cycles where commit BW limit reached 742system.cpu.rob.rob_reads 113065 # The number of ROB reads 743system.cpu.rob.rob_writes 45570 # The number of ROB writes 744system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself 745system.cpu.idleCycles 27019 # Total number of cycles that the CPU has spent unscheduled due to idling 746system.cpu.committedInsts::0 6385 # Number of Instructions Simulated 747system.cpu.committedInsts::1 6385 # Number of Instructions Simulated 748system.cpu.committedInsts::total 12770 # Number of Instructions Simulated 749system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated 750system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated 751system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated 752system.cpu.cpi::0 8.351449 # CPI: Cycles Per Instruction 753system.cpu.cpi::1 8.351449 # CPI: Cycles Per Instruction 754system.cpu.cpi_total 4.175724 # CPI: Total CPI of All Threads 755system.cpu.ipc::0 0.119740 # IPC: Instructions Per Cycle 756system.cpu.ipc::1 0.119740 # IPC: Instructions Per Cycle 757system.cpu.ipc_total 0.239479 # IPC: Total IPC of All Threads 758system.cpu.int_regfile_reads 23483 # number of integer regfile reads 759system.cpu.int_regfile_writes 13138 # number of integer regfile writes | 739system.cpu.commit.op_class_1::total 6612 # Class of committed instruction 740system.cpu.commit.op_class::total 13159 0.00% 0.00% # Class of committed instruction 741system.cpu.commit.bw_lim_events 513 # number cycles where commit BW limit reached 742system.cpu.rob.rob_reads 93105 # The number of ROB reads 743system.cpu.rob.rob_writes 52882 # The number of ROB writes 744system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself 745system.cpu.idleCycles 33518 # Total number of cycles that the CPU has spent unscheduled due to idling 746system.cpu.committedInsts::0 6530 # Number of Instructions Simulated 747system.cpu.committedInsts::1 6595 # Number of Instructions Simulated 748system.cpu.committedInsts::total 13125 # Number of Instructions Simulated 749system.cpu.committedOps::0 6530 # Number of Ops (including micro ops) Simulated 750system.cpu.committedOps::1 6595 # Number of Ops (including micro ops) Simulated 751system.cpu.committedOps::total 13125 # Number of Ops (including micro ops) Simulated 752system.cpu.cpi::0 7.829556 # CPI: Cycles Per Instruction 753system.cpu.cpi::1 7.752388 # CPI: Cycles Per Instruction 754system.cpu.cpi_total 3.895390 # CPI: Total CPI of All Threads 755system.cpu.ipc::0 0.127721 # IPC: Instructions Per Cycle 756system.cpu.ipc::1 0.128993 # IPC: Instructions Per Cycle 757system.cpu.ipc_total 0.256714 # IPC: Total IPC of All Threads 758system.cpu.int_regfile_reads 25576 # number of integer regfile reads 759system.cpu.int_regfile_writes 14448 # number of integer regfile writes |
| 760system.cpu.fp_regfile_reads 16 # number of floating regfile reads 761system.cpu.fp_regfile_writes 4 # number of floating regfile writes 762system.cpu.misc_regfile_reads 2 # number of misc regfile reads 763system.cpu.misc_regfile_writes 2 # number of misc regfile writes | 760system.cpu.fp_regfile_reads 16 # number of floating regfile reads 761system.cpu.fp_regfile_writes 4 # number of floating regfile writes 762system.cpu.misc_regfile_reads 2 # number of misc regfile reads 763system.cpu.misc_regfile_writes 2 # number of misc regfile writes |
| 764system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states | 764system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states |
| 765system.cpu.dcache.tags.replacements::0 0 # number of replacements 766system.cpu.dcache.tags.replacements::1 0 # number of replacements 767system.cpu.dcache.tags.replacements::total 0 # number of replacements | 765system.cpu.dcache.tags.replacements::0 0 # number of replacements 766system.cpu.dcache.tags.replacements::1 0 # number of replacements 767system.cpu.dcache.tags.replacements::total 0 # number of replacements |
| 768system.cpu.dcache.tags.tagsinuse 216.020896 # Cycle average of tags in use 769system.cpu.dcache.tags.total_refs 4237 # Total number of references to valid blocks. 770system.cpu.dcache.tags.sampled_refs 342 # Sample count of references to valid blocks. 771system.cpu.dcache.tags.avg_refs 12.388889 # Average number of references to valid blocks. | 768system.cpu.dcache.tags.tagsinuse 108.945725 # Cycle average of tags in use 769system.cpu.dcache.tags.total_refs 4625 # Total number of references to valid blocks. 770system.cpu.dcache.tags.sampled_refs 175 # Sample count of references to valid blocks. 771system.cpu.dcache.tags.avg_refs 26.428571 # Average number of references to valid blocks. |
| 772system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 772system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 773system.cpu.dcache.tags.occ_blocks::cpu.data 216.020896 # Average occupied blocks per requestor 774system.cpu.dcache.tags.occ_percent::cpu.data 0.052739 # Average percentage of cache occupancy 775system.cpu.dcache.tags.occ_percent::total 0.052739 # Average percentage of cache occupancy 776system.cpu.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id 777system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 778system.cpu.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id 779system.cpu.dcache.tags.occ_task_id_percent::1024 0.083496 # Percentage of cache occupancy per task id 780system.cpu.dcache.tags.tag_accesses 10870 # Number of tag accesses 781system.cpu.dcache.tags.data_accesses 10870 # Number of data accesses 782system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 783system.cpu.dcache.ReadReq_hits::cpu.data 3225 # number of ReadReq hits 784system.cpu.dcache.ReadReq_hits::total 3225 # number of ReadReq hits 785system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits 786system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits 787system.cpu.dcache.demand_hits::cpu.data 4237 # number of demand (read+write) hits 788system.cpu.dcache.demand_hits::total 4237 # number of demand (read+write) hits 789system.cpu.dcache.overall_hits::cpu.data 4237 # number of overall hits 790system.cpu.dcache.overall_hits::total 4237 # number of overall hits 791system.cpu.dcache.ReadReq_misses::cpu.data 309 # number of ReadReq misses 792system.cpu.dcache.ReadReq_misses::total 309 # number of ReadReq misses 793system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses 794system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses 795system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses 796system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses 797system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses 798system.cpu.dcache.overall_misses::total 1027 # number of overall misses 799system.cpu.dcache.ReadReq_miss_latency::cpu.data 24016000 # number of ReadReq miss cycles 800system.cpu.dcache.ReadReq_miss_latency::total 24016000 # number of ReadReq miss cycles 801system.cpu.dcache.WriteReq_miss_latency::cpu.data 51330451 # number of WriteReq miss cycles 802system.cpu.dcache.WriteReq_miss_latency::total 51330451 # number of WriteReq miss cycles 803system.cpu.dcache.demand_miss_latency::cpu.data 75346451 # number of demand (read+write) miss cycles 804system.cpu.dcache.demand_miss_latency::total 75346451 # number of demand (read+write) miss cycles 805system.cpu.dcache.overall_miss_latency::cpu.data 75346451 # number of overall miss cycles 806system.cpu.dcache.overall_miss_latency::total 75346451 # number of overall miss cycles 807system.cpu.dcache.ReadReq_accesses::cpu.data 3534 # number of ReadReq accesses(hits+misses) 808system.cpu.dcache.ReadReq_accesses::total 3534 # number of ReadReq accesses(hits+misses) 809system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 810system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) 811system.cpu.dcache.demand_accesses::cpu.data 5264 # number of demand (read+write) accesses 812system.cpu.dcache.demand_accesses::total 5264 # number of demand (read+write) accesses 813system.cpu.dcache.overall_accesses::cpu.data 5264 # number of overall (read+write) accesses 814system.cpu.dcache.overall_accesses::total 5264 # number of overall (read+write) accesses 815system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087436 # miss rate for ReadReq accesses 816system.cpu.dcache.ReadReq_miss_rate::total 0.087436 # miss rate for ReadReq accesses 817system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 818system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 819system.cpu.dcache.demand_miss_rate::cpu.data 0.195099 # miss rate for demand accesses 820system.cpu.dcache.demand_miss_rate::total 0.195099 # miss rate for demand accesses 821system.cpu.dcache.overall_miss_rate::cpu.data 0.195099 # miss rate for overall accesses 822system.cpu.dcache.overall_miss_rate::total 0.195099 # miss rate for overall accesses 823system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77721.682848 # average ReadReq miss latency 824system.cpu.dcache.ReadReq_avg_miss_latency::total 77721.682848 # average ReadReq miss latency 825system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71490.878830 # average WriteReq miss latency 826system.cpu.dcache.WriteReq_avg_miss_latency::total 71490.878830 # average WriteReq miss latency 827system.cpu.dcache.demand_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency 828system.cpu.dcache.demand_avg_miss_latency::total 73365.580331 # average overall miss latency 829system.cpu.dcache.overall_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency 830system.cpu.dcache.overall_avg_miss_latency::total 73365.580331 # average overall miss latency 831system.cpu.dcache.blocked_cycles::no_mshrs 5997 # number of cycles access was blocked 832system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 833system.cpu.dcache.blocked::no_mshrs 108 # number of cycles access was blocked 834system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 835system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.527778 # average number of cycles each access was blocked 836system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 837system.cpu.dcache.ReadReq_mshr_hits::cpu.data 110 # number of ReadReq MSHR hits 838system.cpu.dcache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits 839system.cpu.dcache.WriteReq_mshr_hits::cpu.data 574 # number of WriteReq MSHR hits 840system.cpu.dcache.WriteReq_mshr_hits::total 574 # number of WriteReq MSHR hits 841system.cpu.dcache.demand_mshr_hits::cpu.data 684 # number of demand (read+write) MSHR hits 842system.cpu.dcache.demand_mshr_hits::total 684 # number of demand (read+write) MSHR hits 843system.cpu.dcache.overall_mshr_hits::cpu.data 684 # number of overall MSHR hits 844system.cpu.dcache.overall_mshr_hits::total 684 # number of overall MSHR hits 845system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses 846system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses 847system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses 848system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses 849system.cpu.dcache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses 850system.cpu.dcache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses 851system.cpu.dcache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses 852system.cpu.dcache.overall_mshr_misses::total 343 # number of overall MSHR misses 853system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17847000 # number of ReadReq MSHR miss cycles 854system.cpu.dcache.ReadReq_mshr_miss_latency::total 17847000 # number of ReadReq MSHR miss cycles 855system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12459487 # number of WriteReq MSHR miss cycles 856system.cpu.dcache.WriteReq_mshr_miss_latency::total 12459487 # number of WriteReq MSHR miss cycles 857system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30306487 # number of demand (read+write) MSHR miss cycles 858system.cpu.dcache.demand_mshr_miss_latency::total 30306487 # number of demand (read+write) MSHR miss cycles 859system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30306487 # number of overall MSHR miss cycles 860system.cpu.dcache.overall_mshr_miss_latency::total 30306487 # number of overall MSHR miss cycles 861system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056310 # mshr miss rate for ReadReq accesses 862system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056310 # mshr miss rate for ReadReq accesses 863system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 864system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 865system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for demand accesses 866system.cpu.dcache.demand_mshr_miss_rate::total 0.065160 # mshr miss rate for demand accesses 867system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for overall accesses 868system.cpu.dcache.overall_mshr_miss_rate::total 0.065160 # mshr miss rate for overall accesses 869system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89683.417085 # average ReadReq mshr miss latency 870system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89683.417085 # average ReadReq mshr miss latency 871system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86524.215278 # average WriteReq mshr miss latency 872system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86524.215278 # average WriteReq mshr miss latency 873system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency 874system.cpu.dcache.demand_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency 875system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency 876system.cpu.dcache.overall_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency 877system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 878system.cpu.icache.tags.replacements::0 7 # number of replacements | 773system.cpu.dcache.tags.occ_blocks::cpu.data 108.945725 # Average occupied blocks per requestor 774system.cpu.dcache.tags.occ_percent::cpu.data 0.026598 # Average percentage of cache occupancy 775system.cpu.dcache.tags.occ_percent::total 0.026598 # Average percentage of cache occupancy 776system.cpu.dcache.tags.occ_task_id_blocks::1024 175 # Occupied blocks per task id 777system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 778system.cpu.dcache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id 779system.cpu.dcache.tags.occ_task_id_percent::1024 0.042725 # Percentage of cache occupancy per task id 780system.cpu.dcache.tags.tag_accesses 11523 # Number of tag accesses 781system.cpu.dcache.tags.data_accesses 11523 # Number of data accesses 782system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states 783system.cpu.dcache.ReadReq_hits::cpu.data 3561 # number of ReadReq hits 784system.cpu.dcache.ReadReq_hits::total 3561 # number of ReadReq hits 785system.cpu.dcache.WriteReq_hits::cpu.data 1064 # number of WriteReq hits 786system.cpu.dcache.WriteReq_hits::total 1064 # number of WriteReq hits 787system.cpu.dcache.demand_hits::cpu.data 4625 # number of demand (read+write) hits 788system.cpu.dcache.demand_hits::total 4625 # number of demand (read+write) hits 789system.cpu.dcache.overall_hits::cpu.data 4625 # number of overall hits 790system.cpu.dcache.overall_hits::total 4625 # number of overall hits 791system.cpu.dcache.ReadReq_misses::cpu.data 338 # number of ReadReq misses 792system.cpu.dcache.ReadReq_misses::total 338 # number of ReadReq misses 793system.cpu.dcache.WriteReq_misses::cpu.data 711 # number of WriteReq misses 794system.cpu.dcache.WriteReq_misses::total 711 # number of WriteReq misses 795system.cpu.dcache.demand_misses::cpu.data 1049 # number of demand (read+write) misses 796system.cpu.dcache.demand_misses::total 1049 # number of demand (read+write) misses 797system.cpu.dcache.overall_misses::cpu.data 1049 # number of overall misses 798system.cpu.dcache.overall_misses::total 1049 # number of overall misses 799system.cpu.dcache.ReadReq_miss_latency::cpu.data 29216500 # number of ReadReq miss cycles 800system.cpu.dcache.ReadReq_miss_latency::total 29216500 # number of ReadReq miss cycles 801system.cpu.dcache.WriteReq_miss_latency::cpu.data 54293993 # number of WriteReq miss cycles 802system.cpu.dcache.WriteReq_miss_latency::total 54293993 # number of WriteReq miss cycles 803system.cpu.dcache.demand_miss_latency::cpu.data 83510493 # number of demand (read+write) miss cycles 804system.cpu.dcache.demand_miss_latency::total 83510493 # number of demand (read+write) miss cycles 805system.cpu.dcache.overall_miss_latency::cpu.data 83510493 # number of overall miss cycles 806system.cpu.dcache.overall_miss_latency::total 83510493 # number of overall miss cycles 807system.cpu.dcache.ReadReq_accesses::cpu.data 3899 # number of ReadReq accesses(hits+misses) 808system.cpu.dcache.ReadReq_accesses::total 3899 # number of ReadReq accesses(hits+misses) 809system.cpu.dcache.WriteReq_accesses::cpu.data 1775 # number of WriteReq accesses(hits+misses) 810system.cpu.dcache.WriteReq_accesses::total 1775 # number of WriteReq accesses(hits+misses) 811system.cpu.dcache.demand_accesses::cpu.data 5674 # number of demand (read+write) accesses 812system.cpu.dcache.demand_accesses::total 5674 # number of demand (read+write) accesses 813system.cpu.dcache.overall_accesses::cpu.data 5674 # number of overall (read+write) accesses 814system.cpu.dcache.overall_accesses::total 5674 # number of overall (read+write) accesses 815system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086689 # miss rate for ReadReq accesses 816system.cpu.dcache.ReadReq_miss_rate::total 0.086689 # miss rate for ReadReq accesses 817system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.400563 # miss rate for WriteReq accesses 818system.cpu.dcache.WriteReq_miss_rate::total 0.400563 # miss rate for WriteReq accesses 819system.cpu.dcache.demand_miss_rate::cpu.data 0.184878 # miss rate for demand accesses 820system.cpu.dcache.demand_miss_rate::total 0.184878 # miss rate for demand accesses 821system.cpu.dcache.overall_miss_rate::cpu.data 0.184878 # miss rate for overall accesses 822system.cpu.dcache.overall_miss_rate::total 0.184878 # miss rate for overall accesses 823system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 86439.349112 # average ReadReq miss latency 824system.cpu.dcache.ReadReq_avg_miss_latency::total 86439.349112 # average ReadReq miss latency 825system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 76362.859353 # average WriteReq miss latency 826system.cpu.dcache.WriteReq_avg_miss_latency::total 76362.859353 # average WriteReq miss latency 827system.cpu.dcache.demand_avg_miss_latency::cpu.data 79609.621544 # average overall miss latency 828system.cpu.dcache.demand_avg_miss_latency::total 79609.621544 # average overall miss latency 829system.cpu.dcache.overall_avg_miss_latency::cpu.data 79609.621544 # average overall miss latency 830system.cpu.dcache.overall_avg_miss_latency::total 79609.621544 # average overall miss latency 831system.cpu.dcache.blocked_cycles::no_mshrs 1769 # number of cycles access was blocked 832system.cpu.dcache.blocked_cycles::no_targets 155 # number of cycles access was blocked 833system.cpu.dcache.blocked::no_mshrs 17 # number of cycles access was blocked 834system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked 835system.cpu.dcache.avg_blocked_cycles::no_mshrs 104.058824 # average number of cycles each access was blocked 836system.cpu.dcache.avg_blocked_cycles::no_targets 155 # average number of cycles each access was blocked 837system.cpu.dcache.ReadReq_mshr_hits::cpu.data 236 # number of ReadReq MSHR hits 838system.cpu.dcache.ReadReq_mshr_hits::total 236 # number of ReadReq MSHR hits 839system.cpu.dcache.WriteReq_mshr_hits::cpu.data 638 # number of WriteReq MSHR hits 840system.cpu.dcache.WriteReq_mshr_hits::total 638 # number of WriteReq MSHR hits 841system.cpu.dcache.demand_mshr_hits::cpu.data 874 # number of demand (read+write) MSHR hits 842system.cpu.dcache.demand_mshr_hits::total 874 # number of demand (read+write) MSHR hits 843system.cpu.dcache.overall_mshr_hits::cpu.data 874 # number of overall MSHR hits 844system.cpu.dcache.overall_mshr_hits::total 874 # number of overall MSHR hits 845system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 846system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 847system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses 848system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses 849system.cpu.dcache.demand_mshr_misses::cpu.data 175 # number of demand (read+write) MSHR misses 850system.cpu.dcache.demand_mshr_misses::total 175 # number of demand (read+write) MSHR misses 851system.cpu.dcache.overall_mshr_misses::cpu.data 175 # number of overall MSHR misses 852system.cpu.dcache.overall_mshr_misses::total 175 # number of overall MSHR misses 853system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10272000 # number of ReadReq MSHR miss cycles 854system.cpu.dcache.ReadReq_mshr_miss_latency::total 10272000 # number of ReadReq MSHR miss cycles 855system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6249500 # number of WriteReq MSHR miss cycles 856system.cpu.dcache.WriteReq_mshr_miss_latency::total 6249500 # number of WriteReq MSHR miss cycles 857system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16521500 # number of demand (read+write) MSHR miss cycles 858system.cpu.dcache.demand_mshr_miss_latency::total 16521500 # number of demand (read+write) MSHR miss cycles 859system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16521500 # number of overall MSHR miss cycles 860system.cpu.dcache.overall_mshr_miss_latency::total 16521500 # number of overall MSHR miss cycles 861system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026161 # mshr miss rate for ReadReq accesses 862system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026161 # mshr miss rate for ReadReq accesses 863system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.041127 # mshr miss rate for WriteReq accesses 864system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.041127 # mshr miss rate for WriteReq accesses 865system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.030842 # mshr miss rate for demand accesses 866system.cpu.dcache.demand_mshr_miss_rate::total 0.030842 # mshr miss rate for demand accesses 867system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.030842 # mshr miss rate for overall accesses 868system.cpu.dcache.overall_mshr_miss_rate::total 0.030842 # mshr miss rate for overall accesses 869system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100705.882353 # average ReadReq mshr miss latency 870system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100705.882353 # average ReadReq mshr miss latency 871system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 85609.589041 # average WriteReq mshr miss latency 872system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 85609.589041 # average WriteReq mshr miss latency 873system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94408.571429 # average overall mshr miss latency 874system.cpu.dcache.demand_avg_mshr_miss_latency::total 94408.571429 # average overall mshr miss latency 875system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94408.571429 # average overall mshr miss latency 876system.cpu.dcache.overall_avg_mshr_miss_latency::total 94408.571429 # average overall mshr miss latency 877system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states 878system.cpu.icache.tags.replacements::0 1 # number of replacements |
| 879system.cpu.icache.tags.replacements::1 0 # number of replacements | 879system.cpu.icache.tags.replacements::1 0 # number of replacements |
| 880system.cpu.icache.tags.replacements::total 7 # number of replacements 881system.cpu.icache.tags.tagsinuse 318.054191 # Cycle average of tags in use 882system.cpu.icache.tags.total_refs 2937 # Total number of references to valid blocks. 883system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks. 884system.cpu.icache.tags.avg_refs 4.676752 # Average number of references to valid blocks. | 880system.cpu.icache.tags.replacements::total 1 # number of replacements 881system.cpu.icache.tags.tagsinuse 159.243131 # Cycle average of tags in use 882system.cpu.icache.tags.total_refs 3483 # Total number of references to valid blocks. 883system.cpu.icache.tags.sampled_refs 317 # Sample count of references to valid blocks. 884system.cpu.icache.tags.avg_refs 10.987382 # Average number of references to valid blocks. |
| 885system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 885system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 886system.cpu.icache.tags.occ_blocks::cpu.inst 318.054191 # Average occupied blocks per requestor 887system.cpu.icache.tags.occ_percent::cpu.inst 0.155300 # Average percentage of cache occupancy 888system.cpu.icache.tags.occ_percent::total 0.155300 # Average percentage of cache occupancy 889system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id 890system.cpu.icache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id 891system.cpu.icache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id 892system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id 893system.cpu.icache.tags.tag_accesses 8292 # Number of tag accesses 894system.cpu.icache.tags.data_accesses 8292 # Number of data accesses 895system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 896system.cpu.icache.ReadReq_hits::cpu.inst 2937 # number of ReadReq hits 897system.cpu.icache.ReadReq_hits::total 2937 # number of ReadReq hits 898system.cpu.icache.demand_hits::cpu.inst 2937 # number of demand (read+write) hits 899system.cpu.icache.demand_hits::total 2937 # number of demand (read+write) hits 900system.cpu.icache.overall_hits::cpu.inst 2937 # number of overall hits 901system.cpu.icache.overall_hits::total 2937 # number of overall hits 902system.cpu.icache.ReadReq_misses::cpu.inst 895 # number of ReadReq misses 903system.cpu.icache.ReadReq_misses::total 895 # number of ReadReq misses 904system.cpu.icache.demand_misses::cpu.inst 895 # number of demand (read+write) misses 905system.cpu.icache.demand_misses::total 895 # number of demand (read+write) misses 906system.cpu.icache.overall_misses::cpu.inst 895 # number of overall misses 907system.cpu.icache.overall_misses::total 895 # number of overall misses 908system.cpu.icache.ReadReq_miss_latency::cpu.inst 72804995 # number of ReadReq miss cycles 909system.cpu.icache.ReadReq_miss_latency::total 72804995 # number of ReadReq miss cycles 910system.cpu.icache.demand_miss_latency::cpu.inst 72804995 # number of demand (read+write) miss cycles 911system.cpu.icache.demand_miss_latency::total 72804995 # number of demand (read+write) miss cycles 912system.cpu.icache.overall_miss_latency::cpu.inst 72804995 # number of overall miss cycles 913system.cpu.icache.overall_miss_latency::total 72804995 # number of overall miss cycles 914system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses) 915system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses) 916system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses 917system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses 918system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses 919system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses 920system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233559 # miss rate for ReadReq accesses 921system.cpu.icache.ReadReq_miss_rate::total 0.233559 # miss rate for ReadReq accesses 922system.cpu.icache.demand_miss_rate::cpu.inst 0.233559 # miss rate for demand accesses 923system.cpu.icache.demand_miss_rate::total 0.233559 # miss rate for demand accesses 924system.cpu.icache.overall_miss_rate::cpu.inst 0.233559 # miss rate for overall accesses 925system.cpu.icache.overall_miss_rate::total 0.233559 # miss rate for overall accesses 926system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81346.363128 # average ReadReq miss latency 927system.cpu.icache.ReadReq_avg_miss_latency::total 81346.363128 # average ReadReq miss latency 928system.cpu.icache.demand_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency 929system.cpu.icache.demand_avg_miss_latency::total 81346.363128 # average overall miss latency 930system.cpu.icache.overall_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency 931system.cpu.icache.overall_avg_miss_latency::total 81346.363128 # average overall miss latency 932system.cpu.icache.blocked_cycles::no_mshrs 3504 # number of cycles access was blocked | 886system.cpu.icache.tags.occ_blocks::cpu.inst 159.243131 # Average occupied blocks per requestor 887system.cpu.icache.tags.occ_percent::cpu.inst 0.077755 # Average percentage of cache occupancy 888system.cpu.icache.tags.occ_percent::total 0.077755 # Average percentage of cache occupancy 889system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id 890system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id 891system.cpu.icache.tags.age_task_id_blocks_1024::1 192 # Occupied blocks per task id 892system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id 893system.cpu.icache.tags.tag_accesses 9105 # Number of tag accesses 894system.cpu.icache.tags.data_accesses 9105 # Number of data accesses 895system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states 896system.cpu.icache.ReadReq_hits::cpu.inst 3483 # number of ReadReq hits 897system.cpu.icache.ReadReq_hits::total 3483 # number of ReadReq hits 898system.cpu.icache.demand_hits::cpu.inst 3483 # number of demand (read+write) hits 899system.cpu.icache.demand_hits::total 3483 # number of demand (read+write) hits 900system.cpu.icache.overall_hits::cpu.inst 3483 # number of overall hits 901system.cpu.icache.overall_hits::total 3483 # number of overall hits 902system.cpu.icache.ReadReq_misses::cpu.inst 911 # number of ReadReq misses 903system.cpu.icache.ReadReq_misses::total 911 # number of ReadReq misses 904system.cpu.icache.demand_misses::cpu.inst 911 # number of demand (read+write) misses 905system.cpu.icache.demand_misses::total 911 # number of demand (read+write) misses 906system.cpu.icache.overall_misses::cpu.inst 911 # number of overall misses 907system.cpu.icache.overall_misses::total 911 # number of overall misses 908system.cpu.icache.ReadReq_miss_latency::cpu.inst 73733999 # number of ReadReq miss cycles 909system.cpu.icache.ReadReq_miss_latency::total 73733999 # number of ReadReq miss cycles 910system.cpu.icache.demand_miss_latency::cpu.inst 73733999 # number of demand (read+write) miss cycles 911system.cpu.icache.demand_miss_latency::total 73733999 # number of demand (read+write) miss cycles 912system.cpu.icache.overall_miss_latency::cpu.inst 73733999 # number of overall miss cycles 913system.cpu.icache.overall_miss_latency::total 73733999 # number of overall miss cycles 914system.cpu.icache.ReadReq_accesses::cpu.inst 4394 # number of ReadReq accesses(hits+misses) 915system.cpu.icache.ReadReq_accesses::total 4394 # number of ReadReq accesses(hits+misses) 916system.cpu.icache.demand_accesses::cpu.inst 4394 # number of demand (read+write) accesses 917system.cpu.icache.demand_accesses::total 4394 # number of demand (read+write) accesses 918system.cpu.icache.overall_accesses::cpu.inst 4394 # number of overall (read+write) accesses 919system.cpu.icache.overall_accesses::total 4394 # number of overall (read+write) accesses 920system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.207328 # miss rate for ReadReq accesses 921system.cpu.icache.ReadReq_miss_rate::total 0.207328 # miss rate for ReadReq accesses 922system.cpu.icache.demand_miss_rate::cpu.inst 0.207328 # miss rate for demand accesses 923system.cpu.icache.demand_miss_rate::total 0.207328 # miss rate for demand accesses 924system.cpu.icache.overall_miss_rate::cpu.inst 0.207328 # miss rate for overall accesses 925system.cpu.icache.overall_miss_rate::total 0.207328 # miss rate for overall accesses 926system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80937.430296 # average ReadReq miss latency 927system.cpu.icache.ReadReq_avg_miss_latency::total 80937.430296 # average ReadReq miss latency 928system.cpu.icache.demand_avg_miss_latency::cpu.inst 80937.430296 # average overall miss latency 929system.cpu.icache.demand_avg_miss_latency::total 80937.430296 # average overall miss latency 930system.cpu.icache.overall_avg_miss_latency::cpu.inst 80937.430296 # average overall miss latency 931system.cpu.icache.overall_avg_miss_latency::total 80937.430296 # average overall miss latency 932system.cpu.icache.blocked_cycles::no_mshrs 136 # number of cycles access was blocked |
| 933system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 933system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 934system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked | 934system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked |
| 935system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 935system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 936system.cpu.icache.avg_blocked_cycles::no_mshrs 60.413793 # average number of cycles each access was blocked | 936system.cpu.icache.avg_blocked_cycles::no_mshrs 136 # average number of cycles each access was blocked |
| 937system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 937system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 938system.cpu.icache.writebacks::writebacks 7 # number of writebacks 939system.cpu.icache.writebacks::total 7 # number of writebacks 940system.cpu.icache.ReadReq_mshr_hits::cpu.inst 267 # number of ReadReq MSHR hits 941system.cpu.icache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits 942system.cpu.icache.demand_mshr_hits::cpu.inst 267 # number of demand (read+write) MSHR hits 943system.cpu.icache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits 944system.cpu.icache.overall_mshr_hits::cpu.inst 267 # number of overall MSHR hits 945system.cpu.icache.overall_mshr_hits::total 267 # number of overall MSHR hits 946system.cpu.icache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses 947system.cpu.icache.ReadReq_mshr_misses::total 628 # number of ReadReq MSHR misses 948system.cpu.icache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses 949system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses 950system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses 951system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses 952system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54756996 # number of ReadReq MSHR miss cycles 953system.cpu.icache.ReadReq_mshr_miss_latency::total 54756996 # number of ReadReq MSHR miss cycles 954system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54756996 # number of demand (read+write) MSHR miss cycles 955system.cpu.icache.demand_mshr_miss_latency::total 54756996 # number of demand (read+write) MSHR miss cycles 956system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54756996 # number of overall MSHR miss cycles 957system.cpu.icache.overall_mshr_miss_latency::total 54756996 # number of overall MSHR miss cycles 958system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for ReadReq accesses 959system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163883 # mshr miss rate for ReadReq accesses 960system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for demand accesses 961system.cpu.icache.demand_mshr_miss_rate::total 0.163883 # mshr miss rate for demand accesses 962system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for overall accesses 963system.cpu.icache.overall_mshr_miss_rate::total 0.163883 # mshr miss rate for overall accesses 964system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87192.668790 # average ReadReq mshr miss latency 965system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87192.668790 # average ReadReq mshr miss latency 966system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency 967system.cpu.icache.demand_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency 968system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency 969system.cpu.icache.overall_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency 970system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states | 938system.cpu.icache.writebacks::writebacks 1 # number of writebacks 939system.cpu.icache.writebacks::total 1 # number of writebacks 940system.cpu.icache.ReadReq_mshr_hits::cpu.inst 594 # number of ReadReq MSHR hits 941system.cpu.icache.ReadReq_mshr_hits::total 594 # number of ReadReq MSHR hits 942system.cpu.icache.demand_mshr_hits::cpu.inst 594 # number of demand (read+write) MSHR hits 943system.cpu.icache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits 944system.cpu.icache.overall_mshr_hits::cpu.inst 594 # number of overall MSHR hits 945system.cpu.icache.overall_mshr_hits::total 594 # number of overall MSHR hits 946system.cpu.icache.ReadReq_mshr_misses::cpu.inst 317 # number of ReadReq MSHR misses 947system.cpu.icache.ReadReq_mshr_misses::total 317 # number of ReadReq MSHR misses 948system.cpu.icache.demand_mshr_misses::cpu.inst 317 # number of demand (read+write) MSHR misses 949system.cpu.icache.demand_mshr_misses::total 317 # number of demand (read+write) MSHR misses 950system.cpu.icache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses 951system.cpu.icache.overall_mshr_misses::total 317 # number of overall MSHR misses 952system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27574500 # number of ReadReq MSHR miss cycles 953system.cpu.icache.ReadReq_mshr_miss_latency::total 27574500 # number of ReadReq MSHR miss cycles 954system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27574500 # number of demand (read+write) MSHR miss cycles 955system.cpu.icache.demand_mshr_miss_latency::total 27574500 # number of demand (read+write) MSHR miss cycles 956system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27574500 # number of overall MSHR miss cycles 957system.cpu.icache.overall_mshr_miss_latency::total 27574500 # number of overall MSHR miss cycles 958system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.072144 # mshr miss rate for ReadReq accesses 959system.cpu.icache.ReadReq_mshr_miss_rate::total 0.072144 # mshr miss rate for ReadReq accesses 960system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.072144 # mshr miss rate for demand accesses 961system.cpu.icache.demand_mshr_miss_rate::total 0.072144 # mshr miss rate for demand accesses 962system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.072144 # mshr miss rate for overall accesses 963system.cpu.icache.overall_mshr_miss_rate::total 0.072144 # mshr miss rate for overall accesses 964system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 86985.804416 # average ReadReq mshr miss latency 965system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 86985.804416 # average ReadReq mshr miss latency 966system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 86985.804416 # average overall mshr miss latency 967system.cpu.icache.demand_avg_mshr_miss_latency::total 86985.804416 # average overall mshr miss latency 968system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 86985.804416 # average overall mshr miss latency 969system.cpu.icache.overall_avg_mshr_miss_latency::total 86985.804416 # average overall mshr miss latency 970system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states |
| 971system.cpu.l2cache.tags.replacements::0 0 # number of replacements 972system.cpu.l2cache.tags.replacements::1 0 # number of replacements 973system.cpu.l2cache.tags.replacements::total 0 # number of replacements | 971system.cpu.l2cache.tags.replacements::0 0 # number of replacements 972system.cpu.l2cache.tags.replacements::1 0 # number of replacements 973system.cpu.l2cache.tags.replacements::total 0 # number of replacements |
| 974system.cpu.l2cache.tags.tagsinuse 534.673891 # Cycle average of tags in use 975system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. 976system.cpu.l2cache.tags.sampled_refs 967 # Sample count of references to valid blocks. 977system.cpu.l2cache.tags.avg_refs 0.010341 # Average number of references to valid blocks. | 974system.cpu.l2cache.tags.tagsinuse 268.537778 # Cycle average of tags in use 975system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 976system.cpu.l2cache.tags.sampled_refs 492 # Sample count of references to valid blocks. 977system.cpu.l2cache.tags.avg_refs 0.002033 # Average number of references to valid blocks. |
| 978system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 978system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 979system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.518306 # Average occupied blocks per requestor 980system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155585 # Average occupied blocks per requestor 981system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009720 # Average percentage of cache occupancy 982system.cpu.l2cache.tags.occ_percent::cpu.data 0.006597 # Average percentage of cache occupancy 983system.cpu.l2cache.tags.occ_percent::total 0.016317 # Average percentage of cache occupancy 984system.cpu.l2cache.tags.occ_task_id_blocks::1024 967 # Occupied blocks per task id 985system.cpu.l2cache.tags.age_task_id_blocks_1024::0 306 # Occupied blocks per task id 986system.cpu.l2cache.tags.age_task_id_blocks_1024::1 661 # Occupied blocks per task id 987system.cpu.l2cache.tags.occ_task_id_percent::1024 0.029510 # Percentage of cache occupancy per task id 988system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses 989system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses 990system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 991system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits 992system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits 993system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 994system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 995system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 996system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 997system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 998system.cpu.l2cache.overall_hits::total 3 # number of overall hits 999system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses 1000system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses 1001system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 625 # number of ReadCleanReq misses 1002system.cpu.l2cache.ReadCleanReq_misses::total 625 # number of ReadCleanReq misses 1003system.cpu.l2cache.ReadSharedReq_misses::cpu.data 198 # number of ReadSharedReq misses 1004system.cpu.l2cache.ReadSharedReq_misses::total 198 # number of ReadSharedReq misses 1005system.cpu.l2cache.demand_misses::cpu.inst 625 # number of demand (read+write) misses 1006system.cpu.l2cache.demand_misses::cpu.data 343 # number of demand (read+write) misses 1007system.cpu.l2cache.demand_misses::total 968 # number of demand (read+write) misses 1008system.cpu.l2cache.overall_misses::cpu.inst 625 # number of overall misses 1009system.cpu.l2cache.overall_misses::cpu.data 343 # number of overall misses 1010system.cpu.l2cache.overall_misses::total 968 # number of overall misses 1011system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12308500 # number of ReadExReq miss cycles 1012system.cpu.l2cache.ReadExReq_miss_latency::total 12308500 # number of ReadExReq miss cycles 1013system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53777000 # number of ReadCleanReq miss cycles 1014system.cpu.l2cache.ReadCleanReq_miss_latency::total 53777000 # number of ReadCleanReq miss cycles 1015system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17466000 # number of ReadSharedReq miss cycles 1016system.cpu.l2cache.ReadSharedReq_miss_latency::total 17466000 # number of ReadSharedReq miss cycles 1017system.cpu.l2cache.demand_miss_latency::cpu.inst 53777000 # number of demand (read+write) miss cycles 1018system.cpu.l2cache.demand_miss_latency::cpu.data 29774500 # number of demand (read+write) miss cycles 1019system.cpu.l2cache.demand_miss_latency::total 83551500 # number of demand (read+write) miss cycles 1020system.cpu.l2cache.overall_miss_latency::cpu.inst 53777000 # number of overall miss cycles 1021system.cpu.l2cache.overall_miss_latency::cpu.data 29774500 # number of overall miss cycles 1022system.cpu.l2cache.overall_miss_latency::total 83551500 # number of overall miss cycles 1023system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) 1024system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) 1025system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses) 1026system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses) 1027system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 628 # number of ReadCleanReq accesses(hits+misses) 1028system.cpu.l2cache.ReadCleanReq_accesses::total 628 # number of ReadCleanReq accesses(hits+misses) 1029system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 198 # number of ReadSharedReq accesses(hits+misses) 1030system.cpu.l2cache.ReadSharedReq_accesses::total 198 # number of ReadSharedReq accesses(hits+misses) 1031system.cpu.l2cache.demand_accesses::cpu.inst 628 # number of demand (read+write) accesses 1032system.cpu.l2cache.demand_accesses::cpu.data 343 # number of demand (read+write) accesses 1033system.cpu.l2cache.demand_accesses::total 971 # number of demand (read+write) accesses 1034system.cpu.l2cache.overall_accesses::cpu.inst 628 # number of overall (read+write) accesses 1035system.cpu.l2cache.overall_accesses::cpu.data 343 # number of overall (read+write) accesses 1036system.cpu.l2cache.overall_accesses::total 971 # number of overall (read+write) accesses | 979system.cpu.l2cache.tags.occ_blocks::cpu.inst 159.520172 # Average occupied blocks per requestor 980system.cpu.l2cache.tags.occ_blocks::cpu.data 109.017606 # Average occupied blocks per requestor 981system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004868 # Average percentage of cache occupancy 982system.cpu.l2cache.tags.occ_percent::cpu.data 0.003327 # Average percentage of cache occupancy 983system.cpu.l2cache.tags.occ_percent::total 0.008195 # Average percentage of cache occupancy 984system.cpu.l2cache.tags.occ_task_id_blocks::1024 492 # Occupied blocks per task id 985system.cpu.l2cache.tags.age_task_id_blocks_1024::0 165 # Occupied blocks per task id 986system.cpu.l2cache.tags.age_task_id_blocks_1024::1 327 # Occupied blocks per task id 987system.cpu.l2cache.tags.occ_task_id_percent::1024 0.015015 # Percentage of cache occupancy per task id 988system.cpu.l2cache.tags.tag_accesses 4436 # Number of tag accesses 989system.cpu.l2cache.tags.data_accesses 4436 # Number of data accesses 990system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states 991system.cpu.l2cache.WritebackClean_hits::writebacks 1 # number of WritebackClean hits 992system.cpu.l2cache.WritebackClean_hits::total 1 # number of WritebackClean hits 993system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses 994system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses 995system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 317 # number of ReadCleanReq misses 996system.cpu.l2cache.ReadCleanReq_misses::total 317 # number of ReadCleanReq misses 997system.cpu.l2cache.ReadSharedReq_misses::cpu.data 102 # number of ReadSharedReq misses 998system.cpu.l2cache.ReadSharedReq_misses::total 102 # number of ReadSharedReq misses 999system.cpu.l2cache.demand_misses::cpu.inst 317 # number of demand (read+write) misses 1000system.cpu.l2cache.demand_misses::cpu.data 175 # number of demand (read+write) misses 1001system.cpu.l2cache.demand_misses::total 492 # number of demand (read+write) misses 1002system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses 1003system.cpu.l2cache.overall_misses::cpu.data 175 # number of overall misses 1004system.cpu.l2cache.overall_misses::total 492 # number of overall misses 1005system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6138000 # number of ReadExReq miss cycles 1006system.cpu.l2cache.ReadExReq_miss_latency::total 6138000 # number of ReadExReq miss cycles 1007system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27097500 # number of ReadCleanReq miss cycles 1008system.cpu.l2cache.ReadCleanReq_miss_latency::total 27097500 # number of ReadCleanReq miss cycles 1009system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 10111000 # number of ReadSharedReq miss cycles 1010system.cpu.l2cache.ReadSharedReq_miss_latency::total 10111000 # number of ReadSharedReq miss cycles 1011system.cpu.l2cache.demand_miss_latency::cpu.inst 27097500 # number of demand (read+write) miss cycles 1012system.cpu.l2cache.demand_miss_latency::cpu.data 16249000 # number of demand (read+write) miss cycles 1013system.cpu.l2cache.demand_miss_latency::total 43346500 # number of demand (read+write) miss cycles 1014system.cpu.l2cache.overall_miss_latency::cpu.inst 27097500 # number of overall miss cycles 1015system.cpu.l2cache.overall_miss_latency::cpu.data 16249000 # number of overall miss cycles 1016system.cpu.l2cache.overall_miss_latency::total 43346500 # number of overall miss cycles 1017system.cpu.l2cache.WritebackClean_accesses::writebacks 1 # number of WritebackClean accesses(hits+misses) 1018system.cpu.l2cache.WritebackClean_accesses::total 1 # number of WritebackClean accesses(hits+misses) 1019system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) 1020system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) 1021system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 317 # number of ReadCleanReq accesses(hits+misses) 1022system.cpu.l2cache.ReadCleanReq_accesses::total 317 # number of ReadCleanReq accesses(hits+misses) 1023system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 102 # number of ReadSharedReq accesses(hits+misses) 1024system.cpu.l2cache.ReadSharedReq_accesses::total 102 # number of ReadSharedReq accesses(hits+misses) 1025system.cpu.l2cache.demand_accesses::cpu.inst 317 # number of demand (read+write) accesses 1026system.cpu.l2cache.demand_accesses::cpu.data 175 # number of demand (read+write) accesses 1027system.cpu.l2cache.demand_accesses::total 492 # number of demand (read+write) accesses 1028system.cpu.l2cache.overall_accesses::cpu.inst 317 # number of overall (read+write) accesses 1029system.cpu.l2cache.overall_accesses::cpu.data 175 # number of overall (read+write) accesses 1030system.cpu.l2cache.overall_accesses::total 492 # number of overall (read+write) accesses |
| 1037system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 1038system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 1031system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 1032system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 1039system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995223 # miss rate for ReadCleanReq accesses 1040system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995223 # miss rate for ReadCleanReq accesses | 1033system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 1 # miss rate for ReadCleanReq accesses 1034system.cpu.l2cache.ReadCleanReq_miss_rate::total 1 # miss rate for ReadCleanReq accesses |
| 1041system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 1042system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses | 1035system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 1036system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses |
| 1043system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995223 # miss rate for demand accesses | 1037system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses |
| 1044system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 1038system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 1045system.cpu.l2cache.demand_miss_rate::total 0.996910 # miss rate for demand accesses 1046system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995223 # miss rate for overall accesses | 1039system.cpu.l2cache.demand_miss_rate::total 1 # miss rate for demand accesses 1040system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses |
| 1047system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 1041system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 1048system.cpu.l2cache.overall_miss_rate::total 0.996910 # miss rate for overall accesses 1049system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84886.206897 # average ReadExReq miss latency 1050system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84886.206897 # average ReadExReq miss latency 1051system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86043.200000 # average ReadCleanReq miss latency 1052system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86043.200000 # average ReadCleanReq miss latency 1053system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88212.121212 # average ReadSharedReq miss latency 1054system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88212.121212 # average ReadSharedReq miss latency 1055system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency 1056system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency 1057system.cpu.l2cache.demand_avg_miss_latency::total 86313.533058 # average overall miss latency 1058system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency 1059system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency 1060system.cpu.l2cache.overall_avg_miss_latency::total 86313.533058 # average overall miss latency | 1042system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses 1043system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84082.191781 # average ReadExReq miss latency 1044system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84082.191781 # average ReadExReq miss latency 1045system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 85481.072555 # average ReadCleanReq miss latency 1046system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 85481.072555 # average ReadCleanReq miss latency 1047system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 99127.450980 # average ReadSharedReq miss latency 1048system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 99127.450980 # average ReadSharedReq miss latency 1049system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 85481.072555 # average overall miss latency 1050system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92851.428571 # average overall miss latency 1051system.cpu.l2cache.demand_avg_miss_latency::total 88102.642276 # average overall miss latency 1052system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 85481.072555 # average overall miss latency 1053system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92851.428571 # average overall miss latency 1054system.cpu.l2cache.overall_avg_miss_latency::total 88102.642276 # average overall miss latency |
| 1061system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1062system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1063system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1064system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1065system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1066system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1055system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1056system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1057system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1058system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1059system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1060system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1067system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses 1068system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses 1069system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 625 # number of ReadCleanReq MSHR misses 1070system.cpu.l2cache.ReadCleanReq_mshr_misses::total 625 # number of ReadCleanReq MSHR misses 1071system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses 1072system.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses 1073system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses 1074system.cpu.l2cache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses 1075system.cpu.l2cache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses 1076system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses 1077system.cpu.l2cache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses 1078system.cpu.l2cache.overall_mshr_misses::total 968 # number of overall MSHR misses 1079system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10858500 # number of ReadExReq MSHR miss cycles 1080system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10858500 # number of ReadExReq MSHR miss cycles 1081system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47527000 # number of ReadCleanReq MSHR miss cycles 1082system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47527000 # number of ReadCleanReq MSHR miss cycles 1083system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15496000 # number of ReadSharedReq MSHR miss cycles 1084system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15496000 # number of ReadSharedReq MSHR miss cycles 1085system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47527000 # number of demand (read+write) MSHR miss cycles 1086system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26354500 # number of demand (read+write) MSHR miss cycles 1087system.cpu.l2cache.demand_mshr_miss_latency::total 73881500 # number of demand (read+write) MSHR miss cycles 1088system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47527000 # number of overall MSHR miss cycles 1089system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26354500 # number of overall MSHR miss cycles 1090system.cpu.l2cache.overall_mshr_miss_latency::total 73881500 # number of overall MSHR miss cycles | 1061system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses 1062system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses 1063system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 317 # number of ReadCleanReq MSHR misses 1064system.cpu.l2cache.ReadCleanReq_mshr_misses::total 317 # number of ReadCleanReq MSHR misses 1065system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 102 # number of ReadSharedReq MSHR misses 1066system.cpu.l2cache.ReadSharedReq_mshr_misses::total 102 # number of ReadSharedReq MSHR misses 1067system.cpu.l2cache.demand_mshr_misses::cpu.inst 317 # number of demand (read+write) MSHR misses 1068system.cpu.l2cache.demand_mshr_misses::cpu.data 175 # number of demand (read+write) MSHR misses 1069system.cpu.l2cache.demand_mshr_misses::total 492 # number of demand (read+write) MSHR misses 1070system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses 1071system.cpu.l2cache.overall_mshr_misses::cpu.data 175 # number of overall MSHR misses 1072system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses 1073system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5408000 # number of ReadExReq MSHR miss cycles 1074system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5408000 # number of ReadExReq MSHR miss cycles 1075system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23927500 # number of ReadCleanReq MSHR miss cycles 1076system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23927500 # number of ReadCleanReq MSHR miss cycles 1077system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9091000 # number of ReadSharedReq MSHR miss cycles 1078system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9091000 # number of ReadSharedReq MSHR miss cycles 1079system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23927500 # number of demand (read+write) MSHR miss cycles 1080system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14499000 # number of demand (read+write) MSHR miss cycles 1081system.cpu.l2cache.demand_mshr_miss_latency::total 38426500 # number of demand (read+write) MSHR miss cycles 1082system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23927500 # number of overall MSHR miss cycles 1083system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14499000 # number of overall MSHR miss cycles 1084system.cpu.l2cache.overall_mshr_miss_latency::total 38426500 # number of overall MSHR miss cycles |
| 1091system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1092system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 1085system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1086system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 1093system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for ReadCleanReq accesses 1094system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995223 # mshr miss rate for ReadCleanReq accesses | 1087system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses 1088system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses |
| 1095system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 1096system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses | 1089system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 1090system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses |
| 1097system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for demand accesses | 1091system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses |
| 1098system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 1092system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 1099system.cpu.l2cache.demand_mshr_miss_rate::total 0.996910 # mshr miss rate for demand accesses 1100system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for overall accesses | 1093system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses 1094system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses |
| 1101system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 1095system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 1102system.cpu.l2cache.overall_mshr_miss_rate::total 0.996910 # mshr miss rate for overall accesses 1103system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74886.206897 # average ReadExReq mshr miss latency 1104system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74886.206897 # average ReadExReq mshr miss latency 1105system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76043.200000 # average ReadCleanReq mshr miss latency 1106system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76043.200000 # average ReadCleanReq mshr miss latency 1107system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78262.626263 # average ReadSharedReq mshr miss latency 1108system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78262.626263 # average ReadSharedReq mshr miss latency 1109system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency 1110system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency 1111system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency 1112system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency 1113system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency 1114system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency 1115system.cpu.toL2Bus.snoop_filter.tot_requests 978 # Total number of requests made to the snoop filter. 1116system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1096system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses 1097system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74082.191781 # average ReadExReq mshr miss latency 1098system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74082.191781 # average ReadExReq mshr miss latency 1099system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75481.072555 # average ReadCleanReq mshr miss latency 1100system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75481.072555 # average ReadCleanReq mshr miss latency 1101system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89127.450980 # average ReadSharedReq mshr miss latency 1102system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89127.450980 # average ReadSharedReq mshr miss latency 1103system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75481.072555 # average overall mshr miss latency 1104system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82851.428571 # average overall mshr miss latency 1105system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78102.642276 # average overall mshr miss latency 1106system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75481.072555 # average overall mshr miss latency 1107system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82851.428571 # average overall mshr miss latency 1108system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78102.642276 # average overall mshr miss latency 1109system.cpu.toL2Bus.snoop_filter.tot_requests 493 # Total number of requests made to the snoop filter. 1110system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 1117system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1118system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1119system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1120system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1111system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1112system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1113system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1114system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1121system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 1122system.cpu.toL2Bus.trans_dist::ReadResp 825 # Transaction distribution 1123system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution 1124system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution 1125system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution 1126system.cpu.toL2Bus.trans_dist::ReadCleanReq 628 # Transaction distribution 1127system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution 1128system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1263 # Packet count per connected master and slave (bytes) 1129system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 685 # Packet count per connected master and slave (bytes) 1130system.cpu.toL2Bus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) 1131system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40640 # Cumulative packet size per connected master and slave (bytes) 1132system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21888 # Cumulative packet size per connected master and slave (bytes) 1133system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) | 1115system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states 1116system.cpu.toL2Bus.trans_dist::ReadResp 419 # Transaction distribution 1117system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 1118system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution 1119system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::ReadCleanReq 317 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::ReadSharedReq 102 # Transaction distribution 1122system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 635 # Packet count per connected master and slave (bytes) 1123system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350 # Packet count per connected master and slave (bytes) 1124system.cpu.toL2Bus.pkt_count::total 985 # Packet count per connected master and slave (bytes) 1125system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20352 # Cumulative packet size per connected master and slave (bytes) 1126system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes) 1127system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes) |
| 1134system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1135system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) | 1128system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1129system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1136system.cpu.toL2Bus.snoop_fanout::samples 971 # Request fanout histogram 1137system.cpu.toL2Bus.snoop_fanout::mean 0.002060 # Request fanout histogram 1138system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram | 1130system.cpu.toL2Bus.snoop_fanout::samples 492 # Request fanout histogram 1131system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram 1132system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram |
| 1139system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1133system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1140system.cpu.toL2Bus.snoop_fanout::0 969 99.79% 99.79% # Request fanout histogram 1141system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram | 1134system.cpu.toL2Bus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram 1135system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram |
| 1142system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1143system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1144system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram | 1136system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1137system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1138system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 1145system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 1146system.cpu.toL2Bus.snoop_fanout::total 971 # Request fanout histogram 1147system.cpu.toL2Bus.reqLayer0.occupancy 496000 # Layer occupancy (ticks) 1148system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) 1149system.cpu.toL2Bus.respLayer0.occupancy 942000 # Layer occupancy (ticks) 1150system.cpu.toL2Bus.respLayer0.utilization 3.5 # Layer utilization (%) 1151system.cpu.toL2Bus.respLayer1.occupancy 513000 # Layer occupancy (ticks) 1152system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) 1153system.membus.snoop_filter.tot_requests 968 # Total number of requests made to the snoop filter. | 1139system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 1140system.cpu.toL2Bus.snoop_fanout::total 492 # Request fanout histogram 1141system.cpu.toL2Bus.reqLayer0.occupancy 247500 # Layer occupancy (ticks) 1142system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 1143system.cpu.toL2Bus.respLayer0.occupancy 475500 # Layer occupancy (ticks) 1144system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%) 1145system.cpu.toL2Bus.respLayer1.occupancy 262500 # Layer occupancy (ticks) 1146system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 1147system.membus.snoop_filter.tot_requests 492 # Total number of requests made to the snoop filter. |
| 1154system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1155system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1156system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1157system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1158system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1148system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1149system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1150system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1151system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1152system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1159system.membus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 1160system.membus.trans_dist::ReadResp 822 # Transaction distribution 1161system.membus.trans_dist::ReadExReq 145 # Transaction distribution 1162system.membus.trans_dist::ReadExResp 145 # Transaction distribution 1163system.membus.trans_dist::ReadSharedReq 823 # Transaction distribution 1164system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1935 # Packet count per connected master and slave (bytes) 1165system.membus.pkt_count::total 1935 # Packet count per connected master and slave (bytes) 1166system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61888 # Cumulative packet size per connected master and slave (bytes) 1167system.membus.pkt_size::total 61888 # Cumulative packet size per connected master and slave (bytes) | 1153system.membus.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states 1154system.membus.trans_dist::ReadResp 419 # Transaction distribution 1155system.membus.trans_dist::ReadExReq 73 # Transaction distribution 1156system.membus.trans_dist::ReadExResp 73 # Transaction distribution 1157system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution 1158system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 984 # Packet count per connected master and slave (bytes) 1159system.membus.pkt_count::total 984 # Packet count per connected master and slave (bytes) 1160system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31488 # Cumulative packet size per connected master and slave (bytes) 1161system.membus.pkt_size::total 31488 # Cumulative packet size per connected master and slave (bytes) |
| 1168system.membus.snoops 0 # Total snoops (count) 1169system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1162system.membus.snoops 0 # Total snoops (count) 1163system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1170system.membus.snoop_fanout::samples 968 # Request fanout histogram | 1164system.membus.snoop_fanout::samples 492 # Request fanout histogram |
| 1171system.membus.snoop_fanout::mean 0 # Request fanout histogram 1172system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1173system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1165system.membus.snoop_fanout::mean 0 # Request fanout histogram 1166system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1167system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1174system.membus.snoop_fanout::0 968 100.00% 100.00% # Request fanout histogram | 1168system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram |
| 1175system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1176system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1177system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1178system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1169system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1170system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1171system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1172system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1179system.membus.snoop_fanout::total 968 # Request fanout histogram 1180system.membus.reqLayer0.occupancy 1179500 # Layer occupancy (ticks) 1181system.membus.reqLayer0.utilization 4.4 # Layer utilization (%) 1182system.membus.respLayer1.occupancy 5127250 # Layer occupancy (ticks) 1183system.membus.respLayer1.utilization 19.2 # Layer utilization (%) | 1173system.membus.snoop_fanout::total 492 # Request fanout histogram 1174system.membus.reqLayer0.occupancy 588500 # Layer occupancy (ticks) 1175system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) 1176system.membus.respLayer1.occupancy 2626750 # Layer occupancy (ticks) 1177system.membus.respLayer1.utilization 10.3 # Layer utilization (%) |
| 1184 1185---------- End Simulation Statistics ---------- | 1178 1179---------- End Simulation Statistics ---------- |