| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25607000 # Number of ticks simulated 5final_tick 25607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000027 # Number of seconds simulated 4sim_ticks 26661500 # Number of ticks simulated 5final_tick 26661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 110915 # Simulator instruction rate (inst/s) 8host_op_rate 110902 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 222369986 # Simulator tick rate (ticks/s) 10host_mem_usage 254744 # Number of bytes of host memory used 11host_seconds 0.12 # Real time elapsed on the host | 7host_inst_rate 67147 # Simulator instruction rate (inst/s) 8host_op_rate 67138 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 140157650 # Simulator tick rate (ticks/s) 10host_mem_usage 253164 # Number of bytes of host memory used 11host_seconds 0.19 # Real time elapsed on the host |
| 12sim_insts 12770 # Number of instructions simulated 13sim_ops 12770 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 12770 # Number of instructions simulated 13sim_ops 12770 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 21824 # Number of bytes read from this memory 19system.physmem.bytes_read::total 61760 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 341 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 965 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 1559573554 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 852266958 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 2411840512 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 1559573554 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 1559573554 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 1559573554 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 852266958 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 2411840512 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 966 # Number of read requests accepted | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 21888 # Number of bytes read from this memory 19system.physmem.bytes_read::total 61888 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 342 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 967 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 1500290681 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 820959061 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 2321249742 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 1500290681 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 1500290681 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 1500290681 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 820959061 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 2321249742 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.readReqs 968 # Number of read requests accepted |
| 34system.physmem.writeReqs 0 # Number of write requests accepted | 34system.physmem.writeReqs 0 # Number of write requests accepted |
| 35system.physmem.readBursts 966 # Number of DRAM read bursts, including those serviced by the write queue | 35system.physmem.readBursts 968 # Number of DRAM read bursts, including those serviced by the write queue |
| 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 37system.physmem.bytesReadDRAM 61824 # Total number of bytes read from DRAM | 37system.physmem.bytesReadDRAM 61952 # Total number of bytes read from DRAM |
| 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 40system.physmem.bytesReadSys 61824 # Total read bytes from the system interface side | 40system.physmem.bytesReadSys 61952 # Total read bytes from the system interface side |
| 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 84 # Per bank write bursts 46system.physmem.perBankRdBursts::1 150 # Per bank write bursts 47system.physmem.perBankRdBursts::2 77 # Per bank write bursts 48system.physmem.perBankRdBursts::3 58 # Per bank write bursts 49system.physmem.perBankRdBursts::4 90 # Per bank write bursts | 41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 45system.physmem.perBankRdBursts::0 84 # Per bank write bursts 46system.physmem.perBankRdBursts::1 150 # Per bank write bursts 47system.physmem.perBankRdBursts::2 77 # Per bank write bursts 48system.physmem.perBankRdBursts::3 58 # Per bank write bursts 49system.physmem.perBankRdBursts::4 90 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::5 46 # Per bank write bursts 51system.physmem.perBankRdBursts::6 32 # Per bank write bursts | 50system.physmem.perBankRdBursts::5 45 # Per bank write bursts 51system.physmem.perBankRdBursts::6 33 # Per bank write bursts |
| 52system.physmem.perBankRdBursts::7 50 # Per bank write bursts | 52system.physmem.perBankRdBursts::7 50 # Per bank write bursts |
| 53system.physmem.perBankRdBursts::8 41 # Per bank write bursts 54system.physmem.perBankRdBursts::9 37 # Per bank write bursts | 53system.physmem.perBankRdBursts::8 42 # Per bank write bursts 54system.physmem.perBankRdBursts::9 38 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::10 28 # Per bank write bursts 56system.physmem.perBankRdBursts::11 34 # Per bank write bursts 57system.physmem.perBankRdBursts::12 15 # Per bank write bursts 58system.physmem.perBankRdBursts::13 120 # Per bank write bursts 59system.physmem.perBankRdBursts::14 67 # Per bank write bursts 60system.physmem.perBankRdBursts::15 37 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts --- 8 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 55system.physmem.perBankRdBursts::10 28 # Per bank write bursts 56system.physmem.perBankRdBursts::11 34 # Per bank write bursts 57system.physmem.perBankRdBursts::12 15 # Per bank write bursts 58system.physmem.perBankRdBursts::13 120 # Per bank write bursts 59system.physmem.perBankRdBursts::14 67 # Per bank write bursts 60system.physmem.perBankRdBursts::15 37 # Per bank write bursts 61system.physmem.perBankWrBursts::0 0 # Per bank write bursts 62system.physmem.perBankWrBursts::1 0 # Per bank write bursts --- 8 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 25577000 # Total gap between requests | 79system.physmem.totGap 26630500 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 86system.physmem.readPktSize::6 966 # Read request sizes (log2) | 86system.physmem.readPktSize::6 968 # Read request sizes (log2) |
| 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) | 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 94system.physmem.rdQLenPdf::0 351 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 323 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 171 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 89 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 23 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::0 332 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 313 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 185 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::3 94 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see | 99system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see | 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see |
| 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see --- 72 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see --- 72 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 278.748815 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 172.887192 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 291.495109 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 76 36.02% 36.02% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 57 27.01% 63.03% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 23 10.90% 73.93% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 12 5.69% 79.62% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 8 3.79% 83.41% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 11 5.21% 88.63% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 6 2.84% 91.47% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 6 2.84% 94.31% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 12 5.69% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation 204system.physmem.totQLat 14120500 # Total ticks spent queuing 205system.physmem.totMemAccLat 32233000 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 4830000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 14617.49 # Average queueing delay per DRAM burst | 190system.physmem.bytesPerActivate::samples 202 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 289.584158 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 180.299588 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 295.891915 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 69 34.16% 34.16% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 55 27.23% 61.39% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 20 9.90% 71.29% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 16 7.92% 79.21% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 9 4.46% 83.66% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 7 3.47% 87.13% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 9 4.46% 91.58% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 1.49% 93.07% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 14 6.93% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 202 # Bytes accessed per row activation 204system.physmem.totQLat 15942250 # Total ticks spent queuing 205system.physmem.totMemAccLat 34092250 # Total ticks spent from burst creation until serviced by the DRAM 206system.physmem.totBusLat 4840000 # Total ticks spent in databus transfers 207system.physmem.avgQLat 16469.27 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 33367.49 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 2414.34 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 35219.27 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 2323.65 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 2414.34 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 2323.65 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 18.86 # Data bus utilization in percentage 216system.physmem.busUtilRead 18.86 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 18.15 # Data bus utilization in percentage 216system.physmem.busUtilRead 18.15 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 220system.physmem.readRowHits 745 # Number of row buffer hits during reads | 220system.physmem.readRowHits 755 # Number of row buffer hits during reads |
| 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 222system.physmem.readRowHitRate 77.12 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 78.00 # Row buffer hit rate for reads |
| 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 26477.23 # Average gap between requests 225system.physmem.pageHitRate 77.12 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 861840 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 470250 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 4477200 # Energy for read commands per rank (pJ) | 224system.physmem.avgGap 27510.85 # Average gap between requests 225system.physmem.pageHitRate 78.00 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 849660 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 436425 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 4191180 # Energy for read commands per rank (pJ) |
| 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 230system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 16092810 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 54750 # Energy for precharge background per rank (pJ) 233system.physmem_0.totalEnergy 23482530 # Total energy per rank (pJ) 234system.physmem_0.averagePower 994.232548 # Core power per rank (mW) 235system.physmem_0.memoryStateTime::IDLE 763000 # Time in different power states | 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 6127500 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 5972460 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 19470105 # Total energy per rank (pJ) 237system.physmem_0.averagePower 730.243038 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 12953500 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states |
| 236system.physmem_0.memoryStateTime::REF 780000 # Time in different power states | 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states |
| 237system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 238system.physmem_0.memoryStateTime::ACT 22830000 # Time in different power states 239system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 240system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ) 241system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ) 242system.physmem_1.readEnergy 2628600 # Energy for read commands per rank (pJ) | 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 12735000 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 13102250 # Time in different power states 245system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 330165 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 2720340 # Energy for read commands per rank (pJ) |
| 243system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 244system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) 245system.physmem_1.actBackEnergy 15488325 # Energy for active background per rank (pJ) 246system.physmem_1.preBackEnergy 585000 # Energy for precharge background per rank (pJ) 247system.physmem_1.totalEnergy 21314310 # Total energy per rank (pJ) 248system.physmem_1.averagePower 902.431754 # Core power per rank (mW) 249system.physmem_1.memoryStateTime::IDLE 878500 # Time in different power states | 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 4612440 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 162240 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 6908970 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 373920 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 17623155 # Total energy per rank (pJ) 256system.physmem_1.averagePower 660.971589 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 16131250 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 312000 # Time in different power states |
| 250system.physmem_1.memoryStateTime::REF 780000 # Time in different power states | 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states |
| 251system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 252system.physmem_1.memoryStateTime::ACT 21974000 # Time in different power states 253system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 254system.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states 255system.cpu.branchPred.lookups 4896 # Number of BP lookups 256system.cpu.branchPred.condPredicted 2917 # Number of conditional branches predicted 257system.cpu.branchPred.condIncorrect 793 # Number of conditional branches incorrect 258system.cpu.branchPred.BTBLookups 3827 # Number of BTB lookups 259system.cpu.branchPred.BTBHits 1151 # Number of BTB hits | 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 973000 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 9438250 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 15158250 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 4864 # Number of BP lookups 266system.cpu.branchPred.condPredicted 2895 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 795 # Number of conditional branches incorrect 268system.cpu.branchPred.BTBLookups 3714 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 1183 # Number of BTB hits |
| 260system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 261system.cpu.branchPred.BTBHitPct 30.075777 # BTB Hit Percentage 262system.cpu.branchPred.usedRAS 688 # Number of times the RAS was used to get a target. 263system.cpu.branchPred.RASInCorrect 51 # Number of incorrect RAS predictions. 264system.cpu.branchPred.indirectLookups 820 # Number of indirect predictor lookups. 265system.cpu.branchPred.indirectHits 149 # Number of indirect target hits. 266system.cpu.branchPred.indirectMisses 671 # Number of indirect misses. 267system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. | 271system.cpu.branchPred.BTBHitPct 31.852450 # BTB Hit Percentage 272system.cpu.branchPred.usedRAS 710 # Number of times the RAS was used to get a target. 273system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 762 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 147 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 615 # Number of indirect misses. 277system.cpu.branchPredindirectMispredicted 133 # Number of mispredicted indirect branches. |
| 268system.cpu_clk_domain.clock 500 # Clock period in ticks 269system.cpu.dtb.fetch_hits 0 # ITB hits 270system.cpu.dtb.fetch_misses 0 # ITB misses 271system.cpu.dtb.fetch_acv 0 # ITB acv 272system.cpu.dtb.fetch_accesses 0 # ITB accesses | 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.fetch_hits 0 # ITB hits 280system.cpu.dtb.fetch_misses 0 # ITB misses 281system.cpu.dtb.fetch_acv 0 # ITB acv 282system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 273system.cpu.dtb.read_hits 4131 # DTB read hits 274system.cpu.dtb.read_misses 80 # DTB read misses | 283system.cpu.dtb.read_hits 4130 # DTB read hits 284system.cpu.dtb.read_misses 76 # DTB read misses |
| 275system.cpu.dtb.read_acv 0 # DTB read access violations | 285system.cpu.dtb.read_acv 0 # DTB read access violations |
| 276system.cpu.dtb.read_accesses 4211 # DTB read accesses 277system.cpu.dtb.write_hits 2002 # DTB write hits 278system.cpu.dtb.write_misses 47 # DTB write misses | 286system.cpu.dtb.read_accesses 4206 # DTB read accesses 287system.cpu.dtb.write_hits 2011 # DTB write hits 288system.cpu.dtb.write_misses 48 # DTB write misses |
| 279system.cpu.dtb.write_acv 0 # DTB write access violations | 289system.cpu.dtb.write_acv 0 # DTB write access violations |
| 280system.cpu.dtb.write_accesses 2049 # DTB write accesses 281system.cpu.dtb.data_hits 6133 # DTB hits 282system.cpu.dtb.data_misses 127 # DTB misses | 290system.cpu.dtb.write_accesses 2059 # DTB write accesses 291system.cpu.dtb.data_hits 6141 # DTB hits 292system.cpu.dtb.data_misses 124 # DTB misses |
| 283system.cpu.dtb.data_acv 0 # DTB access violations | 293system.cpu.dtb.data_acv 0 # DTB access violations |
| 284system.cpu.dtb.data_accesses 6260 # DTB accesses 285system.cpu.itb.fetch_hits 3841 # ITB hits | 294system.cpu.dtb.data_accesses 6265 # DTB accesses 295system.cpu.itb.fetch_hits 3836 # ITB hits |
| 286system.cpu.itb.fetch_misses 50 # ITB misses 287system.cpu.itb.fetch_acv 0 # ITB acv | 296system.cpu.itb.fetch_misses 50 # ITB misses 297system.cpu.itb.fetch_acv 0 # ITB acv |
| 288system.cpu.itb.fetch_accesses 3891 # ITB accesses | 298system.cpu.itb.fetch_accesses 3886 # ITB accesses |
| 289system.cpu.itb.read_hits 0 # DTB read hits 290system.cpu.itb.read_misses 0 # DTB read misses 291system.cpu.itb.read_acv 0 # DTB read access violations 292system.cpu.itb.read_accesses 0 # DTB read accesses 293system.cpu.itb.write_hits 0 # DTB write hits 294system.cpu.itb.write_misses 0 # DTB write misses 295system.cpu.itb.write_acv 0 # DTB write access violations 296system.cpu.itb.write_accesses 0 # DTB write accesses 297system.cpu.itb.data_hits 0 # DTB hits 298system.cpu.itb.data_misses 0 # DTB misses 299system.cpu.itb.data_acv 0 # DTB access violations 300system.cpu.itb.data_accesses 0 # DTB accesses 301system.cpu.workload0.num_syscalls 17 # Number of system calls 302system.cpu.workload1.num_syscalls 17 # Number of system calls | 299system.cpu.itb.read_hits 0 # DTB read hits 300system.cpu.itb.read_misses 0 # DTB read misses 301system.cpu.itb.read_acv 0 # DTB read access violations 302system.cpu.itb.read_accesses 0 # DTB read accesses 303system.cpu.itb.write_hits 0 # DTB write hits 304system.cpu.itb.write_misses 0 # DTB write misses 305system.cpu.itb.write_acv 0 # DTB write access violations 306system.cpu.itb.write_accesses 0 # DTB write accesses 307system.cpu.itb.data_hits 0 # DTB hits 308system.cpu.itb.data_misses 0 # DTB misses 309system.cpu.itb.data_acv 0 # DTB access violations 310system.cpu.itb.data_accesses 0 # DTB accesses 311system.cpu.workload0.num_syscalls 17 # Number of system calls 312system.cpu.workload1.num_syscalls 17 # Number of system calls |
| 303system.cpu.pwrStateResidencyTicks::ON 25607000 # Cumulative time (in ticks) in various power states 304system.cpu.numCycles 51215 # number of cpu cycles simulated | 313system.cpu.pwrStateResidencyTicks::ON 26661500 # Cumulative time (in ticks) in various power states 314system.cpu.numCycles 53324 # number of cpu cycles simulated |
| 305system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 306system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 315system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 316system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 307system.cpu.fetch.icacheStallCycles 758 # Number of cycles fetch is stalled on an Icache miss 308system.cpu.fetch.Insts 28344 # Number of instructions fetch has processed 309system.cpu.fetch.Branches 4896 # Number of branches that fetch encountered 310system.cpu.fetch.predictedBranches 1988 # Number of branches that fetch has predicted taken 311system.cpu.fetch.Cycles 10026 # Number of cycles fetch has run and was not squashing or blocked 312system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing 313system.cpu.fetch.MiscStallCycles 478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 314system.cpu.fetch.CacheLines 3841 # Number of cache lines fetched 315system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed 316system.cpu.fetch.rateDist::samples 26635 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::mean 1.064164 # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::stdev 2.464308 # Number of instructions fetched each cycle (Total) | 317system.cpu.fetch.icacheStallCycles 748 # Number of cycles fetch is stalled on an Icache miss 318system.cpu.fetch.Insts 27869 # Number of instructions fetch has processed 319system.cpu.fetch.Branches 4864 # Number of branches that fetch encountered 320system.cpu.fetch.predictedBranches 2040 # Number of branches that fetch has predicted taken 321system.cpu.fetch.Cycles 9408 # Number of cycles fetch has run and was not squashing or blocked 322system.cpu.fetch.SquashCycles 875 # Number of cycles fetch has spent squashing 323system.cpu.fetch.MiscStallCycles 344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 324system.cpu.fetch.CacheLines 3836 # Number of cache lines fetched 325system.cpu.fetch.IcacheSquashes 566 # Number of outstanding Icache misses that were squashed 326system.cpu.fetch.rateDist::samples 26300 # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::mean 1.059658 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::stdev 2.449516 # Number of instructions fetched each cycle (Total) |
| 319system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 320system.cpu.fetch.rateDist::0 21569 80.98% 80.98% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::1 505 1.90% 82.88% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::2 398 1.49% 84.37% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::3 435 1.63% 86.00% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::4 472 1.77% 87.78% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::5 332 1.25% 89.02% # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::6 468 1.76% 90.78% # Number of instructions fetched each cycle (Total) 327system.cpu.fetch.rateDist::7 266 1.00% 91.78% # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.rateDist::8 2190 8.22% 100.00% # Number of instructions fetched each cycle (Total) | 330system.cpu.fetch.rateDist::0 21275 80.89% 80.89% # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::1 504 1.92% 82.81% # Number of instructions fetched each cycle (Total) 332system.cpu.fetch.rateDist::2 391 1.49% 84.30% # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.rateDist::3 446 1.70% 85.99% # Number of instructions fetched each cycle (Total) 334system.cpu.fetch.rateDist::4 478 1.82% 87.81% # Number of instructions fetched each cycle (Total) 335system.cpu.fetch.rateDist::5 367 1.40% 89.21% # Number of instructions fetched each cycle (Total) 336system.cpu.fetch.rateDist::6 469 1.78% 90.99% # Number of instructions fetched each cycle (Total) 337system.cpu.fetch.rateDist::7 276 1.05% 92.04% # Number of instructions fetched each cycle (Total) 338system.cpu.fetch.rateDist::8 2094 7.96% 100.00% # Number of instructions fetched each cycle (Total) |
| 329system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 330system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 331system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 332system.cpu.fetch.rateDist::total 26635 # Number of instructions fetched each cycle (Total) 333system.cpu.fetch.branchRate 0.095597 # Number of branch fetches per cycle 334system.cpu.fetch.rate 0.553432 # Number of inst fetches per cycle 335system.cpu.decode.IdleCycles 36561 # Number of cycles decode is idle 336system.cpu.decode.BlockedCycles 11106 # Number of cycles decode is blocked 337system.cpu.decode.RunCycles 3971 # Number of cycles decode is running 338system.cpu.decode.UnblockCycles 513 # Number of cycles decode is unblocking 339system.cpu.decode.SquashCycles 726 # Number of cycles decode is squashing 340system.cpu.decode.BranchResolved 381 # Number of times decode resolved a branch 341system.cpu.decode.BranchMispred 147 # Number of times decode detected a branch misprediction 342system.cpu.decode.DecodedInsts 24763 # Number of instructions handled by decode 343system.cpu.decode.SquashedInsts 394 # Number of squashed instructions handled by decode 344system.cpu.rename.SquashCycles 726 # Number of cycles rename is squashing 345system.cpu.rename.IdleCycles 36906 # Number of cycles rename is idle 346system.cpu.rename.BlockCycles 4191 # Number of cycles rename is blocking 347system.cpu.rename.serializeStallCycles 1623 # count of cycles rename stalled for serializing inst 348system.cpu.rename.RunCycles 4148 # Number of cycles rename is running 349system.cpu.rename.UnblockCycles 5283 # Number of cycles rename is unblocking 350system.cpu.rename.RenamedInsts 23783 # Number of instructions processed by rename 351system.cpu.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full 352system.cpu.rename.IQFullEvents 282 # Number of times rename has blocked due to IQ full 353system.cpu.rename.LQFullEvents 398 # Number of times rename has blocked due to LQ full 354system.cpu.rename.SQFullEvents 4456 # Number of times rename has blocked due to SQ full 355system.cpu.rename.RenamedOperands 17841 # Number of destination operands rename has renamed 356system.cpu.rename.RenameLookups 29807 # Number of register rename lookups that rename has made 357system.cpu.rename.int_rename_lookups 29789 # Number of integer rename lookups | 342system.cpu.fetch.rateDist::total 26300 # Number of instructions fetched each cycle (Total) 343system.cpu.fetch.branchRate 0.091216 # Number of branch fetches per cycle 344system.cpu.fetch.rate 0.522635 # Number of inst fetches per cycle 345system.cpu.decode.IdleCycles 36528 # Number of cycles decode is idle 346system.cpu.decode.BlockedCycles 10375 # Number of cycles decode is blocked 347system.cpu.decode.RunCycles 3958 # Number of cycles decode is running 348system.cpu.decode.UnblockCycles 495 # Number of cycles decode is unblocking 349system.cpu.decode.SquashCycles 725 # Number of cycles decode is squashing 350system.cpu.decode.BranchResolved 405 # Number of times decode resolved a branch 351system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction 352system.cpu.decode.DecodedInsts 24583 # Number of instructions handled by decode 353system.cpu.decode.SquashedInsts 377 # Number of squashed instructions handled by decode 354system.cpu.rename.SquashCycles 725 # Number of cycles rename is squashing 355system.cpu.rename.IdleCycles 36872 # Number of cycles rename is idle 356system.cpu.rename.BlockCycles 3499 # Number of cycles rename is blocking 357system.cpu.rename.serializeStallCycles 1435 # count of cycles rename stalled for serializing inst 358system.cpu.rename.RunCycles 4116 # Number of cycles rename is running 359system.cpu.rename.UnblockCycles 5434 # Number of cycles rename is unblocking 360system.cpu.rename.RenamedInsts 23584 # Number of instructions processed by rename 361system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full 362system.cpu.rename.IQFullEvents 223 # Number of times rename has blocked due to IQ full 363system.cpu.rename.LQFullEvents 328 # Number of times rename has blocked due to LQ full 364system.cpu.rename.SQFullEvents 4703 # Number of times rename has blocked due to SQ full 365system.cpu.rename.RenamedOperands 17574 # Number of destination operands rename has renamed 366system.cpu.rename.RenameLookups 29532 # Number of register rename lookups that rename has made 367system.cpu.rename.int_rename_lookups 29514 # Number of integer rename lookups |
| 358system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 359system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed | 368system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups 369system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed |
| 360system.cpu.rename.UndoneMaps 8687 # Number of HB maps that are undone due to squashing | 370system.cpu.rename.UndoneMaps 8420 # Number of HB maps that are undone due to squashing |
| 361system.cpu.rename.serializingInsts 57 # count of serializing insts renamed 362system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed | 371system.cpu.rename.serializingInsts 57 # count of serializing insts renamed 372system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed |
| 363system.cpu.rename.skidInsts 1771 # count of insts added to the skid buffer 364system.cpu.memDep0.insertedLoads 2529 # Number of loads inserted to the mem dependence unit. 365system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit. 366system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads. 367system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. 368system.cpu.memDep1.insertedLoads 1973 # Number of loads inserted to the mem dependence unit. 369system.cpu.memDep1.insertedStores 1111 # Number of stores inserted to the mem dependence unit. 370system.cpu.memDep1.conflictingLoads 6 # Number of conflicting loads. 371system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. 372system.cpu.iq.iqInstsAdded 21942 # Number of instructions added to the IQ (excludes non-spec) 373system.cpu.iq.iqNonSpecInstsAdded 50 # Number of non-speculative instructions added to the IQ | 373system.cpu.rename.skidInsts 1621 # count of insts added to the skid buffer 374system.cpu.memDep0.insertedLoads 1925 # Number of loads inserted to the mem dependence unit. 375system.cpu.memDep0.insertedStores 1093 # Number of stores inserted to the mem dependence unit. 376system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads. 377system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 378system.cpu.memDep1.insertedLoads 2578 # Number of loads inserted to the mem dependence unit. 379system.cpu.memDep1.insertedStores 1286 # Number of stores inserted to the mem dependence unit. 380system.cpu.memDep1.conflictingLoads 15 # Number of conflicting loads. 381system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores. 382system.cpu.iq.iqInstsAdded 21800 # Number of instructions added to the IQ (excludes non-spec) 383system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ |
| 374system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued | 384system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued |
| 375system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued 376system.cpu.iq.iqSquashedInstsExamined 9221 # Number of squashed instructions iterated over during squash; mainly for profiling 377system.cpu.iq.iqSquashedOperandsExamined 4863 # Number of squashed operands that are examined and possibly removed from graph 378system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed 379system.cpu.iq.issued_per_cycle::samples 26635 # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::mean 0.724460 # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::stdev 1.451046 # Number of insts issued each cycle | 385system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued 386system.cpu.iq.iqSquashedInstsExamined 9080 # Number of squashed instructions iterated over during squash; mainly for profiling 387system.cpu.iq.iqSquashedOperandsExamined 4753 # Number of squashed operands that are examined and possibly removed from graph 388system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed 389system.cpu.iq.issued_per_cycle::samples 26300 # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::mean 0.733688 # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::stdev 1.450617 # Number of insts issued each cycle |
| 382system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 392system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 383system.cpu.iq.issued_per_cycle::0 19310 72.50% 72.50% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::1 2394 8.99% 81.49% # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::2 1620 6.08% 87.57% # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::3 1274 4.78% 92.35% # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::4 1030 3.87% 96.22% # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::5 532 2.00% 98.22% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::6 319 1.20% 99.41% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::7 102 0.38% 99.80% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::8 54 0.20% 100.00% # Number of insts issued each cycle | 393system.cpu.iq.issued_per_cycle::0 18970 72.13% 72.13% # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::1 2362 8.98% 81.11% # Number of insts issued each cycle 395system.cpu.iq.issued_per_cycle::2 1626 6.18% 87.29% # Number of insts issued each cycle 396system.cpu.iq.issued_per_cycle::3 1294 4.92% 92.21% # Number of insts issued each cycle 397system.cpu.iq.issued_per_cycle::4 1061 4.03% 96.25% # Number of insts issued each cycle 398system.cpu.iq.issued_per_cycle::5 563 2.14% 98.39% # Number of insts issued each cycle 399system.cpu.iq.issued_per_cycle::6 282 1.07% 99.46% # Number of insts issued each cycle 400system.cpu.iq.issued_per_cycle::7 87 0.33% 99.79% # Number of insts issued each cycle 401system.cpu.iq.issued_per_cycle::8 55 0.21% 100.00% # Number of insts issued each cycle |
| 392system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 393system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 394system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 402system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 403system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 404system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 395system.cpu.iq.issued_per_cycle::total 26635 # Number of insts issued each cycle | 405system.cpu.iq.issued_per_cycle::total 26300 # Number of insts issued each cycle |
| 396system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 406system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 397system.cpu.iq.fu_full::IntAlu 28 9.18% 9.18% # attempts to use FU when none available 398system.cpu.iq.fu_full::IntMult 0 0.00% 9.18% # attempts to use FU when none available 399system.cpu.iq.fu_full::IntDiv 0 0.00% 9.18% # attempts to use FU when none available 400system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.18% # attempts to use FU when none available 401system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.18% # attempts to use FU when none available 402system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.18% # attempts to use FU when none available 403system.cpu.iq.fu_full::FloatMult 0 0.00% 9.18% # attempts to use FU when none available 404system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.18% # attempts to use FU when none available 405system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.18% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.18% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.18% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.18% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.18% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.18% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.18% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdMult 0 0.00% 9.18% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.18% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdShift 0 0.00% 9.18% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.18% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.18% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.18% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.18% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.18% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.18% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.18% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.18% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.18% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.18% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.18% # attempts to use FU when none available 426system.cpu.iq.fu_full::MemRead 201 65.90% 75.08% # attempts to use FU when none available 427system.cpu.iq.fu_full::MemWrite 76 24.92% 100.00% # attempts to use FU when none available | 407system.cpu.iq.fu_full::IntAlu 29 9.70% 9.70% # attempts to use FU when none available 408system.cpu.iq.fu_full::IntMult 0 0.00% 9.70% # attempts to use FU when none available 409system.cpu.iq.fu_full::IntDiv 0 0.00% 9.70% # attempts to use FU when none available 410system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.70% # attempts to use FU when none available 411system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.70% # attempts to use FU when none available 412system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.70% # attempts to use FU when none available 413system.cpu.iq.fu_full::FloatMult 0 0.00% 9.70% # attempts to use FU when none available 414system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.70% # attempts to use FU when none available 415system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.70% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.70% # attempts to use FU when none available 417system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.70% # attempts to use FU when none available 418system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.70% # attempts to use FU when none available 419system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.70% # attempts to use FU when none available 420system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.70% # attempts to use FU when none available 421system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.70% # attempts to use FU when none available 422system.cpu.iq.fu_full::SimdMult 0 0.00% 9.70% # attempts to use FU when none available 423system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.70% # attempts to use FU when none available 424system.cpu.iq.fu_full::SimdShift 0 0.00% 9.70% # attempts to use FU when none available 425system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.70% # attempts to use FU when none available 426system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.70% # attempts to use FU when none available 427system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.70% # attempts to use FU when none available 428system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.70% # attempts to use FU when none available 429system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.70% # attempts to use FU when none available 430system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.70% # attempts to use FU when none available 431system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.70% # attempts to use FU when none available 432system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.70% # attempts to use FU when none available 433system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.70% # attempts to use FU when none available 434system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.70% # attempts to use FU when none available 435system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.70% # attempts to use FU when none available 436system.cpu.iq.fu_full::MemRead 191 63.88% 73.58% # attempts to use FU when none available 437system.cpu.iq.fu_full::MemWrite 79 26.42% 100.00% # attempts to use FU when none available |
| 428system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 429system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 430system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued | 438system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 439system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 440system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued |
| 431system.cpu.iq.FU_type_0::IntAlu 6749 65.93% 65.95% # Type of FU issued 432system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.96% # Type of FU issued 433system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.96% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.98% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued 437system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued 438system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued 439system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued 460system.cpu.iq.FU_type_0::MemRead 2387 23.32% 89.30% # Type of FU issued 461system.cpu.iq.FU_type_0::MemWrite 1095 10.70% 100.00% # Type of FU issued | 441system.cpu.iq.FU_type_0::IntAlu 5884 66.04% 66.06% # Type of FU issued 442system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.07% # Type of FU issued 443system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued 444system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.09% # Type of FU issued 445system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued 446system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued 447system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued 448system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued 449system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued 457system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued 458system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued 459system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued 460system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued 461system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued 462system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued 463system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued 464system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued 465system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued 466system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued 467system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued 468system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued 469system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued 470system.cpu.iq.FU_type_0::MemRead 2015 22.62% 88.71% # Type of FU issued 471system.cpu.iq.FU_type_0::MemWrite 1006 11.29% 100.00% # Type of FU issued |
| 462system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 463system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 472system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 473system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 464system.cpu.iq.FU_type_0::total 10236 # Type of FU issued | 474system.cpu.iq.FU_type_0::total 8910 # Type of FU issued |
| 465system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued | 475system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued |
| 466system.cpu.iq.FU_type_1::IntAlu 6020 66.45% 66.47% # Type of FU issued 467system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.48% # Type of FU issued 468system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.48% # Type of FU issued 469system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.50% # Type of FU issued 470system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.50% # Type of FU issued 471system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.50% # Type of FU issued 472system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.50% # Type of FU issued 473system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.50% # Type of FU issued 474system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.50% # Type of FU issued 475system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.50% # Type of FU issued 476system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.50% # Type of FU issued 477system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.50% # Type of FU issued 478system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.50% # Type of FU issued 479system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.50% # Type of FU issued 480system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.50% # Type of FU issued 481system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.50% # Type of FU issued 482system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.50% # Type of FU issued 483system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.50% # Type of FU issued 484system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.50% # Type of FU issued 485system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.50% # Type of FU issued 486system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.50% # Type of FU issued 487system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.50% # Type of FU issued 488system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.50% # Type of FU issued 489system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.50% # Type of FU issued 490system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.50% # Type of FU issued 491system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.50% # Type of FU issued 492system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.50% # Type of FU issued 493system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.50% # Type of FU issued 494system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.50% # Type of FU issued 495system.cpu.iq.FU_type_1::MemRead 2019 22.28% 88.79% # Type of FU issued 496system.cpu.iq.FU_type_1::MemWrite 1016 11.21% 100.00% # Type of FU issued | 476system.cpu.iq.FU_type_1::IntAlu 6849 65.94% 65.96% # Type of FU issued 477system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued 478system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.97% # Type of FU issued 479system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Type of FU issued 480system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued 481system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued 482system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued 483system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued 484system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued 485system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued 486system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued 487system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.99% # Type of FU issued 488system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.99% # Type of FU issued 489system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.99% # Type of FU issued 490system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.99% # Type of FU issued 491system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.99% # Type of FU issued 492system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.99% # Type of FU issued 493system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.99% # Type of FU issued 494system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued 495system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.99% # Type of FU issued 496system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued 497system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued 498system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued 499system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued 500system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued 501system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued 502system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued 503system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued 504system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued 505system.cpu.iq.FU_type_1::MemRead 2411 23.21% 89.21% # Type of FU issued 506system.cpu.iq.FU_type_1::MemWrite 1121 10.79% 100.00% # Type of FU issued |
| 497system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 498system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 507system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued 508system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 499system.cpu.iq.FU_type_1::total 9060 # Type of FU issued | 509system.cpu.iq.FU_type_1::total 10386 # Type of FU issued |
| 500system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued | 510system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued |
| 501system.cpu.iq.rate 0.376765 # Inst issue rate 502system.cpu.iq.fu_busy_cnt::0 157 # FU busy when requested | 511system.cpu.iq.rate 0.361863 # Inst issue rate 512system.cpu.iq.fu_busy_cnt::0 151 # FU busy when requested |
| 503system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested | 513system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested |
| 504system.cpu.iq.fu_busy_cnt::total 305 # FU busy when requested 505system.cpu.iq.fu_busy_rate::0 0.008136 # FU busy rate (busy events/executed inst) | 514system.cpu.iq.fu_busy_cnt::total 299 # FU busy when requested 515system.cpu.iq.fu_busy_rate::0 0.007825 # FU busy rate (busy events/executed inst) |
| 506system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst) | 516system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst) |
| 507system.cpu.iq.fu_busy_rate::total 0.015806 # FU busy rate (busy events/executed inst) 508system.cpu.iq.int_inst_queue_reads 65537 # Number of integer instruction queue reads 509system.cpu.iq.int_inst_queue_writes 31224 # Number of integer instruction queue writes 510system.cpu.iq.int_inst_queue_wakeup_accesses 17544 # Number of integer instruction queue wakeup accesses | 517system.cpu.iq.fu_busy_rate::total 0.015495 # FU busy rate (busy events/executed inst) 518system.cpu.iq.int_inst_queue_reads 65200 # Number of integer instruction queue reads 519system.cpu.iq.int_inst_queue_writes 30942 # Number of integer instruction queue writes 520system.cpu.iq.int_inst_queue_wakeup_accesses 17504 # Number of integer instruction queue wakeup accesses |
| 511system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 512system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 513system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses | 521system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads 522system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes 523system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses |
| 514system.cpu.iq.int_alu_accesses 19575 # Number of integer alu accesses | 524system.cpu.iq.int_alu_accesses 19569 # Number of integer alu accesses |
| 515system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses | 525system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses |
| 516system.cpu.iew.lsq.thread0.forwLoads 93 # Number of loads that had data forwarded from stores | 526system.cpu.iew.lsq.thread0.forwLoads 39 # Number of loads that had data forwarded from stores |
| 517system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 527system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 518system.cpu.iew.lsq.thread0.squashedLoads 1344 # Number of loads squashed 519system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed 520system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 521system.cpu.iew.lsq.thread0.squashedStores 388 # Number of stores squashed | 528system.cpu.iew.lsq.thread0.squashedLoads 740 # Number of loads squashed 529system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 530system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations 531system.cpu.iew.lsq.thread0.squashedStores 228 # Number of stores squashed |
| 522system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 523system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 524system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled | 532system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 533system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 534system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled |
| 525system.cpu.iew.lsq.thread0.cacheBlocked 261 # Number of times an access to memory failed due to the cache being blocked 526system.cpu.iew.lsq.thread1.forwLoads 45 # Number of loads that had data forwarded from stores | 535system.cpu.iew.lsq.thread0.cacheBlocked 290 # Number of times an access to memory failed due to the cache being blocked 536system.cpu.iew.lsq.thread1.forwLoads 97 # Number of loads that had data forwarded from stores |
| 527system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address | 537system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 528system.cpu.iew.lsq.thread1.squashedLoads 788 # Number of loads squashed 529system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed 530system.cpu.iew.lsq.thread1.memOrderViolation 12 # Number of memory ordering violations 531system.cpu.iew.lsq.thread1.squashedStores 246 # Number of stores squashed | 538system.cpu.iew.lsq.thread1.squashedLoads 1393 # Number of loads squashed 539system.cpu.iew.lsq.thread1.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed 540system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations 541system.cpu.iew.lsq.thread1.squashedStores 421 # Number of stores squashed |
| 532system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 533system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 534system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled | 542system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 543system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 544system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled |
| 535system.cpu.iew.lsq.thread1.cacheBlocked 288 # Number of times an access to memory failed due to the cache being blocked | 545system.cpu.iew.lsq.thread1.cacheBlocked 234 # Number of times an access to memory failed due to the cache being blocked |
| 536system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 546system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 537system.cpu.iew.iewSquashCycles 726 # Number of cycles IEW is squashing 538system.cpu.iew.iewBlockCycles 2949 # Number of cycles IEW is blocking 539system.cpu.iew.iewUnblockCycles 377 # Number of cycles IEW is unblocking 540system.cpu.iew.iewDispatchedInsts 22125 # Number of instructions dispatched to IQ 541system.cpu.iew.iewDispSquashedInsts 143 # Number of squashed instructions skipped by dispatch 542system.cpu.iew.iewDispLoadInsts 4502 # Number of dispatched load instructions 543system.cpu.iew.iewDispStoreInsts 2364 # Number of dispatched store instructions 544system.cpu.iew.iewDispNonSpecInsts 50 # Number of dispatched non-speculative instructions 545system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall 546system.cpu.iew.iewLSQFullEvents 340 # Number of times the LSQ has become full, causing a stall | 547system.cpu.iew.iewSquashCycles 725 # Number of cycles IEW is squashing 548system.cpu.iew.iewBlockCycles 1992 # Number of cycles IEW is blocking 549system.cpu.iew.iewUnblockCycles 420 # Number of cycles IEW is unblocking 550system.cpu.iew.iewDispatchedInsts 21985 # Number of instructions dispatched to IQ 551system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch 552system.cpu.iew.iewDispLoadInsts 4503 # Number of dispatched load instructions 553system.cpu.iew.iewDispStoreInsts 2379 # Number of dispatched store instructions 554system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions 555system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall 556system.cpu.iew.iewLSQFullEvents 390 # Number of times the LSQ has become full, causing a stall |
| 547system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations | 557system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations |
| 548system.cpu.iew.predictedTakenIncorrect 130 # Number of branches that were predicted taken incorrectly 549system.cpu.iew.predictedNotTakenIncorrect 639 # Number of branches that were predicted not taken incorrectly 550system.cpu.iew.branchMispredicts 769 # Number of branch mispredicts detected at execute 551system.cpu.iew.iewExecutedInsts 18625 # Number of executed instructions 552system.cpu.iew.iewExecLoadInsts::0 2260 # Number of load instructions executed 553system.cpu.iew.iewExecLoadInsts::1 1960 # Number of load instructions executed 554system.cpu.iew.iewExecLoadInsts::total 4220 # Number of load instructions executed 555system.cpu.iew.iewExecSquashedInsts 671 # Number of squashed instructions skipped in execute | 558system.cpu.iew.predictedTakenIncorrect 134 # Number of branches that were predicted taken incorrectly 559system.cpu.iew.predictedNotTakenIncorrect 638 # Number of branches that were predicted not taken incorrectly 560system.cpu.iew.branchMispredicts 772 # Number of branch mispredicts detected at execute 561system.cpu.iew.iewExecutedInsts 18585 # Number of executed instructions 562system.cpu.iew.iewExecLoadInsts::0 1945 # Number of load instructions executed 563system.cpu.iew.iewExecLoadInsts::1 2264 # Number of load instructions executed 564system.cpu.iew.iewExecLoadInsts::total 4209 # Number of load instructions executed 565system.cpu.iew.iewExecSquashedInsts 711 # Number of squashed instructions skipped in execute |
| 556system.cpu.iew.exec_swp::0 0 # number of swp insts executed 557system.cpu.iew.exec_swp::1 0 # number of swp insts executed 558system.cpu.iew.exec_swp::total 0 # number of swp insts executed | 566system.cpu.iew.exec_swp::0 0 # number of swp insts executed 567system.cpu.iew.exec_swp::1 0 # number of swp insts executed 568system.cpu.iew.exec_swp::total 0 # number of swp insts executed |
| 559system.cpu.iew.exec_nop::0 66 # number of nop insts executed 560system.cpu.iew.exec_nop::1 67 # number of nop insts executed 561system.cpu.iew.exec_nop::total 133 # number of nop insts executed 562system.cpu.iew.exec_refs::0 3318 # number of memory reference insts executed 563system.cpu.iew.exec_refs::1 2963 # number of memory reference insts executed 564system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed 565system.cpu.iew.exec_branches::0 1546 # Number of branches executed 566system.cpu.iew.exec_branches::1 1419 # Number of branches executed 567system.cpu.iew.exec_branches::total 2965 # Number of branches executed 568system.cpu.iew.exec_stores::0 1058 # Number of stores executed 569system.cpu.iew.exec_stores::1 1003 # Number of stores executed 570system.cpu.iew.exec_stores::total 2061 # Number of stores executed 571system.cpu.iew.exec_rate 0.363663 # Inst execution rate 572system.cpu.iew.wb_sent::0 9379 # cumulative count of insts sent to commit 573system.cpu.iew.wb_sent::1 8440 # cumulative count of insts sent to commit 574system.cpu.iew.wb_sent::total 17819 # cumulative count of insts sent to commit 575system.cpu.iew.wb_count::0 9213 # cumulative count of insts written-back 576system.cpu.iew.wb_count::1 8351 # cumulative count of insts written-back 577system.cpu.iew.wb_count::total 17564 # cumulative count of insts written-back 578system.cpu.iew.wb_producers::0 4854 # num instructions producing a value 579system.cpu.iew.wb_producers::1 4443 # num instructions producing a value 580system.cpu.iew.wb_producers::total 9297 # num instructions producing a value 581system.cpu.iew.wb_consumers::0 6502 # num instructions consuming a value 582system.cpu.iew.wb_consumers::1 5954 # num instructions consuming a value 583system.cpu.iew.wb_consumers::total 12456 # num instructions consuming a value 584system.cpu.iew.wb_rate::0 0.179889 # insts written-back per cycle 585system.cpu.iew.wb_rate::1 0.163058 # insts written-back per cycle 586system.cpu.iew.wb_rate::total 0.342946 # insts written-back per cycle 587system.cpu.iew.wb_fanout::0 0.746540 # average fanout of values written-back 588system.cpu.iew.wb_fanout::1 0.746221 # average fanout of values written-back 589system.cpu.iew.wb_fanout::total 0.746387 # average fanout of values written-back 590system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit | 569system.cpu.iew.exec_nop::0 63 # number of nop insts executed 570system.cpu.iew.exec_nop::1 71 # number of nop insts executed 571system.cpu.iew.exec_nop::total 134 # number of nop insts executed 572system.cpu.iew.exec_refs::0 2942 # number of memory reference insts executed 573system.cpu.iew.exec_refs::1 3338 # number of memory reference insts executed 574system.cpu.iew.exec_refs::total 6280 # number of memory reference insts executed 575system.cpu.iew.exec_branches::0 1393 # Number of branches executed 576system.cpu.iew.exec_branches::1 1580 # Number of branches executed 577system.cpu.iew.exec_branches::total 2973 # Number of branches executed 578system.cpu.iew.exec_stores::0 997 # Number of stores executed 579system.cpu.iew.exec_stores::1 1074 # Number of stores executed 580system.cpu.iew.exec_stores::total 2071 # Number of stores executed 581system.cpu.iew.exec_rate 0.348530 # Inst execution rate 582system.cpu.iew.wb_sent::0 8281 # cumulative count of insts sent to commit 583system.cpu.iew.wb_sent::1 9496 # cumulative count of insts sent to commit 584system.cpu.iew.wb_sent::total 17777 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count::0 8197 # cumulative count of insts written-back 586system.cpu.iew.wb_count::1 9327 # cumulative count of insts written-back 587system.cpu.iew.wb_count::total 17524 # cumulative count of insts written-back 588system.cpu.iew.wb_producers::0 4340 # num instructions producing a value 589system.cpu.iew.wb_producers::1 4919 # num instructions producing a value 590system.cpu.iew.wb_producers::total 9259 # num instructions producing a value 591system.cpu.iew.wb_consumers::0 5879 # num instructions consuming a value 592system.cpu.iew.wb_consumers::1 6619 # num instructions consuming a value 593system.cpu.iew.wb_consumers::total 12498 # num instructions consuming a value 594system.cpu.iew.wb_rate::0 0.153721 # insts written-back per cycle 595system.cpu.iew.wb_rate::1 0.174912 # insts written-back per cycle 596system.cpu.iew.wb_rate::total 0.328633 # insts written-back per cycle 597system.cpu.iew.wb_fanout::0 0.738221 # average fanout of values written-back 598system.cpu.iew.wb_fanout::1 0.743164 # average fanout of values written-back 599system.cpu.iew.wb_fanout::total 0.740839 # average fanout of values written-back 600system.cpu.commit.commitSquashedInsts 9130 # The number of squashed insts skipped by commit |
| 591system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards | 601system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards |
| 592system.cpu.commit.branchMispredicts 647 # The number of times a branch was mispredicted 593system.cpu.commit.committed_per_cycle::samples 26599 # Number of insts commited each cycle 594system.cpu.commit.committed_per_cycle::mean 0.481371 # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::stdev 1.387327 # Number of insts commited each cycle | 602system.cpu.commit.branchMispredicts 646 # The number of times a branch was mispredicted 603system.cpu.commit.committed_per_cycle::samples 26282 # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::mean 0.487178 # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::stdev 1.404713 # Number of insts commited each cycle |
| 596system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 606system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 597system.cpu.commit.committed_per_cycle::0 21475 80.74% 80.74% # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::1 2692 10.12% 90.86% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::2 910 3.42% 94.28% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::3 379 1.42% 95.70% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::4 247 0.93% 96.63% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::5 153 0.58% 97.21% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::6 207 0.78% 97.98% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::7 128 0.48% 98.47% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::8 408 1.53% 100.00% # Number of insts commited each cycle | 607system.cpu.commit.committed_per_cycle::0 21298 81.04% 81.04% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::1 2499 9.51% 90.54% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::2 926 3.52% 94.07% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::3 403 1.53% 95.60% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::4 249 0.95% 96.55% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::5 154 0.59% 97.13% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::6 215 0.82% 97.95% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::7 116 0.44% 98.39% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::8 422 1.61% 100.00% # Number of insts commited each cycle |
| 606system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 616system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 617system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 609system.cpu.commit.committed_per_cycle::total 26599 # Number of insts commited each cycle | 619system.cpu.commit.committed_per_cycle::total 26282 # Number of insts commited each cycle |
| 610system.cpu.commit.committedInsts::0 6402 # Number of instructions committed 611system.cpu.commit.committedInsts::1 6402 # Number of instructions committed 612system.cpu.commit.committedInsts::total 12804 # Number of instructions committed 613system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed 614system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed 615system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed 616system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 617system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed --- 85 unchanged lines hidden (view full) --- 703system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 704system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 705system.cpu.commit.op_class_1::MemRead 1185 18.51% 86.49% # Class of committed instruction 706system.cpu.commit.op_class_1::MemWrite 865 13.51% 100.00% # Class of committed instruction 707system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction 708system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 709system.cpu.commit.op_class_1::total 6402 # Class of committed instruction 710system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction | 620system.cpu.commit.committedInsts::0 6402 # Number of instructions committed 621system.cpu.commit.committedInsts::1 6402 # Number of instructions committed 622system.cpu.commit.committedInsts::total 12804 # Number of instructions committed 623system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed 624system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed 625system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed 626system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed 627system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed --- 85 unchanged lines hidden (view full) --- 713system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 714system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 715system.cpu.commit.op_class_1::MemRead 1185 18.51% 86.49% # Class of committed instruction 716system.cpu.commit.op_class_1::MemWrite 865 13.51% 100.00% # Class of committed instruction 717system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction 718system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 719system.cpu.commit.op_class_1::total 6402 # Class of committed instruction 720system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction |
| 711system.cpu.commit.bw_lim_events 408 # number cycles where commit BW limit reached 712system.cpu.rob.rob_reads 113983 # The number of ROB reads 713system.cpu.rob.rob_writes 45899 # The number of ROB writes 714system.cpu.timesIdled 392 # Number of times that the entire CPU went into an idle state and unscheduled itself 715system.cpu.idleCycles 24580 # Total number of cycles that the CPU has spent unscheduled due to idling | 721system.cpu.commit.bw_lim_events 422 # number cycles where commit BW limit reached 722system.cpu.rob.rob_reads 113054 # The number of ROB reads 723system.cpu.rob.rob_writes 45570 # The number of ROB writes 724system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself 725system.cpu.idleCycles 27024 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 716system.cpu.committedInsts::0 6385 # Number of Instructions Simulated 717system.cpu.committedInsts::1 6385 # Number of Instructions Simulated 718system.cpu.committedInsts::total 12770 # Number of Instructions Simulated 719system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated 720system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated 721system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated | 726system.cpu.committedInsts::0 6385 # Number of Instructions Simulated 727system.cpu.committedInsts::1 6385 # Number of Instructions Simulated 728system.cpu.committedInsts::total 12770 # Number of Instructions Simulated 729system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated 730system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated 731system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated |
| 722system.cpu.cpi::0 8.021143 # CPI: Cycles Per Instruction 723system.cpu.cpi::1 8.021143 # CPI: Cycles Per Instruction 724system.cpu.cpi_total 4.010572 # CPI: Total CPI of All Threads 725system.cpu.ipc::0 0.124671 # IPC: Instructions Per Cycle 726system.cpu.ipc::1 0.124671 # IPC: Instructions Per Cycle 727system.cpu.ipc_total 0.249341 # IPC: Total IPC of All Threads 728system.cpu.int_regfile_reads 23552 # number of integer regfile reads 729system.cpu.int_regfile_writes 13174 # number of integer regfile writes | 732system.cpu.cpi::0 8.351449 # CPI: Cycles Per Instruction 733system.cpu.cpi::1 8.351449 # CPI: Cycles Per Instruction 734system.cpu.cpi_total 4.175724 # CPI: Total CPI of All Threads 735system.cpu.ipc::0 0.119740 # IPC: Instructions Per Cycle 736system.cpu.ipc::1 0.119740 # IPC: Instructions Per Cycle 737system.cpu.ipc_total 0.239479 # IPC: Total IPC of All Threads 738system.cpu.int_regfile_reads 23475 # number of integer regfile reads 739system.cpu.int_regfile_writes 13132 # number of integer regfile writes |
| 730system.cpu.fp_regfile_reads 16 # number of floating regfile reads 731system.cpu.fp_regfile_writes 4 # number of floating regfile writes 732system.cpu.misc_regfile_reads 2 # number of misc regfile reads 733system.cpu.misc_regfile_writes 2 # number of misc regfile writes | 740system.cpu.fp_regfile_reads 16 # number of floating regfile reads 741system.cpu.fp_regfile_writes 4 # number of floating regfile writes 742system.cpu.misc_regfile_reads 2 # number of misc regfile reads 743system.cpu.misc_regfile_writes 2 # number of misc regfile writes |
| 734system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states | 744system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states |
| 735system.cpu.dcache.tags.replacements::0 0 # number of replacements 736system.cpu.dcache.tags.replacements::1 0 # number of replacements 737system.cpu.dcache.tags.replacements::total 0 # number of replacements | 745system.cpu.dcache.tags.replacements::0 0 # number of replacements 746system.cpu.dcache.tags.replacements::1 0 # number of replacements 747system.cpu.dcache.tags.replacements::total 0 # number of replacements |
| 738system.cpu.dcache.tags.tagsinuse 214.351374 # Cycle average of tags in use 739system.cpu.dcache.tags.total_refs 4238 # Total number of references to valid blocks. 740system.cpu.dcache.tags.sampled_refs 341 # Sample count of references to valid blocks. 741system.cpu.dcache.tags.avg_refs 12.428152 # Average number of references to valid blocks. | 748system.cpu.dcache.tags.tagsinuse 216.020971 # Cycle average of tags in use 749system.cpu.dcache.tags.total_refs 4236 # Total number of references to valid blocks. 750system.cpu.dcache.tags.sampled_refs 342 # Sample count of references to valid blocks. 751system.cpu.dcache.tags.avg_refs 12.385965 # Average number of references to valid blocks. |
| 742system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 752system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 743system.cpu.dcache.tags.occ_blocks::cpu.data 214.351374 # Average occupied blocks per requestor 744system.cpu.dcache.tags.occ_percent::cpu.data 0.052332 # Average percentage of cache occupancy 745system.cpu.dcache.tags.occ_percent::total 0.052332 # Average percentage of cache occupancy 746system.cpu.dcache.tags.occ_task_id_blocks::1024 341 # Occupied blocks per task id 747system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 748system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id 749system.cpu.dcache.tags.occ_task_id_percent::1024 0.083252 # Percentage of cache occupancy per task id 750system.cpu.dcache.tags.tag_accesses 10843 # Number of tag accesses 751system.cpu.dcache.tags.data_accesses 10843 # Number of data accesses 752system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states 753system.cpu.dcache.ReadReq_hits::cpu.data 3221 # number of ReadReq hits 754system.cpu.dcache.ReadReq_hits::total 3221 # number of ReadReq hits 755system.cpu.dcache.WriteReq_hits::cpu.data 1017 # number of WriteReq hits 756system.cpu.dcache.WriteReq_hits::total 1017 # number of WriteReq hits 757system.cpu.dcache.demand_hits::cpu.data 4238 # number of demand (read+write) hits 758system.cpu.dcache.demand_hits::total 4238 # number of demand (read+write) hits 759system.cpu.dcache.overall_hits::cpu.data 4238 # number of overall hits 760system.cpu.dcache.overall_hits::total 4238 # number of overall hits 761system.cpu.dcache.ReadReq_misses::cpu.data 300 # number of ReadReq misses 762system.cpu.dcache.ReadReq_misses::total 300 # number of ReadReq misses 763system.cpu.dcache.WriteReq_misses::cpu.data 713 # number of WriteReq misses 764system.cpu.dcache.WriteReq_misses::total 713 # number of WriteReq misses 765system.cpu.dcache.demand_misses::cpu.data 1013 # number of demand (read+write) misses 766system.cpu.dcache.demand_misses::total 1013 # number of demand (read+write) misses 767system.cpu.dcache.overall_misses::cpu.data 1013 # number of overall misses 768system.cpu.dcache.overall_misses::total 1013 # number of overall misses 769system.cpu.dcache.ReadReq_miss_latency::cpu.data 25278500 # number of ReadReq miss cycles 770system.cpu.dcache.ReadReq_miss_latency::total 25278500 # number of ReadReq miss cycles 771system.cpu.dcache.WriteReq_miss_latency::cpu.data 49654940 # number of WriteReq miss cycles 772system.cpu.dcache.WriteReq_miss_latency::total 49654940 # number of WriteReq miss cycles 773system.cpu.dcache.demand_miss_latency::cpu.data 74933440 # number of demand (read+write) miss cycles 774system.cpu.dcache.demand_miss_latency::total 74933440 # number of demand (read+write) miss cycles 775system.cpu.dcache.overall_miss_latency::cpu.data 74933440 # number of overall miss cycles 776system.cpu.dcache.overall_miss_latency::total 74933440 # number of overall miss cycles 777system.cpu.dcache.ReadReq_accesses::cpu.data 3521 # number of ReadReq accesses(hits+misses) 778system.cpu.dcache.ReadReq_accesses::total 3521 # number of ReadReq accesses(hits+misses) | 753system.cpu.dcache.tags.occ_blocks::cpu.data 216.020971 # Average occupied blocks per requestor 754system.cpu.dcache.tags.occ_percent::cpu.data 0.052739 # Average percentage of cache occupancy 755system.cpu.dcache.tags.occ_percent::total 0.052739 # Average percentage of cache occupancy 756system.cpu.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id 757system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 758system.cpu.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id 759system.cpu.dcache.tags.occ_task_id_percent::1024 0.083496 # Percentage of cache occupancy per task id 760system.cpu.dcache.tags.tag_accesses 10868 # Number of tag accesses 761system.cpu.dcache.tags.data_accesses 10868 # Number of data accesses 762system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 763system.cpu.dcache.ReadReq_hits::cpu.data 3224 # number of ReadReq hits 764system.cpu.dcache.ReadReq_hits::total 3224 # number of ReadReq hits 765system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits 766system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits 767system.cpu.dcache.demand_hits::cpu.data 4236 # number of demand (read+write) hits 768system.cpu.dcache.demand_hits::total 4236 # number of demand (read+write) hits 769system.cpu.dcache.overall_hits::cpu.data 4236 # number of overall hits 770system.cpu.dcache.overall_hits::total 4236 # number of overall hits 771system.cpu.dcache.ReadReq_misses::cpu.data 309 # number of ReadReq misses 772system.cpu.dcache.ReadReq_misses::total 309 # number of ReadReq misses 773system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses 774system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses 775system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses 776system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses 777system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses 778system.cpu.dcache.overall_misses::total 1027 # number of overall misses 779system.cpu.dcache.ReadReq_miss_latency::cpu.data 24016000 # number of ReadReq miss cycles 780system.cpu.dcache.ReadReq_miss_latency::total 24016000 # number of ReadReq miss cycles 781system.cpu.dcache.WriteReq_miss_latency::cpu.data 51330451 # number of WriteReq miss cycles 782system.cpu.dcache.WriteReq_miss_latency::total 51330451 # number of WriteReq miss cycles 783system.cpu.dcache.demand_miss_latency::cpu.data 75346451 # number of demand (read+write) miss cycles 784system.cpu.dcache.demand_miss_latency::total 75346451 # number of demand (read+write) miss cycles 785system.cpu.dcache.overall_miss_latency::cpu.data 75346451 # number of overall miss cycles 786system.cpu.dcache.overall_miss_latency::total 75346451 # number of overall miss cycles 787system.cpu.dcache.ReadReq_accesses::cpu.data 3533 # number of ReadReq accesses(hits+misses) 788system.cpu.dcache.ReadReq_accesses::total 3533 # number of ReadReq accesses(hits+misses) |
| 779system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 780system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) | 789system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) 790system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) |
| 781system.cpu.dcache.demand_accesses::cpu.data 5251 # number of demand (read+write) accesses 782system.cpu.dcache.demand_accesses::total 5251 # number of demand (read+write) accesses 783system.cpu.dcache.overall_accesses::cpu.data 5251 # number of overall (read+write) accesses 784system.cpu.dcache.overall_accesses::total 5251 # number of overall (read+write) accesses 785system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085203 # miss rate for ReadReq accesses 786system.cpu.dcache.ReadReq_miss_rate::total 0.085203 # miss rate for ReadReq accesses 787system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412139 # miss rate for WriteReq accesses 788system.cpu.dcache.WriteReq_miss_rate::total 0.412139 # miss rate for WriteReq accesses 789system.cpu.dcache.demand_miss_rate::cpu.data 0.192916 # miss rate for demand accesses 790system.cpu.dcache.demand_miss_rate::total 0.192916 # miss rate for demand accesses 791system.cpu.dcache.overall_miss_rate::cpu.data 0.192916 # miss rate for overall accesses 792system.cpu.dcache.overall_miss_rate::total 0.192916 # miss rate for overall accesses 793system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 84261.666667 # average ReadReq miss latency 794system.cpu.dcache.ReadReq_avg_miss_latency::total 84261.666667 # average ReadReq miss latency 795system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69642.272090 # average WriteReq miss latency 796system.cpu.dcache.WriteReq_avg_miss_latency::total 69642.272090 # average WriteReq miss latency 797system.cpu.dcache.demand_avg_miss_latency::cpu.data 73971.806515 # average overall miss latency 798system.cpu.dcache.demand_avg_miss_latency::total 73971.806515 # average overall miss latency 799system.cpu.dcache.overall_avg_miss_latency::cpu.data 73971.806515 # average overall miss latency 800system.cpu.dcache.overall_avg_miss_latency::total 73971.806515 # average overall miss latency 801system.cpu.dcache.blocked_cycles::no_mshrs 6514 # number of cycles access was blocked | 791system.cpu.dcache.demand_accesses::cpu.data 5263 # number of demand (read+write) accesses 792system.cpu.dcache.demand_accesses::total 5263 # number of demand (read+write) accesses 793system.cpu.dcache.overall_accesses::cpu.data 5263 # number of overall (read+write) accesses 794system.cpu.dcache.overall_accesses::total 5263 # number of overall (read+write) accesses 795system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087461 # miss rate for ReadReq accesses 796system.cpu.dcache.ReadReq_miss_rate::total 0.087461 # miss rate for ReadReq accesses 797system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses 798system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses 799system.cpu.dcache.demand_miss_rate::cpu.data 0.195136 # miss rate for demand accesses 800system.cpu.dcache.demand_miss_rate::total 0.195136 # miss rate for demand accesses 801system.cpu.dcache.overall_miss_rate::cpu.data 0.195136 # miss rate for overall accesses 802system.cpu.dcache.overall_miss_rate::total 0.195136 # miss rate for overall accesses 803system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77721.682848 # average ReadReq miss latency 804system.cpu.dcache.ReadReq_avg_miss_latency::total 77721.682848 # average ReadReq miss latency 805system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71490.878830 # average WriteReq miss latency 806system.cpu.dcache.WriteReq_avg_miss_latency::total 71490.878830 # average WriteReq miss latency 807system.cpu.dcache.demand_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency 808system.cpu.dcache.demand_avg_miss_latency::total 73365.580331 # average overall miss latency 809system.cpu.dcache.overall_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency 810system.cpu.dcache.overall_avg_miss_latency::total 73365.580331 # average overall miss latency 811system.cpu.dcache.blocked_cycles::no_mshrs 5997 # number of cycles access was blocked |
| 802system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 812system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 803system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked | 813system.cpu.dcache.blocked::no_mshrs 108 # number of cycles access was blocked |
| 804system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 814system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 805system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.547445 # average number of cycles each access was blocked | 815system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.527778 # average number of cycles each access was blocked |
| 806system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 816system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 807system.cpu.dcache.ReadReq_mshr_hits::cpu.data 103 # number of ReadReq MSHR hits 808system.cpu.dcache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits 809system.cpu.dcache.WriteReq_mshr_hits::cpu.data 568 # number of WriteReq MSHR hits 810system.cpu.dcache.WriteReq_mshr_hits::total 568 # number of WriteReq MSHR hits 811system.cpu.dcache.demand_mshr_hits::cpu.data 671 # number of demand (read+write) MSHR hits 812system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits 813system.cpu.dcache.overall_mshr_hits::cpu.data 671 # number of overall MSHR hits 814system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits 815system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197 # number of ReadReq MSHR misses 816system.cpu.dcache.ReadReq_mshr_misses::total 197 # number of ReadReq MSHR misses 817system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses 818system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses 819system.cpu.dcache.demand_mshr_misses::cpu.data 342 # number of demand (read+write) MSHR misses 820system.cpu.dcache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses 821system.cpu.dcache.overall_mshr_misses::cpu.data 342 # number of overall MSHR misses 822system.cpu.dcache.overall_mshr_misses::total 342 # number of overall MSHR misses 823system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18892500 # number of ReadReq MSHR miss cycles 824system.cpu.dcache.ReadReq_mshr_miss_latency::total 18892500 # number of ReadReq MSHR miss cycles 825system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12000985 # number of WriteReq MSHR miss cycles 826system.cpu.dcache.WriteReq_mshr_miss_latency::total 12000985 # number of WriteReq MSHR miss cycles 827system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30893485 # number of demand (read+write) MSHR miss cycles 828system.cpu.dcache.demand_mshr_miss_latency::total 30893485 # number of demand (read+write) MSHR miss cycles 829system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30893485 # number of overall MSHR miss cycles 830system.cpu.dcache.overall_mshr_miss_latency::total 30893485 # number of overall MSHR miss cycles 831system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055950 # mshr miss rate for ReadReq accesses 832system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055950 # mshr miss rate for ReadReq accesses 833system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses 834system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses 835system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065130 # mshr miss rate for demand accesses 836system.cpu.dcache.demand_mshr_miss_rate::total 0.065130 # mshr miss rate for demand accesses 837system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065130 # mshr miss rate for overall accesses 838system.cpu.dcache.overall_mshr_miss_rate::total 0.065130 # mshr miss rate for overall accesses 839system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95901.015228 # average ReadReq mshr miss latency 840system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95901.015228 # average ReadReq mshr miss latency 841system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82765.413793 # average WriteReq mshr miss latency 842system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82765.413793 # average WriteReq mshr miss latency 843system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90331.827485 # average overall mshr miss latency 844system.cpu.dcache.demand_avg_mshr_miss_latency::total 90331.827485 # average overall mshr miss latency 845system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90331.827485 # average overall mshr miss latency 846system.cpu.dcache.overall_avg_mshr_miss_latency::total 90331.827485 # average overall mshr miss latency 847system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states | 817system.cpu.dcache.ReadReq_mshr_hits::cpu.data 110 # number of ReadReq MSHR hits 818system.cpu.dcache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits 819system.cpu.dcache.WriteReq_mshr_hits::cpu.data 574 # number of WriteReq MSHR hits 820system.cpu.dcache.WriteReq_mshr_hits::total 574 # number of WriteReq MSHR hits 821system.cpu.dcache.demand_mshr_hits::cpu.data 684 # number of demand (read+write) MSHR hits 822system.cpu.dcache.demand_mshr_hits::total 684 # number of demand (read+write) MSHR hits 823system.cpu.dcache.overall_mshr_hits::cpu.data 684 # number of overall MSHR hits 824system.cpu.dcache.overall_mshr_hits::total 684 # number of overall MSHR hits 825system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses 826system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses 827system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses 828system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses 829system.cpu.dcache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses 830system.cpu.dcache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses 831system.cpu.dcache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses 832system.cpu.dcache.overall_mshr_misses::total 343 # number of overall MSHR misses 833system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17847000 # number of ReadReq MSHR miss cycles 834system.cpu.dcache.ReadReq_mshr_miss_latency::total 17847000 # number of ReadReq MSHR miss cycles 835system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12459487 # number of WriteReq MSHR miss cycles 836system.cpu.dcache.WriteReq_mshr_miss_latency::total 12459487 # number of WriteReq MSHR miss cycles 837system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30306487 # number of demand (read+write) MSHR miss cycles 838system.cpu.dcache.demand_mshr_miss_latency::total 30306487 # number of demand (read+write) MSHR miss cycles 839system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30306487 # number of overall MSHR miss cycles 840system.cpu.dcache.overall_mshr_miss_latency::total 30306487 # number of overall MSHR miss cycles 841system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056326 # mshr miss rate for ReadReq accesses 842system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056326 # mshr miss rate for ReadReq accesses 843system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 844system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 845system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for demand accesses 846system.cpu.dcache.demand_mshr_miss_rate::total 0.065172 # mshr miss rate for demand accesses 847system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for overall accesses 848system.cpu.dcache.overall_mshr_miss_rate::total 0.065172 # mshr miss rate for overall accesses 849system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89683.417085 # average ReadReq mshr miss latency 850system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89683.417085 # average ReadReq mshr miss latency 851system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86524.215278 # average WriteReq mshr miss latency 852system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86524.215278 # average WriteReq mshr miss latency 853system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency 854system.cpu.dcache.demand_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency 855system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency 856system.cpu.dcache.overall_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency 857system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states |
| 848system.cpu.icache.tags.replacements::0 7 # number of replacements 849system.cpu.icache.tags.replacements::1 0 # number of replacements 850system.cpu.icache.tags.replacements::total 7 # number of replacements | 858system.cpu.icache.tags.replacements::0 7 # number of replacements 859system.cpu.icache.tags.replacements::1 0 # number of replacements 860system.cpu.icache.tags.replacements::total 7 # number of replacements |
| 851system.cpu.icache.tags.tagsinuse 314.192674 # Cycle average of tags in use 852system.cpu.icache.tags.total_refs 2931 # Total number of references to valid blocks. 853system.cpu.icache.tags.sampled_refs 627 # Sample count of references to valid blocks. 854system.cpu.icache.tags.avg_refs 4.674641 # Average number of references to valid blocks. | 861system.cpu.icache.tags.tagsinuse 318.055053 # Cycle average of tags in use 862system.cpu.icache.tags.total_refs 2937 # Total number of references to valid blocks. 863system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks. 864system.cpu.icache.tags.avg_refs 4.676752 # Average number of references to valid blocks. |
| 855system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 865system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 856system.cpu.icache.tags.occ_blocks::cpu.inst 314.192674 # Average occupied blocks per requestor 857system.cpu.icache.tags.occ_percent::cpu.inst 0.153414 # Average percentage of cache occupancy 858system.cpu.icache.tags.occ_percent::total 0.153414 # Average percentage of cache occupancy 859system.cpu.icache.tags.occ_task_id_blocks::1024 620 # Occupied blocks per task id 860system.cpu.icache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id 861system.cpu.icache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id 862system.cpu.icache.tags.occ_task_id_percent::1024 0.302734 # Percentage of cache occupancy per task id 863system.cpu.icache.tags.tag_accesses 8297 # Number of tag accesses 864system.cpu.icache.tags.data_accesses 8297 # Number of data accesses 865system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states 866system.cpu.icache.ReadReq_hits::cpu.inst 2931 # number of ReadReq hits 867system.cpu.icache.ReadReq_hits::total 2931 # number of ReadReq hits 868system.cpu.icache.demand_hits::cpu.inst 2931 # number of demand (read+write) hits 869system.cpu.icache.demand_hits::total 2931 # number of demand (read+write) hits 870system.cpu.icache.overall_hits::cpu.inst 2931 # number of overall hits 871system.cpu.icache.overall_hits::total 2931 # number of overall hits 872system.cpu.icache.ReadReq_misses::cpu.inst 904 # number of ReadReq misses 873system.cpu.icache.ReadReq_misses::total 904 # number of ReadReq misses 874system.cpu.icache.demand_misses::cpu.inst 904 # number of demand (read+write) misses 875system.cpu.icache.demand_misses::total 904 # number of demand (read+write) misses 876system.cpu.icache.overall_misses::cpu.inst 904 # number of overall misses 877system.cpu.icache.overall_misses::total 904 # number of overall misses 878system.cpu.icache.ReadReq_miss_latency::cpu.inst 70022492 # number of ReadReq miss cycles 879system.cpu.icache.ReadReq_miss_latency::total 70022492 # number of ReadReq miss cycles 880system.cpu.icache.demand_miss_latency::cpu.inst 70022492 # number of demand (read+write) miss cycles 881system.cpu.icache.demand_miss_latency::total 70022492 # number of demand (read+write) miss cycles 882system.cpu.icache.overall_miss_latency::cpu.inst 70022492 # number of overall miss cycles 883system.cpu.icache.overall_miss_latency::total 70022492 # number of overall miss cycles 884system.cpu.icache.ReadReq_accesses::cpu.inst 3835 # number of ReadReq accesses(hits+misses) 885system.cpu.icache.ReadReq_accesses::total 3835 # number of ReadReq accesses(hits+misses) 886system.cpu.icache.demand_accesses::cpu.inst 3835 # number of demand (read+write) accesses 887system.cpu.icache.demand_accesses::total 3835 # number of demand (read+write) accesses 888system.cpu.icache.overall_accesses::cpu.inst 3835 # number of overall (read+write) accesses 889system.cpu.icache.overall_accesses::total 3835 # number of overall (read+write) accesses 890system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235724 # miss rate for ReadReq accesses 891system.cpu.icache.ReadReq_miss_rate::total 0.235724 # miss rate for ReadReq accesses 892system.cpu.icache.demand_miss_rate::cpu.inst 0.235724 # miss rate for demand accesses 893system.cpu.icache.demand_miss_rate::total 0.235724 # miss rate for demand accesses 894system.cpu.icache.overall_miss_rate::cpu.inst 0.235724 # miss rate for overall accesses 895system.cpu.icache.overall_miss_rate::total 0.235724 # miss rate for overall accesses 896system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77458.508850 # average ReadReq miss latency 897system.cpu.icache.ReadReq_avg_miss_latency::total 77458.508850 # average ReadReq miss latency 898system.cpu.icache.demand_avg_miss_latency::cpu.inst 77458.508850 # average overall miss latency 899system.cpu.icache.demand_avg_miss_latency::total 77458.508850 # average overall miss latency 900system.cpu.icache.overall_avg_miss_latency::cpu.inst 77458.508850 # average overall miss latency 901system.cpu.icache.overall_avg_miss_latency::total 77458.508850 # average overall miss latency 902system.cpu.icache.blocked_cycles::no_mshrs 3069 # number of cycles access was blocked | 866system.cpu.icache.tags.occ_blocks::cpu.inst 318.055053 # Average occupied blocks per requestor 867system.cpu.icache.tags.occ_percent::cpu.inst 0.155300 # Average percentage of cache occupancy 868system.cpu.icache.tags.occ_percent::total 0.155300 # Average percentage of cache occupancy 869system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id 870system.cpu.icache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id 871system.cpu.icache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id 872system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id 873system.cpu.icache.tags.tag_accesses 8292 # Number of tag accesses 874system.cpu.icache.tags.data_accesses 8292 # Number of data accesses 875system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 876system.cpu.icache.ReadReq_hits::cpu.inst 2937 # number of ReadReq hits 877system.cpu.icache.ReadReq_hits::total 2937 # number of ReadReq hits 878system.cpu.icache.demand_hits::cpu.inst 2937 # number of demand (read+write) hits 879system.cpu.icache.demand_hits::total 2937 # number of demand (read+write) hits 880system.cpu.icache.overall_hits::cpu.inst 2937 # number of overall hits 881system.cpu.icache.overall_hits::total 2937 # number of overall hits 882system.cpu.icache.ReadReq_misses::cpu.inst 895 # number of ReadReq misses 883system.cpu.icache.ReadReq_misses::total 895 # number of ReadReq misses 884system.cpu.icache.demand_misses::cpu.inst 895 # number of demand (read+write) misses 885system.cpu.icache.demand_misses::total 895 # number of demand (read+write) misses 886system.cpu.icache.overall_misses::cpu.inst 895 # number of overall misses 887system.cpu.icache.overall_misses::total 895 # number of overall misses 888system.cpu.icache.ReadReq_miss_latency::cpu.inst 72806995 # number of ReadReq miss cycles 889system.cpu.icache.ReadReq_miss_latency::total 72806995 # number of ReadReq miss cycles 890system.cpu.icache.demand_miss_latency::cpu.inst 72806995 # number of demand (read+write) miss cycles 891system.cpu.icache.demand_miss_latency::total 72806995 # number of demand (read+write) miss cycles 892system.cpu.icache.overall_miss_latency::cpu.inst 72806995 # number of overall miss cycles 893system.cpu.icache.overall_miss_latency::total 72806995 # number of overall miss cycles 894system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses) 895system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses) 896system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses 897system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses 898system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses 899system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses 900system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233559 # miss rate for ReadReq accesses 901system.cpu.icache.ReadReq_miss_rate::total 0.233559 # miss rate for ReadReq accesses 902system.cpu.icache.demand_miss_rate::cpu.inst 0.233559 # miss rate for demand accesses 903system.cpu.icache.demand_miss_rate::total 0.233559 # miss rate for demand accesses 904system.cpu.icache.overall_miss_rate::cpu.inst 0.233559 # miss rate for overall accesses 905system.cpu.icache.overall_miss_rate::total 0.233559 # miss rate for overall accesses 906system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81348.597765 # average ReadReq miss latency 907system.cpu.icache.ReadReq_avg_miss_latency::total 81348.597765 # average ReadReq miss latency 908system.cpu.icache.demand_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency 909system.cpu.icache.demand_avg_miss_latency::total 81348.597765 # average overall miss latency 910system.cpu.icache.overall_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency 911system.cpu.icache.overall_avg_miss_latency::total 81348.597765 # average overall miss latency 912system.cpu.icache.blocked_cycles::no_mshrs 3504 # number of cycles access was blocked |
| 903system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 913system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 904system.cpu.icache.blocked::no_mshrs 61 # number of cycles access was blocked | 914system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked |
| 905system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 915system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 906system.cpu.icache.avg_blocked_cycles::no_mshrs 50.311475 # average number of cycles each access was blocked | 916system.cpu.icache.avg_blocked_cycles::no_mshrs 60.413793 # average number of cycles each access was blocked |
| 907system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 908system.cpu.icache.writebacks::writebacks 7 # number of writebacks 909system.cpu.icache.writebacks::total 7 # number of writebacks | 917system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 918system.cpu.icache.writebacks::writebacks 7 # number of writebacks 919system.cpu.icache.writebacks::total 7 # number of writebacks |
| 910system.cpu.icache.ReadReq_mshr_hits::cpu.inst 277 # number of ReadReq MSHR hits 911system.cpu.icache.ReadReq_mshr_hits::total 277 # number of ReadReq MSHR hits 912system.cpu.icache.demand_mshr_hits::cpu.inst 277 # number of demand (read+write) MSHR hits 913system.cpu.icache.demand_mshr_hits::total 277 # number of demand (read+write) MSHR hits 914system.cpu.icache.overall_mshr_hits::cpu.inst 277 # number of overall MSHR hits 915system.cpu.icache.overall_mshr_hits::total 277 # number of overall MSHR hits 916system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses 917system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses 918system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses 919system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses 920system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses 921system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses 922system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52227494 # number of ReadReq MSHR miss cycles 923system.cpu.icache.ReadReq_mshr_miss_latency::total 52227494 # number of ReadReq MSHR miss cycles 924system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52227494 # number of demand (read+write) MSHR miss cycles 925system.cpu.icache.demand_mshr_miss_latency::total 52227494 # number of demand (read+write) MSHR miss cycles 926system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52227494 # number of overall MSHR miss cycles 927system.cpu.icache.overall_mshr_miss_latency::total 52227494 # number of overall MSHR miss cycles 928system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for ReadReq accesses 929system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163494 # mshr miss rate for ReadReq accesses 930system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for demand accesses 931system.cpu.icache.demand_mshr_miss_rate::total 0.163494 # mshr miss rate for demand accesses 932system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for overall accesses 933system.cpu.icache.overall_mshr_miss_rate::total 0.163494 # mshr miss rate for overall accesses 934system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83297.438596 # average ReadReq mshr miss latency 935system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83297.438596 # average ReadReq mshr miss latency 936system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83297.438596 # average overall mshr miss latency 937system.cpu.icache.demand_avg_mshr_miss_latency::total 83297.438596 # average overall mshr miss latency 938system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83297.438596 # average overall mshr miss latency 939system.cpu.icache.overall_avg_mshr_miss_latency::total 83297.438596 # average overall mshr miss latency 940system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states | 920system.cpu.icache.ReadReq_mshr_hits::cpu.inst 267 # number of ReadReq MSHR hits 921system.cpu.icache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits 922system.cpu.icache.demand_mshr_hits::cpu.inst 267 # number of demand (read+write) MSHR hits 923system.cpu.icache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits 924system.cpu.icache.overall_mshr_hits::cpu.inst 267 # number of overall MSHR hits 925system.cpu.icache.overall_mshr_hits::total 267 # number of overall MSHR hits 926system.cpu.icache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses 927system.cpu.icache.ReadReq_mshr_misses::total 628 # number of ReadReq MSHR misses 928system.cpu.icache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses 929system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses 930system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses 931system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses 932system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54757996 # number of ReadReq MSHR miss cycles 933system.cpu.icache.ReadReq_mshr_miss_latency::total 54757996 # number of ReadReq MSHR miss cycles 934system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54757996 # number of demand (read+write) MSHR miss cycles 935system.cpu.icache.demand_mshr_miss_latency::total 54757996 # number of demand (read+write) MSHR miss cycles 936system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54757996 # number of overall MSHR miss cycles 937system.cpu.icache.overall_mshr_miss_latency::total 54757996 # number of overall MSHR miss cycles 938system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for ReadReq accesses 939system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163883 # mshr miss rate for ReadReq accesses 940system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for demand accesses 941system.cpu.icache.demand_mshr_miss_rate::total 0.163883 # mshr miss rate for demand accesses 942system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for overall accesses 943system.cpu.icache.overall_mshr_miss_rate::total 0.163883 # mshr miss rate for overall accesses 944system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87194.261146 # average ReadReq mshr miss latency 945system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87194.261146 # average ReadReq mshr miss latency 946system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency 947system.cpu.icache.demand_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency 948system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency 949system.cpu.icache.overall_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency 950system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states |
| 941system.cpu.l2cache.tags.replacements::0 0 # number of replacements 942system.cpu.l2cache.tags.replacements::1 0 # number of replacements 943system.cpu.l2cache.tags.replacements::total 0 # number of replacements | 951system.cpu.l2cache.tags.replacements::0 0 # number of replacements 952system.cpu.l2cache.tags.replacements::1 0 # number of replacements 953system.cpu.l2cache.tags.replacements::total 0 # number of replacements |
| 944system.cpu.l2cache.tags.tagsinuse 529.119750 # Cycle average of tags in use | 954system.cpu.l2cache.tags.tagsinuse 534.674828 # Cycle average of tags in use |
| 945system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. | 955system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. |
| 946system.cpu.l2cache.tags.sampled_refs 965 # Sample count of references to valid blocks. 947system.cpu.l2cache.tags.avg_refs 0.010363 # Average number of references to valid blocks. | 956system.cpu.l2cache.tags.sampled_refs 967 # Sample count of references to valid blocks. 957system.cpu.l2cache.tags.avg_refs 0.010341 # Average number of references to valid blocks. |
| 948system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 958system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 949system.cpu.l2cache.tags.occ_blocks::cpu.inst 314.628551 # Average occupied blocks per requestor 950system.cpu.l2cache.tags.occ_blocks::cpu.data 214.491199 # Average occupied blocks per requestor 951system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009602 # Average percentage of cache occupancy 952system.cpu.l2cache.tags.occ_percent::cpu.data 0.006546 # Average percentage of cache occupancy 953system.cpu.l2cache.tags.occ_percent::total 0.016147 # Average percentage of cache occupancy 954system.cpu.l2cache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id 955system.cpu.l2cache.tags.age_task_id_blocks_1024::0 319 # Occupied blocks per task id 956system.cpu.l2cache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id 957system.cpu.l2cache.tags.occ_task_id_percent::1024 0.029449 # Percentage of cache occupancy per task id 958system.cpu.l2cache.tags.tag_accesses 8773 # Number of tag accesses 959system.cpu.l2cache.tags.data_accesses 8773 # Number of data accesses 960system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states | 959system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.519168 # Average occupied blocks per requestor 960system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155660 # Average occupied blocks per requestor 961system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009720 # Average percentage of cache occupancy 962system.cpu.l2cache.tags.occ_percent::cpu.data 0.006597 # Average percentage of cache occupancy 963system.cpu.l2cache.tags.occ_percent::total 0.016317 # Average percentage of cache occupancy 964system.cpu.l2cache.tags.occ_task_id_blocks::1024 967 # Occupied blocks per task id 965system.cpu.l2cache.tags.age_task_id_blocks_1024::0 306 # Occupied blocks per task id 966system.cpu.l2cache.tags.age_task_id_blocks_1024::1 661 # Occupied blocks per task id 967system.cpu.l2cache.tags.occ_task_id_percent::1024 0.029510 # Percentage of cache occupancy per task id 968system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses 969system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses 970system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states |
| 961system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits 962system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits 963system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 964system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 965system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 966system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 967system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 968system.cpu.l2cache.overall_hits::total 3 # number of overall hits 969system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses 970system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses | 971system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits 972system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits 973system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 974system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 975system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 976system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 977system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 978system.cpu.l2cache.overall_hits::total 3 # number of overall hits 979system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses 980system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses |
| 971system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 624 # number of ReadCleanReq misses 972system.cpu.l2cache.ReadCleanReq_misses::total 624 # number of ReadCleanReq misses 973system.cpu.l2cache.ReadSharedReq_misses::cpu.data 197 # number of ReadSharedReq misses 974system.cpu.l2cache.ReadSharedReq_misses::total 197 # number of ReadSharedReq misses 975system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses 976system.cpu.l2cache.demand_misses::cpu.data 342 # number of demand (read+write) misses 977system.cpu.l2cache.demand_misses::total 966 # number of demand (read+write) misses 978system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses 979system.cpu.l2cache.overall_misses::cpu.data 342 # number of overall misses 980system.cpu.l2cache.overall_misses::total 966 # number of overall misses 981system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11774500 # number of ReadExReq miss cycles 982system.cpu.l2cache.ReadExReq_miss_latency::total 11774500 # number of ReadExReq miss cycles 983system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 51248500 # number of ReadCleanReq miss cycles 984system.cpu.l2cache.ReadCleanReq_miss_latency::total 51248500 # number of ReadCleanReq miss cycles 985system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18588500 # number of ReadSharedReq miss cycles 986system.cpu.l2cache.ReadSharedReq_miss_latency::total 18588500 # number of ReadSharedReq miss cycles 987system.cpu.l2cache.demand_miss_latency::cpu.inst 51248500 # number of demand (read+write) miss cycles 988system.cpu.l2cache.demand_miss_latency::cpu.data 30363000 # number of demand (read+write) miss cycles 989system.cpu.l2cache.demand_miss_latency::total 81611500 # number of demand (read+write) miss cycles 990system.cpu.l2cache.overall_miss_latency::cpu.inst 51248500 # number of overall miss cycles 991system.cpu.l2cache.overall_miss_latency::cpu.data 30363000 # number of overall miss cycles 992system.cpu.l2cache.overall_miss_latency::total 81611500 # number of overall miss cycles | 981system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 625 # number of ReadCleanReq misses 982system.cpu.l2cache.ReadCleanReq_misses::total 625 # number of ReadCleanReq misses 983system.cpu.l2cache.ReadSharedReq_misses::cpu.data 198 # number of ReadSharedReq misses 984system.cpu.l2cache.ReadSharedReq_misses::total 198 # number of ReadSharedReq misses 985system.cpu.l2cache.demand_misses::cpu.inst 625 # number of demand (read+write) misses 986system.cpu.l2cache.demand_misses::cpu.data 343 # number of demand (read+write) misses 987system.cpu.l2cache.demand_misses::total 968 # number of demand (read+write) misses 988system.cpu.l2cache.overall_misses::cpu.inst 625 # number of overall misses 989system.cpu.l2cache.overall_misses::cpu.data 343 # number of overall misses 990system.cpu.l2cache.overall_misses::total 968 # number of overall misses 991system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12308500 # number of ReadExReq miss cycles 992system.cpu.l2cache.ReadExReq_miss_latency::total 12308500 # number of ReadExReq miss cycles 993system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53778000 # number of ReadCleanReq miss cycles 994system.cpu.l2cache.ReadCleanReq_miss_latency::total 53778000 # number of ReadCleanReq miss cycles 995system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17466000 # number of ReadSharedReq miss cycles 996system.cpu.l2cache.ReadSharedReq_miss_latency::total 17466000 # number of ReadSharedReq miss cycles 997system.cpu.l2cache.demand_miss_latency::cpu.inst 53778000 # number of demand (read+write) miss cycles 998system.cpu.l2cache.demand_miss_latency::cpu.data 29774500 # number of demand (read+write) miss cycles 999system.cpu.l2cache.demand_miss_latency::total 83552500 # number of demand (read+write) miss cycles 1000system.cpu.l2cache.overall_miss_latency::cpu.inst 53778000 # number of overall miss cycles 1001system.cpu.l2cache.overall_miss_latency::cpu.data 29774500 # number of overall miss cycles 1002system.cpu.l2cache.overall_miss_latency::total 83552500 # number of overall miss cycles |
| 993system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) 994system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) 995system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses) 996system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses) | 1003system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses) 1004system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses) 1005system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses) 1006system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses) |
| 997system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 627 # number of ReadCleanReq accesses(hits+misses) 998system.cpu.l2cache.ReadCleanReq_accesses::total 627 # number of ReadCleanReq accesses(hits+misses) 999system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 197 # number of ReadSharedReq accesses(hits+misses) 1000system.cpu.l2cache.ReadSharedReq_accesses::total 197 # number of ReadSharedReq accesses(hits+misses) 1001system.cpu.l2cache.demand_accesses::cpu.inst 627 # number of demand (read+write) accesses 1002system.cpu.l2cache.demand_accesses::cpu.data 342 # number of demand (read+write) accesses 1003system.cpu.l2cache.demand_accesses::total 969 # number of demand (read+write) accesses 1004system.cpu.l2cache.overall_accesses::cpu.inst 627 # number of overall (read+write) accesses 1005system.cpu.l2cache.overall_accesses::cpu.data 342 # number of overall (read+write) accesses 1006system.cpu.l2cache.overall_accesses::total 969 # number of overall (read+write) accesses | 1007system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 628 # number of ReadCleanReq accesses(hits+misses) 1008system.cpu.l2cache.ReadCleanReq_accesses::total 628 # number of ReadCleanReq accesses(hits+misses) 1009system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 198 # number of ReadSharedReq accesses(hits+misses) 1010system.cpu.l2cache.ReadSharedReq_accesses::total 198 # number of ReadSharedReq accesses(hits+misses) 1011system.cpu.l2cache.demand_accesses::cpu.inst 628 # number of demand (read+write) accesses 1012system.cpu.l2cache.demand_accesses::cpu.data 343 # number of demand (read+write) accesses 1013system.cpu.l2cache.demand_accesses::total 971 # number of demand (read+write) accesses 1014system.cpu.l2cache.overall_accesses::cpu.inst 628 # number of overall (read+write) accesses 1015system.cpu.l2cache.overall_accesses::cpu.data 343 # number of overall (read+write) accesses 1016system.cpu.l2cache.overall_accesses::total 971 # number of overall (read+write) accesses |
| 1007system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 1008system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 1017system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 1018system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 1009system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995215 # miss rate for ReadCleanReq accesses 1010system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995215 # miss rate for ReadCleanReq accesses | 1019system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995223 # miss rate for ReadCleanReq accesses 1020system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995223 # miss rate for ReadCleanReq accesses |
| 1011system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 1012system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses | 1021system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 1022system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses |
| 1013system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995215 # miss rate for demand accesses | 1023system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995223 # miss rate for demand accesses |
| 1014system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 1024system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 1015system.cpu.l2cache.demand_miss_rate::total 0.996904 # miss rate for demand accesses 1016system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995215 # miss rate for overall accesses | 1025system.cpu.l2cache.demand_miss_rate::total 0.996910 # miss rate for demand accesses 1026system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995223 # miss rate for overall accesses |
| 1017system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 1027system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 1018system.cpu.l2cache.overall_miss_rate::total 0.996904 # miss rate for overall accesses 1019system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81203.448276 # average ReadExReq miss latency 1020system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81203.448276 # average ReadExReq miss latency 1021system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82129.006410 # average ReadCleanReq miss latency 1022system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82129.006410 # average ReadCleanReq miss latency 1023system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94357.868020 # average ReadSharedReq miss latency 1024system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94357.868020 # average ReadSharedReq miss latency 1025system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82129.006410 # average overall miss latency 1026system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88780.701754 # average overall miss latency 1027system.cpu.l2cache.demand_avg_miss_latency::total 84483.954451 # average overall miss latency 1028system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82129.006410 # average overall miss latency 1029system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88780.701754 # average overall miss latency 1030system.cpu.l2cache.overall_avg_miss_latency::total 84483.954451 # average overall miss latency | 1028system.cpu.l2cache.overall_miss_rate::total 0.996910 # miss rate for overall accesses 1029system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84886.206897 # average ReadExReq miss latency 1030system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84886.206897 # average ReadExReq miss latency 1031system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86044.800000 # average ReadCleanReq miss latency 1032system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86044.800000 # average ReadCleanReq miss latency 1033system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88212.121212 # average ReadSharedReq miss latency 1034system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88212.121212 # average ReadSharedReq miss latency 1035system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency 1036system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency 1037system.cpu.l2cache.demand_avg_miss_latency::total 86314.566116 # average overall miss latency 1038system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency 1039system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency 1040system.cpu.l2cache.overall_avg_miss_latency::total 86314.566116 # average overall miss latency |
| 1031system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1032system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1033system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1034system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1035system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1036system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1037system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses 1038system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses | 1041system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1042system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1043system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1044system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1045system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1046system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1047system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses 1048system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses |
| 1039system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 624 # number of ReadCleanReq MSHR misses 1040system.cpu.l2cache.ReadCleanReq_mshr_misses::total 624 # number of ReadCleanReq MSHR misses 1041system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 197 # number of ReadSharedReq MSHR misses 1042system.cpu.l2cache.ReadSharedReq_mshr_misses::total 197 # number of ReadSharedReq MSHR misses 1043system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses 1044system.cpu.l2cache.demand_mshr_misses::cpu.data 342 # number of demand (read+write) MSHR misses 1045system.cpu.l2cache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses 1046system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses 1047system.cpu.l2cache.overall_mshr_misses::cpu.data 342 # number of overall MSHR misses 1048system.cpu.l2cache.overall_mshr_misses::total 966 # number of overall MSHR misses 1049system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10324500 # number of ReadExReq MSHR miss cycles 1050system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10324500 # number of ReadExReq MSHR miss cycles 1051system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 45008500 # number of ReadCleanReq MSHR miss cycles 1052system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 45008500 # number of ReadCleanReq MSHR miss cycles 1053system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16628500 # number of ReadSharedReq MSHR miss cycles 1054system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16628500 # number of ReadSharedReq MSHR miss cycles 1055system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45008500 # number of demand (read+write) MSHR miss cycles 1056system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26953000 # number of demand (read+write) MSHR miss cycles 1057system.cpu.l2cache.demand_mshr_miss_latency::total 71961500 # number of demand (read+write) MSHR miss cycles 1058system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45008500 # number of overall MSHR miss cycles 1059system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26953000 # number of overall MSHR miss cycles 1060system.cpu.l2cache.overall_mshr_miss_latency::total 71961500 # number of overall MSHR miss cycles | 1049system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 625 # number of ReadCleanReq MSHR misses 1050system.cpu.l2cache.ReadCleanReq_mshr_misses::total 625 # number of ReadCleanReq MSHR misses 1051system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses 1052system.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses 1053system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses 1054system.cpu.l2cache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses 1055system.cpu.l2cache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses 1056system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses 1057system.cpu.l2cache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses 1058system.cpu.l2cache.overall_mshr_misses::total 968 # number of overall MSHR misses 1059system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10858500 # number of ReadExReq MSHR miss cycles 1060system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10858500 # number of ReadExReq MSHR miss cycles 1061system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47528000 # number of ReadCleanReq MSHR miss cycles 1062system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47528000 # number of ReadCleanReq MSHR miss cycles 1063system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15496000 # number of ReadSharedReq MSHR miss cycles 1064system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15496000 # number of ReadSharedReq MSHR miss cycles 1065system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47528000 # number of demand (read+write) MSHR miss cycles 1066system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26354500 # number of demand (read+write) MSHR miss cycles 1067system.cpu.l2cache.demand_mshr_miss_latency::total 73882500 # number of demand (read+write) MSHR miss cycles 1068system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47528000 # number of overall MSHR miss cycles 1069system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26354500 # number of overall MSHR miss cycles 1070system.cpu.l2cache.overall_mshr_miss_latency::total 73882500 # number of overall MSHR miss cycles |
| 1061system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1062system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 1071system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 1072system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 1063system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for ReadCleanReq accesses 1064system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995215 # mshr miss rate for ReadCleanReq accesses | 1073system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for ReadCleanReq accesses 1074system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995223 # mshr miss rate for ReadCleanReq accesses |
| 1065system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 1066system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses | 1075system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 1076system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses |
| 1067system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for demand accesses | 1077system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for demand accesses |
| 1068system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 1078system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 1069system.cpu.l2cache.demand_mshr_miss_rate::total 0.996904 # mshr miss rate for demand accesses 1070system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for overall accesses | 1079system.cpu.l2cache.demand_mshr_miss_rate::total 0.996910 # mshr miss rate for demand accesses 1080system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for overall accesses |
| 1071system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 1081system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 1072system.cpu.l2cache.overall_mshr_miss_rate::total 0.996904 # mshr miss rate for overall accesses 1073system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71203.448276 # average ReadExReq mshr miss latency 1074system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71203.448276 # average ReadExReq mshr miss latency 1075system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72129.006410 # average ReadCleanReq mshr miss latency 1076system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72129.006410 # average ReadCleanReq mshr miss latency 1077system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84408.629442 # average ReadSharedReq mshr miss latency 1078system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84408.629442 # average ReadSharedReq mshr miss latency 1079system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72129.006410 # average overall mshr miss latency 1080system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78809.941520 # average overall mshr miss latency 1081system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74494.306418 # average overall mshr miss latency 1082system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72129.006410 # average overall mshr miss latency 1083system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78809.941520 # average overall mshr miss latency 1084system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74494.306418 # average overall mshr miss latency 1085system.cpu.toL2Bus.snoop_filter.tot_requests 976 # Total number of requests made to the snoop filter. | 1082system.cpu.l2cache.overall_mshr_miss_rate::total 0.996910 # mshr miss rate for overall accesses 1083system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74886.206897 # average ReadExReq mshr miss latency 1084system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74886.206897 # average ReadExReq mshr miss latency 1085system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76044.800000 # average ReadCleanReq mshr miss latency 1086system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76044.800000 # average ReadCleanReq mshr miss latency 1087system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78262.626263 # average ReadSharedReq mshr miss latency 1088system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78262.626263 # average ReadSharedReq mshr miss latency 1089system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency 1090system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency 1091system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency 1092system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency 1093system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency 1094system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency 1095system.cpu.toL2Bus.snoop_filter.tot_requests 978 # Total number of requests made to the snoop filter. |
| 1086system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1087system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1088system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1089system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1090system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1096system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1097system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1098system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1099system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1100system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1091system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states 1092system.cpu.toL2Bus.trans_dist::ReadResp 823 # Transaction distribution | 1101system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 1102system.cpu.toL2Bus.trans_dist::ReadResp 825 # Transaction distribution |
| 1093system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution 1094system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution 1095system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution | 1103system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution 1104system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution 1105system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution |
| 1096system.cpu.toL2Bus.trans_dist::ReadCleanReq 627 # Transaction distribution 1097system.cpu.toL2Bus.trans_dist::ReadSharedReq 197 # Transaction distribution 1098system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1261 # Packet count per connected master and slave (bytes) 1099system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 683 # Packet count per connected master and slave (bytes) 1100system.cpu.toL2Bus.pkt_count::total 1944 # Packet count per connected master and slave (bytes) 1101system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40576 # Cumulative packet size per connected master and slave (bytes) 1102system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21824 # Cumulative packet size per connected master and slave (bytes) 1103system.cpu.toL2Bus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes) | 1106system.cpu.toL2Bus.trans_dist::ReadCleanReq 628 # Transaction distribution 1107system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution 1108system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1263 # Packet count per connected master and slave (bytes) 1109system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 685 # Packet count per connected master and slave (bytes) 1110system.cpu.toL2Bus.pkt_count::total 1948 # Packet count per connected master and slave (bytes) 1111system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40640 # Cumulative packet size per connected master and slave (bytes) 1112system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21888 # Cumulative packet size per connected master and slave (bytes) 1113system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes) |
| 1104system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1105system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) | 1114system.cpu.toL2Bus.snoops 0 # Total snoops (count) 1115system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1106system.cpu.toL2Bus.snoop_fanout::samples 969 # Request fanout histogram 1107system.cpu.toL2Bus.snoop_fanout::mean 0.002064 # Request fanout histogram 1108system.cpu.toL2Bus.snoop_fanout::stdev 0.045408 # Request fanout histogram | 1116system.cpu.toL2Bus.snoop_fanout::samples 971 # Request fanout histogram 1117system.cpu.toL2Bus.snoop_fanout::mean 0.002060 # Request fanout histogram 1118system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram |
| 1109system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1119system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1110system.cpu.toL2Bus.snoop_fanout::0 967 99.79% 99.79% # Request fanout histogram | 1120system.cpu.toL2Bus.snoop_fanout::0 969 99.79% 99.79% # Request fanout histogram |
| 1111system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram 1112system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1113system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1114system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1115system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 1121system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram 1122system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 1123system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1124system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1125system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| 1116system.cpu.toL2Bus.snoop_fanout::total 969 # Request fanout histogram 1117system.cpu.toL2Bus.reqLayer0.occupancy 495000 # Layer occupancy (ticks) | 1126system.cpu.toL2Bus.snoop_fanout::total 971 # Request fanout histogram 1127system.cpu.toL2Bus.reqLayer0.occupancy 496000 # Layer occupancy (ticks) |
| 1118system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) | 1128system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) |
| 1119system.cpu.toL2Bus.respLayer0.occupancy 940500 # Layer occupancy (ticks) 1120system.cpu.toL2Bus.respLayer0.utilization 3.7 # Layer utilization (%) 1121system.cpu.toL2Bus.respLayer1.occupancy 511500 # Layer occupancy (ticks) 1122system.cpu.toL2Bus.respLayer1.utilization 2.0 # Layer utilization (%) 1123system.membus.snoop_filter.tot_requests 966 # Total number of requests made to the snoop filter. | 1129system.cpu.toL2Bus.respLayer0.occupancy 942000 # Layer occupancy (ticks) 1130system.cpu.toL2Bus.respLayer0.utilization 3.5 # Layer utilization (%) 1131system.cpu.toL2Bus.respLayer1.occupancy 513000 # Layer occupancy (ticks) 1132system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) 1133system.membus.snoop_filter.tot_requests 968 # Total number of requests made to the snoop filter. |
| 1124system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1125system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1126system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1127system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1128system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1134system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1135system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1136system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1137system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1138system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1129system.membus.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states 1130system.membus.trans_dist::ReadResp 820 # Transaction distribution | 1139system.membus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states 1140system.membus.trans_dist::ReadResp 822 # Transaction distribution |
| 1131system.membus.trans_dist::ReadExReq 145 # Transaction distribution 1132system.membus.trans_dist::ReadExResp 145 # Transaction distribution | 1141system.membus.trans_dist::ReadExReq 145 # Transaction distribution 1142system.membus.trans_dist::ReadExResp 145 # Transaction distribution |
| 1133system.membus.trans_dist::ReadSharedReq 821 # Transaction distribution 1134system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1931 # Packet count per connected master and slave (bytes) 1135system.membus.pkt_count::total 1931 # Packet count per connected master and slave (bytes) 1136system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61760 # Cumulative packet size per connected master and slave (bytes) 1137system.membus.pkt_size::total 61760 # Cumulative packet size per connected master and slave (bytes) | 1143system.membus.trans_dist::ReadSharedReq 823 # Transaction distribution 1144system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1935 # Packet count per connected master and slave (bytes) 1145system.membus.pkt_count::total 1935 # Packet count per connected master and slave (bytes) 1146system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61888 # Cumulative packet size per connected master and slave (bytes) 1147system.membus.pkt_size::total 61888 # Cumulative packet size per connected master and slave (bytes) |
| 1138system.membus.snoops 0 # Total snoops (count) 1139system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1148system.membus.snoops 0 # Total snoops (count) 1149system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1140system.membus.snoop_fanout::samples 966 # Request fanout histogram | 1150system.membus.snoop_fanout::samples 968 # Request fanout histogram |
| 1141system.membus.snoop_fanout::mean 0 # Request fanout histogram 1142system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1143system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1151system.membus.snoop_fanout::mean 0 # Request fanout histogram 1152system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1153system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1144system.membus.snoop_fanout::0 966 100.00% 100.00% # Request fanout histogram | 1154system.membus.snoop_fanout::0 968 100.00% 100.00% # Request fanout histogram |
| 1145system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1146system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1147system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1148system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1155system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1156system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1157system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1158system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1149system.membus.snoop_fanout::total 966 # Request fanout histogram 1150system.membus.reqLayer0.occupancy 1177000 # Layer occupancy (ticks) 1151system.membus.reqLayer0.utilization 4.6 # Layer utilization (%) 1152system.membus.respLayer1.occupancy 5133750 # Layer occupancy (ticks) 1153system.membus.respLayer1.utilization 20.0 # Layer utilization (%) | 1159system.membus.snoop_fanout::total 968 # Request fanout histogram 1160system.membus.reqLayer0.occupancy 1179500 # Layer occupancy (ticks) 1161system.membus.reqLayer0.utilization 4.4 # Layer utilization (%) 1162system.membus.respLayer1.occupancy 5127250 # Layer occupancy (ticks) 1163system.membus.respLayer1.utilization 19.2 # Layer utilization (%) |
| 1154 1155---------- End Simulation Statistics ---------- | 1164 1165---------- End Simulation Statistics ---------- |