| stats.txt (11440:76b5639162af) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25580500 # Number of ticks simulated 5final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25580500 # Number of ticks simulated 5final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 50796 # Simulator instruction rate (inst/s) 8host_op_rate 50792 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 98611945 # Simulator tick rate (ticks/s) 10host_mem_usage 229596 # Number of bytes of host memory used 11host_seconds 0.25 # Real time elapsed on the host | 7host_inst_rate 85448 # Simulator instruction rate (inst/s) 8host_op_rate 85436 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 171120344 # Simulator tick rate (ticks/s) 10host_mem_usage 253996 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host |
| 12sim_insts 12770 # Number of instructions simulated 13sim_ops 12770 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39680 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 21824 # Number of bytes read from this memory 18system.physmem.bytes_read::total 61504 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39680 # Number of instructions bytes read from this memory --- 774 unchanged lines hidden (view full) --- 794system.cpu.dcache.overall_avg_miss_latency::cpu.data 74970.261128 # average overall miss latency 795system.cpu.dcache.overall_avg_miss_latency::total 74970.261128 # average overall miss latency 796system.cpu.dcache.blocked_cycles::no_mshrs 5977 # number of cycles access was blocked 797system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 798system.cpu.dcache.blocked::no_mshrs 130 # number of cycles access was blocked 799system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 800system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.976923 # average number of cycles each access was blocked 801system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 12770 # Number of instructions simulated 13sim_ops 12770 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39680 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 21824 # Number of bytes read from this memory 18system.physmem.bytes_read::total 61504 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39680 # Number of instructions bytes read from this memory --- 774 unchanged lines hidden (view full) --- 794system.cpu.dcache.overall_avg_miss_latency::cpu.data 74970.261128 # average overall miss latency 795system.cpu.dcache.overall_avg_miss_latency::total 74970.261128 # average overall miss latency 796system.cpu.dcache.blocked_cycles::no_mshrs 5977 # number of cycles access was blocked 797system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 798system.cpu.dcache.blocked::no_mshrs 130 # number of cycles access was blocked 799system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 800system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.976923 # average number of cycles each access was blocked 801system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 802system.cpu.dcache.fast_writes 0 # number of fast writes performed 803system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 804system.cpu.dcache.ReadReq_mshr_hits::cpu.data 103 # number of ReadReq MSHR hits 805system.cpu.dcache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits 806system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits 807system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits 808system.cpu.dcache.demand_mshr_hits::cpu.data 669 # number of demand (read+write) MSHR hits 809system.cpu.dcache.demand_mshr_hits::total 669 # number of demand (read+write) MSHR hits 810system.cpu.dcache.overall_mshr_hits::cpu.data 669 # number of overall MSHR hits 811system.cpu.dcache.overall_mshr_hits::total 669 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 836system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87926.020408 # average ReadReq mshr miss latency 837system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87926.020408 # average ReadReq mshr miss latency 838system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87849.219178 # average WriteReq mshr miss latency 839system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87849.219178 # average WriteReq mshr miss latency 840system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency 841system.cpu.dcache.demand_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency 842system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency 843system.cpu.dcache.overall_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency | 802system.cpu.dcache.ReadReq_mshr_hits::cpu.data 103 # number of ReadReq MSHR hits 803system.cpu.dcache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits 804system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits 805system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits 806system.cpu.dcache.demand_mshr_hits::cpu.data 669 # number of demand (read+write) MSHR hits 807system.cpu.dcache.demand_mshr_hits::total 669 # number of demand (read+write) MSHR hits 808system.cpu.dcache.overall_mshr_hits::cpu.data 669 # number of overall MSHR hits 809system.cpu.dcache.overall_mshr_hits::total 669 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 834system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87926.020408 # average ReadReq mshr miss latency 835system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87926.020408 # average ReadReq mshr miss latency 836system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87849.219178 # average WriteReq mshr miss latency 837system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87849.219178 # average WriteReq mshr miss latency 838system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency 839system.cpu.dcache.demand_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency 840system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency 841system.cpu.dcache.overall_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency |
| 844system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 845system.cpu.icache.tags.replacements::0 7 # number of replacements 846system.cpu.icache.tags.replacements::1 0 # number of replacements 847system.cpu.icache.tags.replacements::total 7 # number of replacements 848system.cpu.icache.tags.tagsinuse 317.276824 # Cycle average of tags in use 849system.cpu.icache.tags.total_refs 2916 # Total number of references to valid blocks. 850system.cpu.icache.tags.sampled_refs 623 # Sample count of references to valid blocks. 851system.cpu.icache.tags.avg_refs 4.680578 # Average number of references to valid blocks. 852system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. --- 43 unchanged lines hidden (view full) --- 896system.cpu.icache.overall_avg_miss_latency::cpu.inst 77449.053156 # average overall miss latency 897system.cpu.icache.overall_avg_miss_latency::total 77449.053156 # average overall miss latency 898system.cpu.icache.blocked_cycles::no_mshrs 3083 # number of cycles access was blocked 899system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 900system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked 901system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 902system.cpu.icache.avg_blocked_cycles::no_mshrs 56.054545 # average number of cycles each access was blocked 903system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 842system.cpu.icache.tags.replacements::0 7 # number of replacements 843system.cpu.icache.tags.replacements::1 0 # number of replacements 844system.cpu.icache.tags.replacements::total 7 # number of replacements 845system.cpu.icache.tags.tagsinuse 317.276824 # Cycle average of tags in use 846system.cpu.icache.tags.total_refs 2916 # Total number of references to valid blocks. 847system.cpu.icache.tags.sampled_refs 623 # Sample count of references to valid blocks. 848system.cpu.icache.tags.avg_refs 4.680578 # Average number of references to valid blocks. 849system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. --- 43 unchanged lines hidden (view full) --- 893system.cpu.icache.overall_avg_miss_latency::cpu.inst 77449.053156 # average overall miss latency 894system.cpu.icache.overall_avg_miss_latency::total 77449.053156 # average overall miss latency 895system.cpu.icache.blocked_cycles::no_mshrs 3083 # number of cycles access was blocked 896system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 897system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked 898system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 899system.cpu.icache.avg_blocked_cycles::no_mshrs 56.054545 # average number of cycles each access was blocked 900system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 904system.cpu.icache.fast_writes 0 # number of fast writes performed 905system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 906system.cpu.icache.writebacks::writebacks 7 # number of writebacks 907system.cpu.icache.writebacks::total 7 # number of writebacks 908system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits 909system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits 910system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits 911system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits 912system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits 913system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 930system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163132 # mshr miss rate for overall accesses 931system.cpu.icache.overall_mshr_miss_rate::total 0.163132 # mshr miss rate for overall accesses 932system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80906.894061 # average ReadReq mshr miss latency 933system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80906.894061 # average ReadReq mshr miss latency 934system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency 935system.cpu.icache.demand_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency 936system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency 937system.cpu.icache.overall_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency | 901system.cpu.icache.writebacks::writebacks 7 # number of writebacks 902system.cpu.icache.writebacks::total 7 # number of writebacks 903system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits 904system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits 905system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits 906system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits 907system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits 908system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 925system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163132 # mshr miss rate for overall accesses 926system.cpu.icache.overall_mshr_miss_rate::total 0.163132 # mshr miss rate for overall accesses 927system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80906.894061 # average ReadReq mshr miss latency 928system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80906.894061 # average ReadReq mshr miss latency 929system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency 930system.cpu.icache.demand_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency 931system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency 932system.cpu.icache.overall_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency |
| 938system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 939system.cpu.l2cache.tags.replacements::0 0 # number of replacements 940system.cpu.l2cache.tags.replacements::1 0 # number of replacements 941system.cpu.l2cache.tags.replacements::total 0 # number of replacements 942system.cpu.l2cache.tags.tagsinuse 438.773475 # Cycle average of tags in use 943system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. 944system.cpu.l2cache.tags.sampled_refs 815 # Sample count of references to valid blocks. 945system.cpu.l2cache.tags.avg_refs 0.012270 # Average number of references to valid blocks. 946system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. --- 79 unchanged lines hidden (view full) --- 1026system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86343.567251 # average overall miss latency 1027system.cpu.l2cache.overall_avg_miss_latency::total 82080.561331 # average overall miss latency 1028system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1029system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1030system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1031system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1032system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1033system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 933system.cpu.l2cache.tags.replacements::0 0 # number of replacements 934system.cpu.l2cache.tags.replacements::1 0 # number of replacements 935system.cpu.l2cache.tags.replacements::total 0 # number of replacements 936system.cpu.l2cache.tags.tagsinuse 438.773475 # Cycle average of tags in use 937system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks. 938system.cpu.l2cache.tags.sampled_refs 815 # Sample count of references to valid blocks. 939system.cpu.l2cache.tags.avg_refs 0.012270 # Average number of references to valid blocks. 940system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. --- 79 unchanged lines hidden (view full) --- 1020system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86343.567251 # average overall miss latency 1021system.cpu.l2cache.overall_avg_miss_latency::total 82080.561331 # average overall miss latency 1022system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1023system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1024system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1025system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1026system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1027system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1034system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1035system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1036system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 1037system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 1038system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 620 # number of ReadCleanReq MSHR misses 1039system.cpu.l2cache.ReadCleanReq_mshr_misses::total 620 # number of ReadCleanReq MSHR misses 1040system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 196 # number of ReadSharedReq MSHR misses 1041system.cpu.l2cache.ReadSharedReq_mshr_misses::total 196 # number of ReadSharedReq MSHR misses 1042system.cpu.l2cache.demand_mshr_misses::cpu.inst 620 # number of demand (read+write) MSHR misses 1043system.cpu.l2cache.demand_mshr_misses::cpu.data 342 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 1076system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76433.673469 # average ReadSharedReq mshr miss latency 1077system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76433.673469 # average ReadSharedReq mshr miss latency 1078system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency 1079system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency 1080system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency 1081system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency 1082system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency 1083system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency | 1028system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses 1029system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses 1030system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 620 # number of ReadCleanReq MSHR misses 1031system.cpu.l2cache.ReadCleanReq_mshr_misses::total 620 # number of ReadCleanReq MSHR misses 1032system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 196 # number of ReadSharedReq MSHR misses 1033system.cpu.l2cache.ReadSharedReq_mshr_misses::total 196 # number of ReadSharedReq MSHR misses 1034system.cpu.l2cache.demand_mshr_misses::cpu.inst 620 # number of demand (read+write) MSHR misses 1035system.cpu.l2cache.demand_mshr_misses::cpu.data 342 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 1068system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76433.673469 # average ReadSharedReq mshr miss latency 1069system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76433.673469 # average ReadSharedReq mshr miss latency 1070system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency 1071system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency 1072system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency 1073system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency 1074system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency 1075system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency |
| 1084system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1085system.cpu.toL2Bus.snoop_filter.tot_requests 972 # Total number of requests made to the snoop filter. 1086system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1087system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1088system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1089system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1090system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1091system.cpu.toL2Bus.trans_dist::ReadResp 818 # Transaction distribution 1092system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution --- 53 unchanged lines hidden --- | 1076system.cpu.toL2Bus.snoop_filter.tot_requests 972 # Total number of requests made to the snoop filter. 1077system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1078system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1079system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1080system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1081system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1082system.cpu.toL2Bus.trans_dist::ReadResp 818 # Transaction distribution 1083system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution --- 53 unchanged lines hidden --- |