7,11c7,11
< host_inst_rate 139098 # Simulator instruction rate (inst/s)
< host_op_rate 139080 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 290337480 # Simulator tick rate (ticks/s)
< host_mem_usage 255644 # Number of bytes of host memory used
< host_seconds 0.09 # Real time elapsed on the host
---
> host_inst_rate 29979 # Simulator instruction rate (inst/s)
> host_op_rate 29977 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 62584510 # Simulator tick rate (ticks/s)
> host_mem_usage 237004 # Number of bytes of host memory used
> host_seconds 0.43 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 15942250 # Total ticks spent queuing
< system.physmem.totMemAccLat 34092250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 15941250 # Total ticks spent queuing
> system.physmem.totMemAccLat 34091250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 16469.27 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16468.23 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 35219.27 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 35218.23 # Average memory access latency per DRAM burst
231c231
< system.physmem_0.actBackEnergy 6127500 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 6126930 # Energy for active background per rank (pJ)
233c233
< system.physmem_0.actPowerDownEnergy 5972460 # Energy for active power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 5973030 # Energy for active power-down per rank (pJ)
250c250
< system.physmem_1.actBackEnergy 4612440 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 4611870 # Energy for active background per rank (pJ)
252c252
< system.physmem_1.actPowerDownEnergy 6908970 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 6909540 # Energy for active power-down per rank (pJ)
283c283
< system.cpu.dtb.read_hits 4130 # DTB read hits
---
> system.cpu.dtb.read_hits 4131 # DTB read hits
286c286
< system.cpu.dtb.read_accesses 4206 # DTB read accesses
---
> system.cpu.dtb.read_accesses 4207 # DTB read accesses
291c291
< system.cpu.dtb.data_hits 6141 # DTB hits
---
> system.cpu.dtb.data_hits 6142 # DTB hits
294c294
< system.cpu.dtb.data_accesses 6265 # DTB accesses
---
> system.cpu.dtb.data_accesses 6266 # DTB accesses
326,328c326,328
< system.cpu.fetch.rateDist::samples 26300 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.059658 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.449516 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 26305 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.059456 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.449327 # Number of instructions fetched each cycle (Total)
330c330
< system.cpu.fetch.rateDist::0 21275 80.89% 80.89% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 21280 80.90% 80.90% # Number of instructions fetched each cycle (Total)
333c333
< system.cpu.fetch.rateDist::3 446 1.70% 85.99% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::3 446 1.70% 86.00% # Number of instructions fetched each cycle (Total)
342c342
< system.cpu.fetch.rateDist::total 26300 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 26305 # Number of instructions fetched each cycle (Total)
345,346c345,346
< system.cpu.decode.IdleCycles 36528 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 10375 # Number of cycles decode is blocked
---
> system.cpu.decode.IdleCycles 36539 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 10373 # Number of cycles decode is blocked
348c348
< system.cpu.decode.UnblockCycles 495 # Number of cycles decode is unblocking
---
> system.cpu.decode.UnblockCycles 496 # Number of cycles decode is unblocking
352c352
< system.cpu.decode.DecodedInsts 24583 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 24588 # Number of instructions handled by decode
355c355
< system.cpu.rename.IdleCycles 36872 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 36883 # Number of cycles rename is idle
358c358
< system.cpu.rename.RunCycles 4116 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 4115 # Number of cycles rename is running
362,363c362,363
< system.cpu.rename.IQFullEvents 223 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 328 # Number of times rename has blocked due to LQ full
---
> system.cpu.rename.IQFullEvents 222 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 329 # Number of times rename has blocked due to LQ full
373c373
< system.cpu.rename.skidInsts 1621 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 1617 # count of insts added to the skid buffer
384c384
< system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 19298 # Number of instructions issued
387c387
< system.cpu.iq.iqSquashedOperandsExamined 4753 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedOperandsExamined 4750 # Number of squashed operands that are examined and possibly removed from graph
389,391c389,391
< system.cpu.iq.issued_per_cycle::samples 26300 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.733688 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.450617 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 26305 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.733625 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.450843 # Number of insts issued each cycle
393,398c393,398
< system.cpu.iq.issued_per_cycle::0 18970 72.13% 72.13% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 2362 8.98% 81.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1626 6.18% 87.29% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 1294 4.92% 92.21% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 1061 4.03% 96.25% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 563 2.14% 98.39% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 18975 72.13% 72.13% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 2364 8.99% 81.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1624 6.17% 87.30% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 1293 4.92% 92.21% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 1059 4.03% 96.24% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 566 2.15% 98.39% # Number of insts issued each cycle
405c405
< system.cpu.iq.issued_per_cycle::total 26300 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 26305 # Number of insts issued each cycle
407,441c407,441
< system.cpu.iq.fu_full::IntAlu 29 9.67% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 191 63.67% 73.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 77 25.67% 99.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemWrite 3 1.00% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 29 9.60% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 193 63.91% 73.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 77 25.50% 99.01% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.01% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemWrite 3 0.99% 100.00% # attempts to use FU when none available
445,475c445,475
< system.cpu.iq.FU_type_0::IntAlu 5884 66.04% 66.06% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.07% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 5886 66.05% 66.07% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.08% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued
482c482
< system.cpu.iq.FU_type_0::total 8910 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 8912 # Type of FU issued
522,524c522,524
< system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued
< system.cpu.iq.rate 0.361863 # Inst issue rate
< system.cpu.iq.fu_busy_cnt::0 152 # FU busy when requested
---
> system.cpu.iq.FU_type::total 19298 0.00% 0.00% # Type of FU issued
> system.cpu.iq.rate 0.361901 # Inst issue rate
> system.cpu.iq.fu_busy_cnt::0 154 # FU busy when requested
526,530c526,530
< system.cpu.iq.fu_busy_cnt::total 300 # FU busy when requested
< system.cpu.iq.fu_busy_rate::0 0.007877 # FU busy rate (busy events/executed inst)
< system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst)
< system.cpu.iq.fu_busy_rate::total 0.015547 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 65200 # Number of integer instruction queue reads
---
> system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested
> system.cpu.iq.fu_busy_rate::0 0.007980 # FU busy rate (busy events/executed inst)
> system.cpu.iq.fu_busy_rate::1 0.007669 # FU busy rate (busy events/executed inst)
> system.cpu.iq.fu_busy_rate::total 0.015649 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 65211 # Number of integer instruction queue reads
532c532
< system.cpu.iq.int_inst_queue_wakeup_accesses 17504 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_wakeup_accesses 17509 # Number of integer instruction queue wakeup accesses
536c536
< system.cpu.iq.int_alu_accesses 19569 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 19573 # Number of integer alu accesses
573,574c573,574
< system.cpu.iew.iewExecutedInsts 18585 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts::0 1945 # Number of load instructions executed
---
> system.cpu.iew.iewExecutedInsts 18590 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts::0 1946 # Number of load instructions executed
576,577c576,577
< system.cpu.iew.iewExecLoadInsts::total 4209 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 711 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecLoadInsts::total 4210 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute
584c584
< system.cpu.iew.exec_refs::0 2942 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs::0 2943 # number of memory reference insts executed
586c586
< system.cpu.iew.exec_refs::total 6280 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed
593,594c593,594
< system.cpu.iew.exec_rate 0.348530 # Inst execution rate
< system.cpu.iew.wb_sent::0 8281 # cumulative count of insts sent to commit
---
> system.cpu.iew.exec_rate 0.348624 # Inst execution rate
> system.cpu.iew.wb_sent::0 8287 # cumulative count of insts sent to commit
596,597c596,597
< system.cpu.iew.wb_sent::total 17777 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count::0 8197 # cumulative count of insts written-back
---
> system.cpu.iew.wb_sent::total 17783 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count::0 8202 # cumulative count of insts written-back
599,606c599,606
< system.cpu.iew.wb_count::total 17524 # cumulative count of insts written-back
< system.cpu.iew.wb_producers::0 4340 # num instructions producing a value
< system.cpu.iew.wb_producers::1 4919 # num instructions producing a value
< system.cpu.iew.wb_producers::total 9259 # num instructions producing a value
< system.cpu.iew.wb_consumers::0 5879 # num instructions consuming a value
< system.cpu.iew.wb_consumers::1 6619 # num instructions consuming a value
< system.cpu.iew.wb_consumers::total 12498 # num instructions consuming a value
< system.cpu.iew.wb_rate::0 0.153721 # insts written-back per cycle
---
> system.cpu.iew.wb_count::total 17529 # cumulative count of insts written-back
> system.cpu.iew.wb_producers::0 4343 # num instructions producing a value
> system.cpu.iew.wb_producers::1 4920 # num instructions producing a value
> system.cpu.iew.wb_producers::total 9263 # num instructions producing a value
> system.cpu.iew.wb_consumers::0 5887 # num instructions consuming a value
> system.cpu.iew.wb_consumers::1 6620 # num instructions consuming a value
> system.cpu.iew.wb_consumers::total 12507 # num instructions consuming a value
> system.cpu.iew.wb_rate::0 0.153814 # insts written-back per cycle
608,611c608,611
< system.cpu.iew.wb_rate::total 0.328633 # insts written-back per cycle
< system.cpu.iew.wb_fanout::0 0.738221 # average fanout of values written-back
< system.cpu.iew.wb_fanout::1 0.743164 # average fanout of values written-back
< system.cpu.iew.wb_fanout::total 0.740839 # average fanout of values written-back
---
> system.cpu.iew.wb_rate::total 0.328726 # insts written-back per cycle
> system.cpu.iew.wb_fanout::0 0.737727 # average fanout of values written-back
> system.cpu.iew.wb_fanout::1 0.743202 # average fanout of values written-back
> system.cpu.iew.wb_fanout::total 0.740625 # average fanout of values written-back
615,617c615,617
< system.cpu.commit.committed_per_cycle::samples 26282 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.487178 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.404713 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 26287 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.487085 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.404867 # Number of insts commited each cycle
619,620c619,620
< system.cpu.commit.committed_per_cycle::0 21298 81.04% 81.04% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 2499 9.51% 90.54% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 21303 81.04% 81.04% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 2500 9.51% 90.55% # Number of insts commited each cycle
622c622
< system.cpu.commit.committed_per_cycle::3 403 1.53% 95.60% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::3 402 1.53% 95.60% # Number of insts commited each cycle
624,625c624,625
< system.cpu.commit.committed_per_cycle::5 154 0.59% 97.13% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 215 0.82% 97.95% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::5 154 0.59% 97.14% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 214 0.81% 97.95% # Number of insts commited each cycle
627c627
< system.cpu.commit.committed_per_cycle::8 422 1.61% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::8 423 1.61% 100.00% # Number of insts commited each cycle
631c631
< system.cpu.commit.committed_per_cycle::total 26282 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 26287 # Number of insts commited each cycle
741,742c741,742
< system.cpu.commit.bw_lim_events 422 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 113054 # The number of ROB reads
---
> system.cpu.commit.bw_lim_events 423 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 113065 # The number of ROB reads
745c745
< system.cpu.idleCycles 27024 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 27019 # Total number of cycles that the CPU has spent unscheduled due to idling
758,759c758,759
< system.cpu.int_regfile_reads 23475 # number of integer regfile reads
< system.cpu.int_regfile_writes 13132 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 23483 # number of integer regfile reads
> system.cpu.int_regfile_writes 13138 # number of integer regfile writes
768,769c768,769
< system.cpu.dcache.tags.tagsinuse 216.020971 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 4236 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 216.020896 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 4237 # Total number of references to valid blocks.
771c771
< system.cpu.dcache.tags.avg_refs 12.385965 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 12.388889 # Average number of references to valid blocks.
773c773
< system.cpu.dcache.tags.occ_blocks::cpu.data 216.020971 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 216.020896 # Average occupied blocks per requestor
780,781c780,781
< system.cpu.dcache.tags.tag_accesses 10868 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 10868 # Number of data accesses
---
> system.cpu.dcache.tags.tag_accesses 10870 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 10870 # Number of data accesses
783,784c783,784
< system.cpu.dcache.ReadReq_hits::cpu.data 3224 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 3224 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 3225 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 3225 # number of ReadReq hits
787,790c787,790
< system.cpu.dcache.demand_hits::cpu.data 4236 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 4236 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 4236 # number of overall hits
< system.cpu.dcache.overall_hits::total 4236 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 4237 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 4237 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 4237 # number of overall hits
> system.cpu.dcache.overall_hits::total 4237 # number of overall hits
807,808c807,808
< system.cpu.dcache.ReadReq_accesses::cpu.data 3533 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 3533 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 3534 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 3534 # number of ReadReq accesses(hits+misses)
811,816c811,816
< system.cpu.dcache.demand_accesses::cpu.data 5263 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 5263 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 5263 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 5263 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087461 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.087461 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 5264 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 5264 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 5264 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 5264 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087436 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.087436 # miss rate for ReadReq accesses
819,822c819,822
< system.cpu.dcache.demand_miss_rate::cpu.data 0.195136 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.195136 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.195136 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.195136 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.195099 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.195099 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.195099 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.195099 # miss rate for overall accesses
861,862c861,862
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056326 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056326 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056310 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056310 # mshr miss rate for ReadReq accesses
865,868c865,868
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.065172 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.065172 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.065160 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.065160 # mshr miss rate for overall accesses
881c881
< system.cpu.icache.tags.tagsinuse 318.055053 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 318.054191 # Cycle average of tags in use
886c886
< system.cpu.icache.tags.occ_blocks::cpu.inst 318.055053 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 318.054191 # Average occupied blocks per requestor
908,913c908,913
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 72806995 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 72806995 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 72806995 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 72806995 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 72806995 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 72806995 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 72804995 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 72804995 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 72804995 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 72804995 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 72804995 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 72804995 # number of overall miss cycles
926,931c926,931
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81348.597765 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 81348.597765 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 81348.597765 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 81348.597765 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81346.363128 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 81346.363128 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 81346.363128 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 81346.363128 # average overall miss latency
952,957c952,957
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54757996 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 54757996 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54757996 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 54757996 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54757996 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 54757996 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54756996 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 54756996 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54756996 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 54756996 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54756996 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 54756996 # number of overall MSHR miss cycles
964,969c964,969
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87194.261146 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87194.261146 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87192.668790 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87192.668790 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency
974c974
< system.cpu.l2cache.tags.tagsinuse 534.674828 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 534.673891 # Cycle average of tags in use
979,980c979,980
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.519168 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155660 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.518306 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155585 # Average occupied blocks per requestor
1013,1014c1013,1014
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53778000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 53778000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53777000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 53777000 # number of ReadCleanReq miss cycles
1017c1017
< system.cpu.l2cache.demand_miss_latency::cpu.inst 53778000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 53777000 # number of demand (read+write) miss cycles
1019,1020c1019,1020
< system.cpu.l2cache.demand_miss_latency::total 83552500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 53778000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 83551500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 53777000 # number of overall miss cycles
1022c1022
< system.cpu.l2cache.overall_miss_latency::total 83552500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 83551500 # number of overall miss cycles
1051,1052c1051,1052
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86044.800000 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86044.800000 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86043.200000 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86043.200000 # average ReadCleanReq miss latency
1055c1055
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency
1057,1058c1057,1058
< system.cpu.l2cache.demand_avg_miss_latency::total 86314.566116 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 86313.533058 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency
1060c1060
< system.cpu.l2cache.overall_avg_miss_latency::total 86314.566116 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 86313.533058 # average overall miss latency
1081,1082c1081,1082
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47528000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47528000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47527000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47527000 # number of ReadCleanReq MSHR miss cycles
1085c1085
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47528000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47527000 # number of demand (read+write) MSHR miss cycles
1087,1088c1087,1088
< system.cpu.l2cache.demand_mshr_miss_latency::total 73882500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47528000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 73881500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47527000 # number of overall MSHR miss cycles
1090c1090
< system.cpu.l2cache.overall_mshr_miss_latency::total 73882500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 73881500 # number of overall MSHR miss cycles
1105,1106c1105,1106
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76044.800000 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76044.800000 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76043.200000 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76043.200000 # average ReadCleanReq mshr miss latency
1109c1109
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency
1111,1112c1111,1112
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency
1114c1114
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency
< host_inst_rate 139098 # Simulator instruction rate (inst/s)
< host_op_rate 139080 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 290337480 # Simulator tick rate (ticks/s)
< host_mem_usage 255644 # Number of bytes of host memory used
< host_seconds 0.09 # Real time elapsed on the host
---
> host_inst_rate 29979 # Simulator instruction rate (inst/s)
> host_op_rate 29977 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 62584510 # Simulator tick rate (ticks/s)
> host_mem_usage 237004 # Number of bytes of host memory used
> host_seconds 0.43 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 15942250 # Total ticks spent queuing
< system.physmem.totMemAccLat 34092250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 15941250 # Total ticks spent queuing
> system.physmem.totMemAccLat 34091250 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 16469.27 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16468.23 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 35219.27 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 35218.23 # Average memory access latency per DRAM burst
231c231
< system.physmem_0.actBackEnergy 6127500 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 6126930 # Energy for active background per rank (pJ)
233c233
< system.physmem_0.actPowerDownEnergy 5972460 # Energy for active power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 5973030 # Energy for active power-down per rank (pJ)
250c250
< system.physmem_1.actBackEnergy 4612440 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 4611870 # Energy for active background per rank (pJ)
252c252
< system.physmem_1.actPowerDownEnergy 6908970 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 6909540 # Energy for active power-down per rank (pJ)
283c283
< system.cpu.dtb.read_hits 4130 # DTB read hits
---
> system.cpu.dtb.read_hits 4131 # DTB read hits
286c286
< system.cpu.dtb.read_accesses 4206 # DTB read accesses
---
> system.cpu.dtb.read_accesses 4207 # DTB read accesses
291c291
< system.cpu.dtb.data_hits 6141 # DTB hits
---
> system.cpu.dtb.data_hits 6142 # DTB hits
294c294
< system.cpu.dtb.data_accesses 6265 # DTB accesses
---
> system.cpu.dtb.data_accesses 6266 # DTB accesses
326,328c326,328
< system.cpu.fetch.rateDist::samples 26300 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.059658 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.449516 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 26305 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.059456 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.449327 # Number of instructions fetched each cycle (Total)
330c330
< system.cpu.fetch.rateDist::0 21275 80.89% 80.89% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 21280 80.90% 80.90% # Number of instructions fetched each cycle (Total)
333c333
< system.cpu.fetch.rateDist::3 446 1.70% 85.99% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::3 446 1.70% 86.00% # Number of instructions fetched each cycle (Total)
342c342
< system.cpu.fetch.rateDist::total 26300 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 26305 # Number of instructions fetched each cycle (Total)
345,346c345,346
< system.cpu.decode.IdleCycles 36528 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 10375 # Number of cycles decode is blocked
---
> system.cpu.decode.IdleCycles 36539 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 10373 # Number of cycles decode is blocked
348c348
< system.cpu.decode.UnblockCycles 495 # Number of cycles decode is unblocking
---
> system.cpu.decode.UnblockCycles 496 # Number of cycles decode is unblocking
352c352
< system.cpu.decode.DecodedInsts 24583 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 24588 # Number of instructions handled by decode
355c355
< system.cpu.rename.IdleCycles 36872 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 36883 # Number of cycles rename is idle
358c358
< system.cpu.rename.RunCycles 4116 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 4115 # Number of cycles rename is running
362,363c362,363
< system.cpu.rename.IQFullEvents 223 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 328 # Number of times rename has blocked due to LQ full
---
> system.cpu.rename.IQFullEvents 222 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 329 # Number of times rename has blocked due to LQ full
373c373
< system.cpu.rename.skidInsts 1621 # count of insts added to the skid buffer
---
> system.cpu.rename.skidInsts 1617 # count of insts added to the skid buffer
384c384
< system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 19298 # Number of instructions issued
387c387
< system.cpu.iq.iqSquashedOperandsExamined 4753 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedOperandsExamined 4750 # Number of squashed operands that are examined and possibly removed from graph
389,391c389,391
< system.cpu.iq.issued_per_cycle::samples 26300 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.733688 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.450617 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 26305 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.733625 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.450843 # Number of insts issued each cycle
393,398c393,398
< system.cpu.iq.issued_per_cycle::0 18970 72.13% 72.13% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 2362 8.98% 81.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1626 6.18% 87.29% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 1294 4.92% 92.21% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 1061 4.03% 96.25% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 563 2.14% 98.39% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 18975 72.13% 72.13% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 2364 8.99% 81.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1624 6.17% 87.30% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 1293 4.92% 92.21% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 1059 4.03% 96.24% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 566 2.15% 98.39% # Number of insts issued each cycle
405c405
< system.cpu.iq.issued_per_cycle::total 26300 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 26305 # Number of insts issued each cycle
407,441c407,441
< system.cpu.iq.fu_full::IntAlu 29 9.67% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 191 63.67% 73.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 77 25.67% 99.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMemWrite 3 1.00% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 29 9.60% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.60% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 193 63.91% 73.51% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 77 25.50% 99.01% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.01% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMemWrite 3 0.99% 100.00% # attempts to use FU when none available
445,475c445,475
< system.cpu.iq.FU_type_0::IntAlu 5884 66.04% 66.06% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.07% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 5886 66.05% 66.07% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.08% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued
482c482
< system.cpu.iq.FU_type_0::total 8910 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 8912 # Type of FU issued
522,524c522,524
< system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued
< system.cpu.iq.rate 0.361863 # Inst issue rate
< system.cpu.iq.fu_busy_cnt::0 152 # FU busy when requested
---
> system.cpu.iq.FU_type::total 19298 0.00% 0.00% # Type of FU issued
> system.cpu.iq.rate 0.361901 # Inst issue rate
> system.cpu.iq.fu_busy_cnt::0 154 # FU busy when requested
526,530c526,530
< system.cpu.iq.fu_busy_cnt::total 300 # FU busy when requested
< system.cpu.iq.fu_busy_rate::0 0.007877 # FU busy rate (busy events/executed inst)
< system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst)
< system.cpu.iq.fu_busy_rate::total 0.015547 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 65200 # Number of integer instruction queue reads
---
> system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested
> system.cpu.iq.fu_busy_rate::0 0.007980 # FU busy rate (busy events/executed inst)
> system.cpu.iq.fu_busy_rate::1 0.007669 # FU busy rate (busy events/executed inst)
> system.cpu.iq.fu_busy_rate::total 0.015649 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 65211 # Number of integer instruction queue reads
532c532
< system.cpu.iq.int_inst_queue_wakeup_accesses 17504 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_wakeup_accesses 17509 # Number of integer instruction queue wakeup accesses
536c536
< system.cpu.iq.int_alu_accesses 19569 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 19573 # Number of integer alu accesses
573,574c573,574
< system.cpu.iew.iewExecutedInsts 18585 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts::0 1945 # Number of load instructions executed
---
> system.cpu.iew.iewExecutedInsts 18590 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts::0 1946 # Number of load instructions executed
576,577c576,577
< system.cpu.iew.iewExecLoadInsts::total 4209 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 711 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecLoadInsts::total 4210 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute
584c584
< system.cpu.iew.exec_refs::0 2942 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs::0 2943 # number of memory reference insts executed
586c586
< system.cpu.iew.exec_refs::total 6280 # number of memory reference insts executed
---
> system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed
593,594c593,594
< system.cpu.iew.exec_rate 0.348530 # Inst execution rate
< system.cpu.iew.wb_sent::0 8281 # cumulative count of insts sent to commit
---
> system.cpu.iew.exec_rate 0.348624 # Inst execution rate
> system.cpu.iew.wb_sent::0 8287 # cumulative count of insts sent to commit
596,597c596,597
< system.cpu.iew.wb_sent::total 17777 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count::0 8197 # cumulative count of insts written-back
---
> system.cpu.iew.wb_sent::total 17783 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count::0 8202 # cumulative count of insts written-back
599,606c599,606
< system.cpu.iew.wb_count::total 17524 # cumulative count of insts written-back
< system.cpu.iew.wb_producers::0 4340 # num instructions producing a value
< system.cpu.iew.wb_producers::1 4919 # num instructions producing a value
< system.cpu.iew.wb_producers::total 9259 # num instructions producing a value
< system.cpu.iew.wb_consumers::0 5879 # num instructions consuming a value
< system.cpu.iew.wb_consumers::1 6619 # num instructions consuming a value
< system.cpu.iew.wb_consumers::total 12498 # num instructions consuming a value
< system.cpu.iew.wb_rate::0 0.153721 # insts written-back per cycle
---
> system.cpu.iew.wb_count::total 17529 # cumulative count of insts written-back
> system.cpu.iew.wb_producers::0 4343 # num instructions producing a value
> system.cpu.iew.wb_producers::1 4920 # num instructions producing a value
> system.cpu.iew.wb_producers::total 9263 # num instructions producing a value
> system.cpu.iew.wb_consumers::0 5887 # num instructions consuming a value
> system.cpu.iew.wb_consumers::1 6620 # num instructions consuming a value
> system.cpu.iew.wb_consumers::total 12507 # num instructions consuming a value
> system.cpu.iew.wb_rate::0 0.153814 # insts written-back per cycle
608,611c608,611
< system.cpu.iew.wb_rate::total 0.328633 # insts written-back per cycle
< system.cpu.iew.wb_fanout::0 0.738221 # average fanout of values written-back
< system.cpu.iew.wb_fanout::1 0.743164 # average fanout of values written-back
< system.cpu.iew.wb_fanout::total 0.740839 # average fanout of values written-back
---
> system.cpu.iew.wb_rate::total 0.328726 # insts written-back per cycle
> system.cpu.iew.wb_fanout::0 0.737727 # average fanout of values written-back
> system.cpu.iew.wb_fanout::1 0.743202 # average fanout of values written-back
> system.cpu.iew.wb_fanout::total 0.740625 # average fanout of values written-back
615,617c615,617
< system.cpu.commit.committed_per_cycle::samples 26282 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.487178 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.404713 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 26287 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.487085 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.404867 # Number of insts commited each cycle
619,620c619,620
< system.cpu.commit.committed_per_cycle::0 21298 81.04% 81.04% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 2499 9.51% 90.54% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 21303 81.04% 81.04% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 2500 9.51% 90.55% # Number of insts commited each cycle
622c622
< system.cpu.commit.committed_per_cycle::3 403 1.53% 95.60% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::3 402 1.53% 95.60% # Number of insts commited each cycle
624,625c624,625
< system.cpu.commit.committed_per_cycle::5 154 0.59% 97.13% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 215 0.82% 97.95% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::5 154 0.59% 97.14% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 214 0.81% 97.95% # Number of insts commited each cycle
627c627
< system.cpu.commit.committed_per_cycle::8 422 1.61% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::8 423 1.61% 100.00% # Number of insts commited each cycle
631c631
< system.cpu.commit.committed_per_cycle::total 26282 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 26287 # Number of insts commited each cycle
741,742c741,742
< system.cpu.commit.bw_lim_events 422 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 113054 # The number of ROB reads
---
> system.cpu.commit.bw_lim_events 423 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 113065 # The number of ROB reads
745c745
< system.cpu.idleCycles 27024 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 27019 # Total number of cycles that the CPU has spent unscheduled due to idling
758,759c758,759
< system.cpu.int_regfile_reads 23475 # number of integer regfile reads
< system.cpu.int_regfile_writes 13132 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 23483 # number of integer regfile reads
> system.cpu.int_regfile_writes 13138 # number of integer regfile writes
768,769c768,769
< system.cpu.dcache.tags.tagsinuse 216.020971 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 4236 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 216.020896 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 4237 # Total number of references to valid blocks.
771c771
< system.cpu.dcache.tags.avg_refs 12.385965 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 12.388889 # Average number of references to valid blocks.
773c773
< system.cpu.dcache.tags.occ_blocks::cpu.data 216.020971 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 216.020896 # Average occupied blocks per requestor
780,781c780,781
< system.cpu.dcache.tags.tag_accesses 10868 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 10868 # Number of data accesses
---
> system.cpu.dcache.tags.tag_accesses 10870 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 10870 # Number of data accesses
783,784c783,784
< system.cpu.dcache.ReadReq_hits::cpu.data 3224 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 3224 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 3225 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 3225 # number of ReadReq hits
787,790c787,790
< system.cpu.dcache.demand_hits::cpu.data 4236 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 4236 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 4236 # number of overall hits
< system.cpu.dcache.overall_hits::total 4236 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 4237 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 4237 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 4237 # number of overall hits
> system.cpu.dcache.overall_hits::total 4237 # number of overall hits
807,808c807,808
< system.cpu.dcache.ReadReq_accesses::cpu.data 3533 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 3533 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 3534 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 3534 # number of ReadReq accesses(hits+misses)
811,816c811,816
< system.cpu.dcache.demand_accesses::cpu.data 5263 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 5263 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 5263 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 5263 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087461 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.087461 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 5264 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 5264 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 5264 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 5264 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087436 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.087436 # miss rate for ReadReq accesses
819,822c819,822
< system.cpu.dcache.demand_miss_rate::cpu.data 0.195136 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.195136 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.195136 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.195136 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.195099 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.195099 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.195099 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.195099 # miss rate for overall accesses
861,862c861,862
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056326 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056326 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056310 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056310 # mshr miss rate for ReadReq accesses
865,868c865,868
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.065172 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.065172 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.065160 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.065160 # mshr miss rate for overall accesses
881c881
< system.cpu.icache.tags.tagsinuse 318.055053 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 318.054191 # Cycle average of tags in use
886c886
< system.cpu.icache.tags.occ_blocks::cpu.inst 318.055053 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 318.054191 # Average occupied blocks per requestor
908,913c908,913
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 72806995 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 72806995 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 72806995 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 72806995 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 72806995 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 72806995 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 72804995 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 72804995 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 72804995 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 72804995 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 72804995 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 72804995 # number of overall miss cycles
926,931c926,931
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81348.597765 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 81348.597765 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 81348.597765 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 81348.597765 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81346.363128 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 81346.363128 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 81346.363128 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 81346.363128 # average overall miss latency
952,957c952,957
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54757996 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 54757996 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54757996 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 54757996 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54757996 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 54757996 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54756996 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 54756996 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54756996 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 54756996 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54756996 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 54756996 # number of overall MSHR miss cycles
964,969c964,969
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87194.261146 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87194.261146 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87192.668790 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87192.668790 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency
974c974
< system.cpu.l2cache.tags.tagsinuse 534.674828 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 534.673891 # Cycle average of tags in use
979,980c979,980
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.519168 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155660 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.518306 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155585 # Average occupied blocks per requestor
1013,1014c1013,1014
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53778000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 53778000 # number of ReadCleanReq miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 53777000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 53777000 # number of ReadCleanReq miss cycles
1017c1017
< system.cpu.l2cache.demand_miss_latency::cpu.inst 53778000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 53777000 # number of demand (read+write) miss cycles
1019,1020c1019,1020
< system.cpu.l2cache.demand_miss_latency::total 83552500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 53778000 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 83551500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 53777000 # number of overall miss cycles
1022c1022
< system.cpu.l2cache.overall_miss_latency::total 83552500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 83551500 # number of overall miss cycles
1051,1052c1051,1052
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86044.800000 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86044.800000 # average ReadCleanReq miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86043.200000 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86043.200000 # average ReadCleanReq miss latency
1055c1055
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency
1057,1058c1057,1058
< system.cpu.l2cache.demand_avg_miss_latency::total 86314.566116 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 86313.533058 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency
1060c1060
< system.cpu.l2cache.overall_avg_miss_latency::total 86314.566116 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 86313.533058 # average overall miss latency
1081,1082c1081,1082
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47528000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47528000 # number of ReadCleanReq MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47527000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47527000 # number of ReadCleanReq MSHR miss cycles
1085c1085
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47528000 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47527000 # number of demand (read+write) MSHR miss cycles
1087,1088c1087,1088
< system.cpu.l2cache.demand_mshr_miss_latency::total 73882500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47528000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::total 73881500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47527000 # number of overall MSHR miss cycles
1090c1090
< system.cpu.l2cache.overall_mshr_miss_latency::total 73882500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 73881500 # number of overall MSHR miss cycles
1105,1106c1105,1106
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76044.800000 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76044.800000 # average ReadCleanReq mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76043.200000 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76043.200000 # average ReadCleanReq mshr miss latency
1109c1109
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency
1111,1112c1111,1112
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency
1114c1114
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency