4,5c4,5
< sim_ticks 25580500 # Number of ticks simulated
< final_tick 25580500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 25607000 # Number of ticks simulated
> final_tick 25607000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 123264 # Simulator instruction rate (inst/s)
< host_op_rate 123250 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 246864911 # Simulator tick rate (ticks/s)
< host_mem_usage 250880 # Number of bytes of host memory used
< host_seconds 0.10 # Real time elapsed on the host
---
> host_inst_rate 110915 # Simulator instruction rate (inst/s)
> host_op_rate 110902 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 222369986 # Simulator tick rate (ticks/s)
> host_mem_usage 254744 # Number of bytes of host memory used
> host_seconds 0.12 # Real time elapsed on the host
16,17c16,17
< system.physmem.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 39680 # Number of bytes read from this memory
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 39936 # Number of bytes read from this memory
19,22c19,22
< system.physmem.bytes_read::total 61504 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 39680 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 39680 # Number of instructions bytes read from this memory
< system.physmem.num_reads::cpu.inst 620 # Number of read requests responded to by this memory
---
> system.physmem.bytes_read::total 61760 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 39936 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 39936 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 624 # Number of read requests responded to by this memory
24,33c24,33
< system.physmem.num_reads::total 961 # Number of read requests responded to by this memory
< system.physmem.bw_read::cpu.inst 1551181564 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 853149860 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 2404331424 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 1551181564 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 1551181564 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 1551181564 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 853149860 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 2404331424 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 962 # Number of read requests accepted
---
> system.physmem.num_reads::total 965 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1559573554 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 852266958 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2411840512 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1559573554 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1559573554 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1559573554 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 852266958 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2411840512 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 966 # Number of read requests accepted
35c35
< system.physmem.readBursts 962 # Number of DRAM read bursts, including those serviced by the write queue
---
> system.physmem.readBursts 966 # Number of DRAM read bursts, including those serviced by the write queue
37c37
< system.physmem.bytesReadDRAM 61568 # Total number of bytes read from DRAM
---
> system.physmem.bytesReadDRAM 61824 # Total number of bytes read from DRAM
40c40
< system.physmem.bytesReadSys 61568 # Total read bytes from the system interface side
---
> system.physmem.bytesReadSys 61824 # Total read bytes from the system interface side
45c45
< system.physmem.perBankRdBursts::0 83 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 84 # Per bank write bursts
47,49c47,49
< system.physmem.perBankRdBursts::2 78 # Per bank write bursts
< system.physmem.perBankRdBursts::3 59 # Per bank write bursts
< system.physmem.perBankRdBursts::4 86 # Per bank write bursts
---
> system.physmem.perBankRdBursts::2 77 # Per bank write bursts
> system.physmem.perBankRdBursts::3 58 # Per bank write bursts
> system.physmem.perBankRdBursts::4 90 # Per bank write bursts
60c60
< system.physmem.perBankRdBursts::15 36 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 37 # Per bank write bursts
79c79
< system.physmem.totGap 25549500 # Total gap between requests
---
> system.physmem.totGap 25577000 # Total gap between requests
86c86
< system.physmem.readPktSize::6 962 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 966 # Read request sizes (log2)
94,97c94,97
< system.physmem.rdQLenPdf::0 350 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 315 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 188 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 80 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 351 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 323 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 171 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 89 # What read queue length does an incoming req see
99,101c99,101
< system.physmem.rdQLenPdf::5 6 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see
190,207c190,207
< system.physmem.bytesPerActivate::samples 209 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 281.722488 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 176.924618 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 290.527007 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 69 33.01% 33.01% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 64 30.62% 63.64% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 20 9.57% 73.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 12 5.74% 78.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 11 5.26% 84.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 8 3.83% 88.04% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 9 4.31% 92.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 4 1.91% 94.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 12 5.74% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 209 # Bytes accessed per row activation
< system.physmem.totQLat 12704750 # Total ticks spent queuing
< system.physmem.totMemAccLat 30742250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 4810000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 13206.60 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 211 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 278.748815 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 172.887192 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 291.495109 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 76 36.02% 36.02% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 57 27.01% 63.03% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 23 10.90% 73.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 12 5.69% 79.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 8 3.79% 83.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 11 5.21% 88.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 6 2.84% 91.47% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 6 2.84% 94.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 12 5.69% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 211 # Bytes accessed per row activation
> system.physmem.totQLat 14120500 # Total ticks spent queuing
> system.physmem.totMemAccLat 32233000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 4830000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 14617.49 # Average queueing delay per DRAM burst
209,210c209,210
< system.physmem.avgMemAccLat 31956.60 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 2406.83 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 33367.49 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 2414.34 # Average DRAM read bandwidth in MiByte/s
212c212
< system.physmem.avgRdBWSys 2406.83 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 2414.34 # Average system read bandwidth in MiByte/s
215,216c215,216
< system.physmem.busUtil 18.80 # Data bus utilization in percentage
< system.physmem.busUtilRead 18.80 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 18.86 # Data bus utilization in percentage
> system.physmem.busUtilRead 18.86 # Data bus utilization in percentage for reads
218c218
< system.physmem.avgRdQLen 2.38 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing
220c220
< system.physmem.readRowHits 743 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 745 # Number of row buffer hits during reads
222c222
< system.physmem.readRowHitRate 77.23 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 77.12 # Row buffer hit rate for reads
224,228c224,228
< system.physmem.avgGap 26558.73 # Average gap between requests
< system.physmem.pageHitRate 77.23 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 824040 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 449625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 4453800 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 26477.23 # Average gap between requests
> system.physmem.pageHitRate 77.12 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 861840 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 470250 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 4477200 # Energy for read commands per rank (pJ)
233,235c233,235
< system.physmem_0.totalEnergy 23400705 # Total energy per rank (pJ)
< system.physmem_0.averagePower 990.768140 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 694500 # Time in different power states
---
> system.physmem_0.totalEnergy 23482530 # Total energy per rank (pJ)
> system.physmem_0.averagePower 994.232548 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 763000 # Time in different power states
240,242c240,242
< system.physmem_1.actEnergy 733320 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 400125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 2683200 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 703080 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 383625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 2628600 # Energy for read commands per rank (pJ)
245,249c245,249
< system.physmem_1.actBackEnergy 15873930 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 246750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 21463005 # Total energy per rank (pJ)
< system.physmem_1.averagePower 908.727388 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 326750 # Time in different power states
---
> system.physmem_1.actBackEnergy 15488325 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 585000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 21314310 # Total energy per rank (pJ)
> system.physmem_1.averagePower 902.431754 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 878500 # Time in different power states
252c252
< system.physmem_1.memoryStateTime::ACT 22525750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 21974000 # Time in different power states
254,259c254,259
< system.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 4883 # Number of BP lookups
< system.cpu.branchPred.condPredicted 2924 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 790 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 3812 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 1143 # Number of BTB hits
---
> system.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 4896 # Number of BP lookups
> system.cpu.branchPred.condPredicted 2917 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 793 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 3827 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 1151 # Number of BTB hits
261,266c261,266
< system.cpu.branchPred.BTBHitPct 29.984260 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 681 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 53 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 814 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 150 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 664 # Number of indirect misses.
---
> system.cpu.branchPred.BTBHitPct 30.075777 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 688 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 51 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 820 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 149 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 671 # Number of indirect misses.
273,274c273,274
< system.cpu.dtb.read_hits 4166 # DTB read hits
< system.cpu.dtb.read_misses 75 # DTB read misses
---
> system.cpu.dtb.read_hits 4131 # DTB read hits
> system.cpu.dtb.read_misses 80 # DTB read misses
276,278c276,278
< system.cpu.dtb.read_accesses 4241 # DTB read accesses
< system.cpu.dtb.write_hits 1988 # DTB write hits
< system.cpu.dtb.write_misses 49 # DTB write misses
---
> system.cpu.dtb.read_accesses 4211 # DTB read accesses
> system.cpu.dtb.write_hits 2002 # DTB write hits
> system.cpu.dtb.write_misses 47 # DTB write misses
280,282c280,282
< system.cpu.dtb.write_accesses 2037 # DTB write accesses
< system.cpu.dtb.data_hits 6154 # DTB hits
< system.cpu.dtb.data_misses 124 # DTB misses
---
> system.cpu.dtb.write_accesses 2049 # DTB write accesses
> system.cpu.dtb.data_hits 6133 # DTB hits
> system.cpu.dtb.data_misses 127 # DTB misses
284,286c284,286
< system.cpu.dtb.data_accesses 6278 # DTB accesses
< system.cpu.itb.fetch_hits 3823 # ITB hits
< system.cpu.itb.fetch_misses 51 # ITB misses
---
> system.cpu.dtb.data_accesses 6260 # DTB accesses
> system.cpu.itb.fetch_hits 3841 # ITB hits
> system.cpu.itb.fetch_misses 50 # ITB misses
288c288
< system.cpu.itb.fetch_accesses 3874 # ITB accesses
---
> system.cpu.itb.fetch_accesses 3891 # ITB accesses
303,304c303,304
< system.cpu.pwrStateResidencyTicks::ON 25580500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 51162 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 25607000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 51215 # number of cpu cycles simulated
307,318c307,318
< system.cpu.fetch.icacheStallCycles 749 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 28166 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 4883 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 1974 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 9785 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 559 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.CacheLines 3823 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 565 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 26518 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.062146 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.446390 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 758 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 28344 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 4896 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 1988 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 10026 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 873 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 478 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.CacheLines 3841 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 575 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 26635 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.064164 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.464308 # Number of instructions fetched each cycle (Total)
320,328c320,328
< system.cpu.fetch.rateDist::0 21410 80.74% 80.74% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 517 1.95% 82.69% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 399 1.50% 84.19% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 426 1.61% 85.80% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 581 2.19% 87.99% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 343 1.29% 89.28% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 470 1.77% 91.06% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 262 0.99% 92.04% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 2110 7.96% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 21569 80.98% 80.98% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 505 1.90% 82.88% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 398 1.49% 84.37% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 435 1.63% 86.00% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 472 1.77% 87.78% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 332 1.25% 89.02% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 468 1.76% 90.78% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 266 1.00% 91.78% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 2190 8.22% 100.00% # Number of instructions fetched each cycle (Total)
332,357c332,357
< system.cpu.fetch.rateDist::total 26518 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.095442 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.550526 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 35549 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 11706 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 4004 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 486 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 721 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 379 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 24714 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 389 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 721 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 35923 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 4419 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 1518 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 4115 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 5770 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 23686 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 47 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 451 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 687 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 4626 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 17749 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 29662 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 29644 # Number of integer rename lookups
---
> system.cpu.fetch.rateDist::total 26635 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.095597 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.553432 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 36561 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 11106 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 3971 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 513 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 726 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 381 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 147 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 24763 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 394 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 726 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 36906 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 4191 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 1623 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 4148 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 5283 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 23783 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 30 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 282 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 398 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 4456 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 17841 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 29807 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 29789 # Number of integer rename lookups
360c360
< system.cpu.rename.UndoneMaps 8595 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 8687 # Number of HB maps that are undone due to squashing
363,366c363,366
< system.cpu.rename.skidInsts 1784 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 2582 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1268 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 15 # Number of conflicting loads.
---
> system.cpu.rename.skidInsts 1771 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 2529 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 14 # Number of conflicting loads.
368,369c368,369
< system.cpu.memDep1.insertedLoads 1972 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep1.insertedStores 1081 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep1.insertedLoads 1973 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep1.insertedStores 1111 # Number of stores inserted to the mem dependence unit.
372c372
< system.cpu.iq.iqInstsAdded 21922 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 21942 # Number of instructions added to the IQ (excludes non-spec)
374,377c374,377
< system.cpu.iq.iqInstsIssued 19305 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 9201 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 4899 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 47 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 9221 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 4863 # Number of squashed operands that are examined and possibly removed from graph
379,381c379,381
< system.cpu.iq.issued_per_cycle::samples 26518 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.727996 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.455439 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 26635 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.724460 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.451046 # Number of insts issued each cycle
383,391c383,391
< system.cpu.iq.issued_per_cycle::0 19215 72.46% 72.46% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 2319 8.75% 81.21% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 1762 6.64% 87.85% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 1149 4.33% 92.18% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 1009 3.80% 95.99% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 611 2.30% 98.29% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 303 1.14% 99.43% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 94 0.35% 99.79% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 56 0.21% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 19310 72.50% 72.50% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 2394 8.99% 81.49% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 1620 6.08% 87.57% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 1274 4.78% 92.35% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 1030 3.87% 96.22% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 532 2.00% 98.22% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 319 1.20% 99.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 102 0.38% 99.80% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 54 0.20% 100.00% # Number of insts issued each cycle
395c395
< system.cpu.iq.issued_per_cycle::total 26518 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 26635 # Number of insts issued each cycle
397,427c397,427
< system.cpu.iq.fu_full::IntAlu 25 8.33% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 8.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 198 66.00% 74.33% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 77 25.67% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 28 9.18% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 201 65.90% 75.08% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 76 24.92% 100.00% # attempts to use FU when none available
431,461c431,461
< system.cpu.iq.FU_type_0::IntAlu 6801 65.70% 65.72% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.73% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.73% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.75% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2445 23.62% 89.36% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1101 10.64% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 6749 65.93% 65.95% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 1 0.01% 65.96% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 65.96% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.98% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 2387 23.32% 89.30% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1095 10.70% 100.00% # Type of FU issued
464c464
< system.cpu.iq.FU_type_0::total 10352 # Type of FU issued
---
> system.cpu.iq.FU_type_0::total 10236 # Type of FU issued
466,496c466,496
< system.cpu.iq.FU_type_1::IntAlu 5921 66.13% 66.16% # Type of FU issued
< system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.17% # Type of FU issued
< system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.17% # Type of FU issued
< system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.19% # Type of FU issued
< system.cpu.iq.FU_type_1::MemRead 2023 22.60% 88.79% # Type of FU issued
< system.cpu.iq.FU_type_1::MemWrite 1004 11.21% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_1::IntAlu 6020 66.45% 66.47% # Type of FU issued
> system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.48% # Type of FU issued
> system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.48% # Type of FU issued
> system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.50% # Type of FU issued
> system.cpu.iq.FU_type_1::MemRead 2019 22.28% 88.79% # Type of FU issued
> system.cpu.iq.FU_type_1::MemWrite 1016 11.21% 100.00% # Type of FU issued
499,510c499,510
< system.cpu.iq.FU_type_1::total 8953 # Type of FU issued
< system.cpu.iq.FU_type::total 19305 0.00% 0.00% # Type of FU issued
< system.cpu.iq.rate 0.377331 # Inst issue rate
< system.cpu.iq.fu_busy_cnt::0 160 # FU busy when requested
< system.cpu.iq.fu_busy_cnt::1 140 # FU busy when requested
< system.cpu.iq.fu_busy_cnt::total 300 # FU busy when requested
< system.cpu.iq.fu_busy_rate::0 0.008288 # FU busy rate (busy events/executed inst)
< system.cpu.iq.fu_busy_rate::1 0.007252 # FU busy rate (busy events/executed inst)
< system.cpu.iq.fu_busy_rate::total 0.015540 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 65432 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 31184 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 17495 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_1::total 9060 # Type of FU issued
> system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued
> system.cpu.iq.rate 0.376765 # Inst issue rate
> system.cpu.iq.fu_busy_cnt::0 157 # FU busy when requested
> system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested
> system.cpu.iq.fu_busy_cnt::total 305 # FU busy when requested
> system.cpu.iq.fu_busy_rate::0 0.008136 # FU busy rate (busy events/executed inst)
> system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst)
> system.cpu.iq.fu_busy_rate::total 0.015806 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 65537 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 31224 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 17544 # Number of integer instruction queue wakeup accesses
514c514
< system.cpu.iq.int_alu_accesses 19579 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 19575 # Number of integer alu accesses
518,521c518,521
< system.cpu.iew.lsq.thread0.squashedLoads 1397 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 403 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1344 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 388 # Number of stores squashed
525,526c525,526
< system.cpu.iew.lsq.thread0.cacheBlocked 284 # Number of times an access to memory failed due to the cache being blocked
< system.cpu.iew.lsq.thread1.forwLoads 47 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.cacheBlocked 261 # Number of times an access to memory failed due to the cache being blocked
> system.cpu.iew.lsq.thread1.forwLoads 45 # Number of loads that had data forwarded from stores
528,531c528,531
< system.cpu.iew.lsq.thread1.squashedLoads 787 # Number of loads squashed
< system.cpu.iew.lsq.thread1.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations
< system.cpu.iew.lsq.thread1.squashedStores 216 # Number of stores squashed
---
> system.cpu.iew.lsq.thread1.squashedLoads 788 # Number of loads squashed
> system.cpu.iew.lsq.thread1.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread1.memOrderViolation 12 # Number of memory ordering violations
> system.cpu.iew.lsq.thread1.squashedStores 246 # Number of stores squashed
535c535
< system.cpu.iew.lsq.thread1.cacheBlocked 280 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread1.cacheBlocked 288 # Number of times an access to memory failed due to the cache being blocked
537,543c537,543
< system.cpu.iew.iewSquashCycles 721 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 2770 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 755 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 22107 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 169 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 4554 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 2349 # Number of dispatched store instructions
---
> system.cpu.iew.iewSquashCycles 726 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 2949 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 377 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 22125 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 143 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 4502 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 2364 # Number of dispatched store instructions
545,546c545,546
< system.cpu.iew.iewIQFullEvents 22 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 722 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewIQFullEvents 25 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 340 # Number of times the LSQ has become full, causing a stall
548c548
< system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly
---
> system.cpu.iew.predictedTakenIncorrect 130 # Number of branches that were predicted taken incorrectly
550,555c550,555
< system.cpu.iew.branchMispredicts 771 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 18606 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts::0 2294 # Number of load instructions executed
< system.cpu.iew.iewExecLoadInsts::1 1956 # Number of load instructions executed
< system.cpu.iew.iewExecLoadInsts::total 4250 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 699 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.branchMispredicts 769 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 18625 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts::0 2260 # Number of load instructions executed
> system.cpu.iew.iewExecLoadInsts::1 1960 # Number of load instructions executed
> system.cpu.iew.iewExecLoadInsts::total 4220 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 671 # Number of squashed instructions skipped in execute
559c559
< system.cpu.iew.exec_nop::0 68 # number of nop insts executed
---
> system.cpu.iew.exec_nop::0 66 # number of nop insts executed
561,590c561,590
< system.cpu.iew.exec_nop::total 135 # number of nop insts executed
< system.cpu.iew.exec_refs::0 3353 # number of memory reference insts executed
< system.cpu.iew.exec_refs::1 2946 # number of memory reference insts executed
< system.cpu.iew.exec_refs::total 6299 # number of memory reference insts executed
< system.cpu.iew.exec_branches::0 1561 # Number of branches executed
< system.cpu.iew.exec_branches::1 1400 # Number of branches executed
< system.cpu.iew.exec_branches::total 2961 # Number of branches executed
< system.cpu.iew.exec_stores::0 1059 # Number of stores executed
< system.cpu.iew.exec_stores::1 990 # Number of stores executed
< system.cpu.iew.exec_stores::total 2049 # Number of stores executed
< system.cpu.iew.exec_rate 0.363668 # Inst execution rate
< system.cpu.iew.wb_sent::0 9443 # cumulative count of insts sent to commit
< system.cpu.iew.wb_sent::1 8345 # cumulative count of insts sent to commit
< system.cpu.iew.wb_sent::total 17788 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count::0 9266 # cumulative count of insts written-back
< system.cpu.iew.wb_count::1 8249 # cumulative count of insts written-back
< system.cpu.iew.wb_count::total 17515 # cumulative count of insts written-back
< system.cpu.iew.wb_producers::0 4880 # num instructions producing a value
< system.cpu.iew.wb_producers::1 4386 # num instructions producing a value
< system.cpu.iew.wb_producers::total 9266 # num instructions producing a value
< system.cpu.iew.wb_consumers::0 6580 # num instructions consuming a value
< system.cpu.iew.wb_consumers::1 5911 # num instructions consuming a value
< system.cpu.iew.wb_consumers::total 12491 # num instructions consuming a value
< system.cpu.iew.wb_rate::0 0.181111 # insts written-back per cycle
< system.cpu.iew.wb_rate::1 0.161233 # insts written-back per cycle
< system.cpu.iew.wb_rate::total 0.342344 # insts written-back per cycle
< system.cpu.iew.wb_fanout::0 0.741641 # average fanout of values written-back
< system.cpu.iew.wb_fanout::1 0.742006 # average fanout of values written-back
< system.cpu.iew.wb_fanout::total 0.741814 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 9276 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop::total 133 # number of nop insts executed
> system.cpu.iew.exec_refs::0 3318 # number of memory reference insts executed
> system.cpu.iew.exec_refs::1 2963 # number of memory reference insts executed
> system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed
> system.cpu.iew.exec_branches::0 1546 # Number of branches executed
> system.cpu.iew.exec_branches::1 1419 # Number of branches executed
> system.cpu.iew.exec_branches::total 2965 # Number of branches executed
> system.cpu.iew.exec_stores::0 1058 # Number of stores executed
> system.cpu.iew.exec_stores::1 1003 # Number of stores executed
> system.cpu.iew.exec_stores::total 2061 # Number of stores executed
> system.cpu.iew.exec_rate 0.363663 # Inst execution rate
> system.cpu.iew.wb_sent::0 9379 # cumulative count of insts sent to commit
> system.cpu.iew.wb_sent::1 8440 # cumulative count of insts sent to commit
> system.cpu.iew.wb_sent::total 17819 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count::0 9213 # cumulative count of insts written-back
> system.cpu.iew.wb_count::1 8351 # cumulative count of insts written-back
> system.cpu.iew.wb_count::total 17564 # cumulative count of insts written-back
> system.cpu.iew.wb_producers::0 4854 # num instructions producing a value
> system.cpu.iew.wb_producers::1 4443 # num instructions producing a value
> system.cpu.iew.wb_producers::total 9297 # num instructions producing a value
> system.cpu.iew.wb_consumers::0 6502 # num instructions consuming a value
> system.cpu.iew.wb_consumers::1 5954 # num instructions consuming a value
> system.cpu.iew.wb_consumers::total 12456 # num instructions consuming a value
> system.cpu.iew.wb_rate::0 0.179889 # insts written-back per cycle
> system.cpu.iew.wb_rate::1 0.163058 # insts written-back per cycle
> system.cpu.iew.wb_rate::total 0.342946 # insts written-back per cycle
> system.cpu.iew.wb_fanout::0 0.746540 # average fanout of values written-back
> system.cpu.iew.wb_fanout::1 0.746221 # average fanout of values written-back
> system.cpu.iew.wb_fanout::total 0.746387 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 9288 # The number of squashed insts skipped by commit
592,595c592,595
< system.cpu.commit.branchMispredicts 642 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 26498 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.483206 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.376058 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 647 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 26599 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.481371 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.387327 # Number of insts commited each cycle
597,605c597,605
< system.cpu.commit.committed_per_cycle::0 21430 80.87% 80.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 2543 9.60% 90.47% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 900 3.40% 93.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 463 1.75% 95.61% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 308 1.16% 96.78% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 165 0.62% 97.40% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 178 0.67% 98.07% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 141 0.53% 98.60% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 370 1.40% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 21475 80.74% 80.74% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 2692 10.12% 90.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 910 3.42% 94.28% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 379 1.42% 95.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 247 0.93% 96.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 153 0.58% 97.21% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 207 0.78% 97.98% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 128 0.48% 98.47% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 408 1.53% 100.00% # Number of insts commited each cycle
609c609
< system.cpu.commit.committed_per_cycle::total 26498 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 26599 # Number of insts commited each cycle
711,715c711,715
< system.cpu.commit.bw_lim_events 370 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 113336 # The number of ROB reads
< system.cpu.rob.rob_writes 45860 # The number of ROB writes
< system.cpu.timesIdled 410 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 24644 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 408 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 113983 # The number of ROB reads
> system.cpu.rob.rob_writes 45899 # The number of ROB writes
> system.cpu.timesIdled 392 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 24580 # Total number of cycles that the CPU has spent unscheduled due to idling
722,729c722,729
< system.cpu.cpi::0 8.012843 # CPI: Cycles Per Instruction
< system.cpu.cpi::1 8.012843 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 4.006421 # CPI: Total CPI of All Threads
< system.cpu.ipc::0 0.124800 # IPC: Instructions Per Cycle
< system.cpu.ipc::1 0.124800 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.249599 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 23495 # number of integer regfile reads
< system.cpu.int_regfile_writes 13160 # number of integer regfile writes
---
> system.cpu.cpi::0 8.021143 # CPI: Cycles Per Instruction
> system.cpu.cpi::1 8.021143 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 4.010572 # CPI: Total CPI of All Threads
> system.cpu.ipc::0 0.124671 # IPC: Instructions Per Cycle
> system.cpu.ipc::1 0.124671 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.249341 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 23552 # number of integer regfile reads
> system.cpu.int_regfile_writes 13174 # number of integer regfile writes
734c734
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
738,739c738,739
< system.cpu.dcache.tags.tagsinuse 216.394211 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 4263 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 214.351374 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 4238 # Total number of references to valid blocks.
741c741
< system.cpu.dcache.tags.avg_refs 12.501466 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 12.428152 # Average number of references to valid blocks.
743,745c743,745
< system.cpu.dcache.tags.occ_blocks::cpu.data 216.394211 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.052831 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.052831 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 214.351374 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.052332 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.052332 # Average percentage of cache occupancy
747,748c747,748
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 269 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 264 # Occupied blocks per task id
750,778c750,778
< system.cpu.dcache.tags.tag_accesses 10889 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 10889 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 3245 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 3245 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 1018 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 1018 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 4263 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 4263 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 4263 # number of overall hits
< system.cpu.dcache.overall_hits::total 4263 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 299 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 299 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 712 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 712 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 1011 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 1011 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 1011 # number of overall misses
< system.cpu.dcache.overall_misses::total 1011 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 23300000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 23300000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 52494934 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 52494934 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 75794934 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 75794934 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 75794934 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 75794934 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 3544 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 3544 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.tags.tag_accesses 10843 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 10843 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 3221 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 3221 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 1017 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 1017 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 4238 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 4238 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 4238 # number of overall hits
> system.cpu.dcache.overall_hits::total 4238 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 300 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 300 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 713 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 713 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 1013 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 1013 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 1013 # number of overall misses
> system.cpu.dcache.overall_misses::total 1013 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 25278500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 25278500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 49654940 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 49654940 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 74933440 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 74933440 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 74933440 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 74933440 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 3521 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 3521 # number of ReadReq accesses(hits+misses)
781,801c781,801
< system.cpu.dcache.demand_accesses::cpu.data 5274 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 5274 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 5274 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 5274 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084368 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.084368 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.411561 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.411561 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.191695 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.191695 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.191695 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.191695 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77926.421405 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 77926.421405 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 73728.839888 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 73728.839888 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 74970.261128 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 74970.261128 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 74970.261128 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 74970.261128 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 5977 # number of cycles access was blocked
---
> system.cpu.dcache.demand_accesses::cpu.data 5251 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 5251 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 5251 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 5251 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085203 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.085203 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412139 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.412139 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.192916 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.192916 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.192916 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.192916 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 84261.666667 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 84261.666667 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69642.272090 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 69642.272090 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 73971.806515 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 73971.806515 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 73971.806515 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 73971.806515 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 6514 # number of cycles access was blocked
803c803
< system.cpu.dcache.blocked::no_mshrs 130 # number of cycles access was blocked
---
> system.cpu.dcache.blocked::no_mshrs 137 # number of cycles access was blocked
805c805
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.976923 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 47.547445 # average number of cycles each access was blocked
809,818c809,818
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 566 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 566 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 669 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 669 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 669 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 669 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 196 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 196 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 568 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 568 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 671 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 671 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 671 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 671 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 197 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 197 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 145 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 145 # number of WriteReq MSHR misses
823,847c823,847
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17233500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 17233500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12825986 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 12825986 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30059486 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 30059486 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30059486 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 30059486 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055305 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055305 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.064846 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.064846 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.064846 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.064846 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87926.020408 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87926.020408 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 87849.219178 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 87849.219178 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 87893.233918 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 87893.233918 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18892500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 18892500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12000985 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 12000985 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30893485 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 30893485 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30893485 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 30893485 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.055950 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.055950 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083815 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083815 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065130 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.065130 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065130 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.065130 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 95901.015228 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 95901.015228 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82765.413793 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82765.413793 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90331.827485 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 90331.827485 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90331.827485 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 90331.827485 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
851,854c851,854
< system.cpu.icache.tags.tagsinuse 317.276824 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 2916 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 623 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 4.680578 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 314.192674 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 2931 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 627 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 4.674641 # Average number of references to valid blocks.
856,902c856,902
< system.cpu.icache.tags.occ_blocks::cpu.inst 317.276824 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.154920 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.154920 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 616 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 237 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 379 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.300781 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 8261 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 8261 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 2916 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 2916 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 2916 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 2916 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 2916 # number of overall hits
< system.cpu.icache.overall_hits::total 2916 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 903 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 903 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 903 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 903 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 903 # number of overall misses
< system.cpu.icache.overall_misses::total 903 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 69936495 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 69936495 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 69936495 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 69936495 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 69936495 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 69936495 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 3819 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 3819 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 3819 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 3819 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 3819 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 3819 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.236449 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.236449 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.236449 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.236449 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.236449 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.236449 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77449.053156 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 77449.053156 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 77449.053156 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 77449.053156 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 77449.053156 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 77449.053156 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 3083 # number of cycles access was blocked
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 314.192674 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.153414 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.153414 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 620 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 246 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 374 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.302734 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 8297 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 8297 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 2931 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 2931 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 2931 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 2931 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 2931 # number of overall hits
> system.cpu.icache.overall_hits::total 2931 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 904 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 904 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 904 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 904 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 904 # number of overall misses
> system.cpu.icache.overall_misses::total 904 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 70022492 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 70022492 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 70022492 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 70022492 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 70022492 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 70022492 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 3835 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 3835 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 3835 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 3835 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 3835 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 3835 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.235724 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.235724 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.235724 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.235724 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.235724 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.235724 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77458.508850 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 77458.508850 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 77458.508850 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 77458.508850 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 77458.508850 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 77458.508850 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 3069 # number of cycles access was blocked
904c904
< system.cpu.icache.blocked::no_mshrs 55 # number of cycles access was blocked
---
> system.cpu.icache.blocked::no_mshrs 61 # number of cycles access was blocked
906c906
< system.cpu.icache.avg_blocked_cycles::no_mshrs 56.054545 # average number of cycles each access was blocked
---
> system.cpu.icache.avg_blocked_cycles::no_mshrs 50.311475 # average number of cycles each access was blocked
910,940c910,940
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 280 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 280 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 280 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 280 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 280 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 280 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 623 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 623 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 623 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 623 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 623 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 623 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 50404995 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 50404995 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 50404995 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 50404995 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 50404995 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 50404995 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163132 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163132 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163132 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.163132 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163132 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.163132 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 80906.894061 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 80906.894061 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 80906.894061 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 80906.894061 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 277 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 277 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 277 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 277 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 277 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 277 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 52227494 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 52227494 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 52227494 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 52227494 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 52227494 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 52227494 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163494 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.163494 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163494 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.163494 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83297.438596 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83297.438596 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83297.438596 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 83297.438596 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83297.438596 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 83297.438596 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
944c944
< system.cpu.l2cache.tags.tagsinuse 438.773475 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 529.119750 # Cycle average of tags in use
946,947c946,947
< system.cpu.l2cache.tags.sampled_refs 815 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.012270 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 965 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.010363 # Average number of references to valid blocks.
949,960c949,960
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 317.771557 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 121.001918 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009698 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.003693 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.013390 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 815 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 286 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 529 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.024872 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 8737 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 8737 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 314.628551 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 214.491199 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009602 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.006546 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.016147 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 965 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 319 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 646 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.029449 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 8773 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 8773 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
969,975c969,975
< system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 620 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 620 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 196 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 196 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 620 # number of demand (read+write) misses
---
> system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 624 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 624 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 197 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 197 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 624 # number of demand (read+write) misses
977,978c977,978
< system.cpu.l2cache.demand_misses::total 962 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 620 # number of overall misses
---
> system.cpu.l2cache.demand_misses::total 966 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 624 # number of overall misses
980,992c980,992
< system.cpu.l2cache.overall_misses::total 962 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12598500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 12598500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 49432000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 49432000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 16931000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 16931000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 49432000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 29529500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 78961500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 49432000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 29529500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 78961500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_misses::total 966 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11774500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 11774500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 51248500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 51248500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 18588500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 18588500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 51248500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 30363000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 81611500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 51248500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 30363000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 81611500 # number of overall miss cycles
995,1001c995,1001
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 623 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 623 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 196 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 196 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 623 # number of demand (read+write) accesses
---
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 627 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 627 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 197 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 197 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 627 # number of demand (read+write) accesses
1003,1004c1003,1004
< system.cpu.l2cache.demand_accesses::total 965 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 623 # number of overall (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::total 969 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 627 # number of overall (read+write) accesses
1006c1006
< system.cpu.l2cache.overall_accesses::total 965 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::total 969 # number of overall (read+write) accesses
1009,1010c1009,1010
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995185 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995185 # miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995215 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995215 # miss rate for ReadCleanReq accesses
1013c1013
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995185 # miss rate for demand accesses
---
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995215 # miss rate for demand accesses
1015,1016c1015,1016
< system.cpu.l2cache.demand_miss_rate::total 0.996891 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995185 # miss rate for overall accesses
---
> system.cpu.l2cache.demand_miss_rate::total 0.996904 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995215 # miss rate for overall accesses
1018,1030c1018,1030
< system.cpu.l2cache.overall_miss_rate::total 0.996891 # miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 86291.095890 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86291.095890 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79729.032258 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79729.032258 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86382.653061 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86382.653061 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79729.032258 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86343.567251 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 82080.561331 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79729.032258 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86343.567251 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 82080.561331 # average overall miss latency
---
> system.cpu.l2cache.overall_miss_rate::total 0.996904 # miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81203.448276 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81203.448276 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82129.006410 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82129.006410 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 94357.868020 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 94357.868020 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82129.006410 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88780.701754 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 84483.954451 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82129.006410 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88780.701754 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 84483.954451 # average overall miss latency
1037,1043c1037,1043
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 620 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 620 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 196 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 196 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 620 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 624 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 624 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 197 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 197 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses
1045,1046c1045,1046
< system.cpu.l2cache.demand_mshr_misses::total 962 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 620 # number of overall MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::total 966 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses
1048,1060c1048,1060
< system.cpu.l2cache.overall_mshr_misses::total 962 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11138500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11138500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 43232000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 43232000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 14981000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 14981000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 43232000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26119500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 69351500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 43232000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26119500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 69351500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::total 966 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10324500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10324500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 45008500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 45008500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 16628500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 16628500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45008500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26953000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 71961500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45008500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26953000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 71961500 # number of overall MSHR miss cycles
1063,1064c1063,1064
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995185 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995185 # mshr miss rate for ReadCleanReq accesses
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995215 # mshr miss rate for ReadCleanReq accesses
1067c1067
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995185 # mshr miss rate for demand accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for demand accesses
1069,1070c1069,1070
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.996891 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995185 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.996904 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995215 # mshr miss rate for overall accesses
1072,1085c1072,1085
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.996891 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76291.095890 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76291.095890 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69729.032258 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69729.032258 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76433.673469 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76433.673469 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69729.032258 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76372.807018 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72090.956341 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 972 # Total number of requests made to the snoop filter.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.996904 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71203.448276 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71203.448276 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72129.006410 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72129.006410 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 84408.629442 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 84408.629442 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72129.006410 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78809.941520 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 74494.306418 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72129.006410 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78809.941520 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 74494.306418 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 976 # Total number of requests made to the snoop filter.
1091,1092c1091,1092
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 818 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 823 # Transaction distribution
1094,1098c1094,1098
< system.cpu.toL2Bus.trans_dist::ReadExReq 146 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 146 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 623 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 196 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1253 # Packet count per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 627 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 197 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1261 # Packet count per connected master and slave (bytes)
1100,1101c1100,1101
< system.cpu.toL2Bus.pkt_count::total 1936 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40320 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_count::total 1944 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40576 # Cumulative packet size per connected master and slave (bytes)
1103c1103
< system.cpu.toL2Bus.pkt_size::total 62144 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.pkt_size::total 62400 # Cumulative packet size per connected master and slave (bytes)
1106,1108c1106,1108
< system.cpu.toL2Bus.snoop_fanout::samples 965 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.002073 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.045502 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 969 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.002064 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.045408 # Request fanout histogram
1110c1110
< system.cpu.toL2Bus.snoop_fanout::0 963 99.79% 99.79% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 967 99.79% 99.79% # Request fanout histogram
1116,1117c1116,1117
< system.cpu.toL2Bus.snoop_fanout::total 965 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 493000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 969 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 495000 # Layer occupancy (ticks)
1119c1119
< system.cpu.toL2Bus.respLayer0.occupancy 934500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 940500 # Layer occupancy (ticks)
1123,1131c1123,1137
< system.membus.pwrStateResidencyTicks::UNDEFINED 25580500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 815 # Transaction distribution
< system.membus.trans_dist::ReadExReq 146 # Transaction distribution
< system.membus.trans_dist::ReadExResp 146 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 816 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1923 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 1923 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61504 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 61504 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.snoop_filter.tot_requests 966 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 25607000 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 820 # Transaction distribution
> system.membus.trans_dist::ReadExReq 145 # Transaction distribution
> system.membus.trans_dist::ReadExResp 145 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 821 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1931 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 1931 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61760 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 61760 # Cumulative packet size per connected master and slave (bytes)
1134c1140
< system.membus.snoop_fanout::samples 962 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 966 # Request fanout histogram
1138c1144
< system.membus.snoop_fanout::0 962 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 966 100.00% 100.00% # Request fanout histogram
1143,1144c1149,1150
< system.membus.snoop_fanout::total 962 # Request fanout histogram
< system.membus.reqLayer0.occupancy 1181000 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 966 # Request fanout histogram
> system.membus.reqLayer0.occupancy 1177000 # Layer occupancy (ticks)
1146c1152
< system.membus.respLayer1.occupancy 5115750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 5133750 # Layer occupancy (ticks)