stats.txt (11687:b3d5f0e9e258) stats.txt (11731:c473ca7cc650)
1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000027 # Number of seconds simulated
4sim_ticks 26661500 # Number of ticks simulated
5final_tick 26661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000027 # Number of seconds simulated
4sim_ticks 26661500 # Number of ticks simulated
5final_tick 26661500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 139098 # Simulator instruction rate (inst/s)
8host_op_rate 139080 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 290337480 # Simulator tick rate (ticks/s)
10host_mem_usage 255644 # Number of bytes of host memory used
11host_seconds 0.09 # Real time elapsed on the host
7host_inst_rate 29979 # Simulator instruction rate (inst/s)
8host_op_rate 29977 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 62584510 # Simulator tick rate (ticks/s)
10host_mem_usage 237004 # Number of bytes of host memory used
11host_seconds 0.43 # Real time elapsed on the host
12sim_insts 12770 # Number of instructions simulated
13sim_ops 12770 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 21888 # Number of bytes read from this memory
19system.physmem.bytes_read::total 61888 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 342 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 967 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 1500290681 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 820959061 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 2321249742 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 1500290681 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 1500290681 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 1500290681 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 820959061 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 2321249742 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.readReqs 968 # Number of read requests accepted
34system.physmem.writeReqs 0 # Number of write requests accepted
35system.physmem.readBursts 968 # Number of DRAM read bursts, including those serviced by the write queue
36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37system.physmem.bytesReadDRAM 61952 # Total number of bytes read from DRAM
38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40system.physmem.bytesReadSys 61952 # Total read bytes from the system interface side
41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45system.physmem.perBankRdBursts::0 84 # Per bank write bursts
46system.physmem.perBankRdBursts::1 150 # Per bank write bursts
47system.physmem.perBankRdBursts::2 77 # Per bank write bursts
48system.physmem.perBankRdBursts::3 58 # Per bank write bursts
49system.physmem.perBankRdBursts::4 90 # Per bank write bursts
50system.physmem.perBankRdBursts::5 45 # Per bank write bursts
51system.physmem.perBankRdBursts::6 33 # Per bank write bursts
52system.physmem.perBankRdBursts::7 50 # Per bank write bursts
53system.physmem.perBankRdBursts::8 42 # Per bank write bursts
54system.physmem.perBankRdBursts::9 38 # Per bank write bursts
55system.physmem.perBankRdBursts::10 28 # Per bank write bursts
56system.physmem.perBankRdBursts::11 34 # Per bank write bursts
57system.physmem.perBankRdBursts::12 15 # Per bank write bursts
58system.physmem.perBankRdBursts::13 120 # Per bank write bursts
59system.physmem.perBankRdBursts::14 67 # Per bank write bursts
60system.physmem.perBankRdBursts::15 37 # Per bank write bursts
61system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79system.physmem.totGap 26630500 # Total gap between requests
80system.physmem.readPktSize::0 0 # Read request sizes (log2)
81system.physmem.readPktSize::1 0 # Read request sizes (log2)
82system.physmem.readPktSize::2 0 # Read request sizes (log2)
83system.physmem.readPktSize::3 0 # Read request sizes (log2)
84system.physmem.readPktSize::4 0 # Read request sizes (log2)
85system.physmem.readPktSize::5 0 # Read request sizes (log2)
86system.physmem.readPktSize::6 968 # Read request sizes (log2)
87system.physmem.writePktSize::0 0 # Write request sizes (log2)
88system.physmem.writePktSize::1 0 # Write request sizes (log2)
89system.physmem.writePktSize::2 0 # Write request sizes (log2)
90system.physmem.writePktSize::3 0 # Write request sizes (log2)
91system.physmem.writePktSize::4 0 # Write request sizes (log2)
92system.physmem.writePktSize::5 0 # Write request sizes (log2)
93system.physmem.writePktSize::6 0 # Write request sizes (log2)
94system.physmem.rdQLenPdf::0 332 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::1 313 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::2 185 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::3 94 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190system.physmem.bytesPerActivate::samples 202 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::mean 289.584158 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 180.299588 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 295.891915 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::0-127 69 34.16% 34.16% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::128-255 55 27.23% 61.39% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::256-383 20 9.90% 71.29% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 16 7.92% 79.21% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639 9 4.46% 83.66% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767 7 3.47% 87.13% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895 9 4.46% 91.58% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023 3 1.49% 93.07% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151 14 6.93% 100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total 202 # Bytes accessed per row activation
12sim_insts 12770 # Number of instructions simulated
13sim_ops 12770 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
17system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 21888 # Number of bytes read from this memory
19system.physmem.bytes_read::total 61888 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 342 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 967 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 1500290681 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 820959061 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 2321249742 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 1500290681 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 1500290681 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 1500290681 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 820959061 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 2321249742 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.readReqs 968 # Number of read requests accepted
34system.physmem.writeReqs 0 # Number of write requests accepted
35system.physmem.readBursts 968 # Number of DRAM read bursts, including those serviced by the write queue
36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
37system.physmem.bytesReadDRAM 61952 # Total number of bytes read from DRAM
38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
40system.physmem.bytesReadSys 61952 # Total read bytes from the system interface side
41system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
42system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
43system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
44system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
45system.physmem.perBankRdBursts::0 84 # Per bank write bursts
46system.physmem.perBankRdBursts::1 150 # Per bank write bursts
47system.physmem.perBankRdBursts::2 77 # Per bank write bursts
48system.physmem.perBankRdBursts::3 58 # Per bank write bursts
49system.physmem.perBankRdBursts::4 90 # Per bank write bursts
50system.physmem.perBankRdBursts::5 45 # Per bank write bursts
51system.physmem.perBankRdBursts::6 33 # Per bank write bursts
52system.physmem.perBankRdBursts::7 50 # Per bank write bursts
53system.physmem.perBankRdBursts::8 42 # Per bank write bursts
54system.physmem.perBankRdBursts::9 38 # Per bank write bursts
55system.physmem.perBankRdBursts::10 28 # Per bank write bursts
56system.physmem.perBankRdBursts::11 34 # Per bank write bursts
57system.physmem.perBankRdBursts::12 15 # Per bank write bursts
58system.physmem.perBankRdBursts::13 120 # Per bank write bursts
59system.physmem.perBankRdBursts::14 67 # Per bank write bursts
60system.physmem.perBankRdBursts::15 37 # Per bank write bursts
61system.physmem.perBankWrBursts::0 0 # Per bank write bursts
62system.physmem.perBankWrBursts::1 0 # Per bank write bursts
63system.physmem.perBankWrBursts::2 0 # Per bank write bursts
64system.physmem.perBankWrBursts::3 0 # Per bank write bursts
65system.physmem.perBankWrBursts::4 0 # Per bank write bursts
66system.physmem.perBankWrBursts::5 0 # Per bank write bursts
67system.physmem.perBankWrBursts::6 0 # Per bank write bursts
68system.physmem.perBankWrBursts::7 0 # Per bank write bursts
69system.physmem.perBankWrBursts::8 0 # Per bank write bursts
70system.physmem.perBankWrBursts::9 0 # Per bank write bursts
71system.physmem.perBankWrBursts::10 0 # Per bank write bursts
72system.physmem.perBankWrBursts::11 0 # Per bank write bursts
73system.physmem.perBankWrBursts::12 0 # Per bank write bursts
74system.physmem.perBankWrBursts::13 0 # Per bank write bursts
75system.physmem.perBankWrBursts::14 0 # Per bank write bursts
76system.physmem.perBankWrBursts::15 0 # Per bank write bursts
77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
79system.physmem.totGap 26630500 # Total gap between requests
80system.physmem.readPktSize::0 0 # Read request sizes (log2)
81system.physmem.readPktSize::1 0 # Read request sizes (log2)
82system.physmem.readPktSize::2 0 # Read request sizes (log2)
83system.physmem.readPktSize::3 0 # Read request sizes (log2)
84system.physmem.readPktSize::4 0 # Read request sizes (log2)
85system.physmem.readPktSize::5 0 # Read request sizes (log2)
86system.physmem.readPktSize::6 968 # Read request sizes (log2)
87system.physmem.writePktSize::0 0 # Write request sizes (log2)
88system.physmem.writePktSize::1 0 # Write request sizes (log2)
89system.physmem.writePktSize::2 0 # Write request sizes (log2)
90system.physmem.writePktSize::3 0 # Write request sizes (log2)
91system.physmem.writePktSize::4 0 # Write request sizes (log2)
92system.physmem.writePktSize::5 0 # Write request sizes (log2)
93system.physmem.writePktSize::6 0 # Write request sizes (log2)
94system.physmem.rdQLenPdf::0 332 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::1 313 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::2 185 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::3 94 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::4 37 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::5 7 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
126system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
190system.physmem.bytesPerActivate::samples 202 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::mean 289.584158 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::gmean 180.299588 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::stdev 295.891915 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::0-127 69 34.16% 34.16% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::128-255 55 27.23% 61.39% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::256-383 20 9.90% 71.29% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::384-511 16 7.92% 79.21% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::512-639 9 4.46% 83.66% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::640-767 7 3.47% 87.13% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::768-895 9 4.46% 91.58% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::896-1023 3 1.49% 93.07% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::1024-1151 14 6.93% 100.00% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::total 202 # Bytes accessed per row activation
204system.physmem.totQLat 15942250 # Total ticks spent queuing
205system.physmem.totMemAccLat 34092250 # Total ticks spent from burst creation until serviced by the DRAM
204system.physmem.totQLat 15941250 # Total ticks spent queuing
205system.physmem.totMemAccLat 34091250 # Total ticks spent from burst creation until serviced by the DRAM
206system.physmem.totBusLat 4840000 # Total ticks spent in databus transfers
206system.physmem.totBusLat 4840000 # Total ticks spent in databus transfers
207system.physmem.avgQLat 16469.27 # Average queueing delay per DRAM burst
207system.physmem.avgQLat 16468.23 # Average queueing delay per DRAM burst
208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
209system.physmem.avgMemAccLat 35219.27 # Average memory access latency per DRAM burst
209system.physmem.avgMemAccLat 35218.23 # Average memory access latency per DRAM burst
210system.physmem.avgRdBW 2323.65 # Average DRAM read bandwidth in MiByte/s
211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212system.physmem.avgRdBWSys 2323.65 # Average system read bandwidth in MiByte/s
213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215system.physmem.busUtil 18.15 # Data bus utilization in percentage
216system.physmem.busUtilRead 18.15 # Data bus utilization in percentage for reads
217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing
219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
220system.physmem.readRowHits 755 # Number of row buffer hits during reads
221system.physmem.writeRowHits 0 # Number of row buffer hits during writes
222system.physmem.readRowHitRate 78.00 # Row buffer hit rate for reads
223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
224system.physmem.avgGap 27510.85 # Average gap between requests
225system.physmem.pageHitRate 78.00 # Row buffer hit rate, read and write combined
226system.physmem_0.actEnergy 849660 # Energy for activate commands per rank (pJ)
227system.physmem_0.preEnergy 436425 # Energy for precharge commands per rank (pJ)
228system.physmem_0.readEnergy 4191180 # Energy for read commands per rank (pJ)
229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
210system.physmem.avgRdBW 2323.65 # Average DRAM read bandwidth in MiByte/s
211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
212system.physmem.avgRdBWSys 2323.65 # Average system read bandwidth in MiByte/s
213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
215system.physmem.busUtil 18.15 # Data bus utilization in percentage
216system.physmem.busUtilRead 18.15 # Data bus utilization in percentage for reads
217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
218system.physmem.avgRdQLen 2.46 # Average read queue length when enqueuing
219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
220system.physmem.readRowHits 755 # Number of row buffer hits during reads
221system.physmem.writeRowHits 0 # Number of row buffer hits during writes
222system.physmem.readRowHitRate 78.00 # Row buffer hit rate for reads
223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
224system.physmem.avgGap 27510.85 # Average gap between requests
225system.physmem.pageHitRate 78.00 # Row buffer hit rate, read and write combined
226system.physmem_0.actEnergy 849660 # Energy for activate commands per rank (pJ)
227system.physmem_0.preEnergy 436425 # Energy for precharge commands per rank (pJ)
228system.physmem_0.readEnergy 4191180 # Energy for read commands per rank (pJ)
229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
231system.physmem_0.actBackEnergy 6127500 # Energy for active background per rank (pJ)
231system.physmem_0.actBackEnergy 6126930 # Energy for active background per rank (pJ)
232system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ)
232system.physmem_0.preBackEnergy 47520 # Energy for precharge background per rank (pJ)
233system.physmem_0.actPowerDownEnergy 5972460 # Energy for active power-down per rank (pJ)
233system.physmem_0.actPowerDownEnergy 5973030 # Energy for active power-down per rank (pJ)
234system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ)
235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
236system.physmem_0.totalEnergy 19470105 # Total energy per rank (pJ)
237system.physmem_0.averagePower 730.243038 # Core power per rank (mW)
238system.physmem_0.totalIdleTime 12953500 # Total Idle time Per DRAM Rank
239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states
240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
242system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states
243system.physmem_0.memoryStateTime::ACT 12735000 # Time in different power states
244system.physmem_0.memoryStateTime::ACT_PDN 13102250 # Time in different power states
245system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ)
246system.physmem_1.preEnergy 330165 # Energy for precharge commands per rank (pJ)
247system.physmem_1.readEnergy 2720340 # Energy for read commands per rank (pJ)
248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
234system.physmem_0.prePowerDownEnergy 1440 # Energy for precharge power-down per rank (pJ)
235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
236system.physmem_0.totalEnergy 19470105 # Total energy per rank (pJ)
237system.physmem_0.averagePower 730.243038 # Core power per rank (mW)
238system.physmem_0.totalIdleTime 12953500 # Total Idle time Per DRAM Rank
239system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states
240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
242system.physmem_0.memoryStateTime::PRE_PDN 3750 # Time in different power states
243system.physmem_0.memoryStateTime::ACT 12735000 # Time in different power states
244system.physmem_0.memoryStateTime::ACT_PDN 13102250 # Time in different power states
245system.physmem_1.actEnergy 671160 # Energy for activate commands per rank (pJ)
246system.physmem_1.preEnergy 330165 # Energy for precharge commands per rank (pJ)
247system.physmem_1.readEnergy 2720340 # Energy for read commands per rank (pJ)
248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
250system.physmem_1.actBackEnergy 4612440 # Energy for active background per rank (pJ)
250system.physmem_1.actBackEnergy 4611870 # Energy for active background per rank (pJ)
251system.physmem_1.preBackEnergy 162240 # Energy for precharge background per rank (pJ)
251system.physmem_1.preBackEnergy 162240 # Energy for precharge background per rank (pJ)
252system.physmem_1.actPowerDownEnergy 6908970 # Energy for active power-down per rank (pJ)
252system.physmem_1.actPowerDownEnergy 6909540 # Energy for active power-down per rank (pJ)
253system.physmem_1.prePowerDownEnergy 373920 # Energy for precharge power-down per rank (pJ)
254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
255system.physmem_1.totalEnergy 17623155 # Total energy per rank (pJ)
256system.physmem_1.averagePower 660.971589 # Core power per rank (mW)
257system.physmem_1.totalIdleTime 16131250 # Total Idle time Per DRAM Rank
258system.physmem_1.memoryStateTime::IDLE 312000 # Time in different power states
259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
261system.physmem_1.memoryStateTime::PRE_PDN 973000 # Time in different power states
262system.physmem_1.memoryStateTime::ACT 9438250 # Time in different power states
263system.physmem_1.memoryStateTime::ACT_PDN 15158250 # Time in different power states
264system.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
265system.cpu.branchPred.lookups 4864 # Number of BP lookups
266system.cpu.branchPred.condPredicted 2895 # Number of conditional branches predicted
267system.cpu.branchPred.condIncorrect 795 # Number of conditional branches incorrect
268system.cpu.branchPred.BTBLookups 3714 # Number of BTB lookups
269system.cpu.branchPred.BTBHits 1183 # Number of BTB hits
270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
271system.cpu.branchPred.BTBHitPct 31.852450 # BTB Hit Percentage
272system.cpu.branchPred.usedRAS 710 # Number of times the RAS was used to get a target.
273system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions.
274system.cpu.branchPred.indirectLookups 762 # Number of indirect predictor lookups.
275system.cpu.branchPred.indirectHits 147 # Number of indirect target hits.
276system.cpu.branchPred.indirectMisses 615 # Number of indirect misses.
277system.cpu.branchPredindirectMispredicted 133 # Number of mispredicted indirect branches.
278system.cpu_clk_domain.clock 500 # Clock period in ticks
279system.cpu.dtb.fetch_hits 0 # ITB hits
280system.cpu.dtb.fetch_misses 0 # ITB misses
281system.cpu.dtb.fetch_acv 0 # ITB acv
282system.cpu.dtb.fetch_accesses 0 # ITB accesses
253system.physmem_1.prePowerDownEnergy 373920 # Energy for precharge power-down per rank (pJ)
254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
255system.physmem_1.totalEnergy 17623155 # Total energy per rank (pJ)
256system.physmem_1.averagePower 660.971589 # Core power per rank (mW)
257system.physmem_1.totalIdleTime 16131250 # Total Idle time Per DRAM Rank
258system.physmem_1.memoryStateTime::IDLE 312000 # Time in different power states
259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
261system.physmem_1.memoryStateTime::PRE_PDN 973000 # Time in different power states
262system.physmem_1.memoryStateTime::ACT 9438250 # Time in different power states
263system.physmem_1.memoryStateTime::ACT_PDN 15158250 # Time in different power states
264system.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
265system.cpu.branchPred.lookups 4864 # Number of BP lookups
266system.cpu.branchPred.condPredicted 2895 # Number of conditional branches predicted
267system.cpu.branchPred.condIncorrect 795 # Number of conditional branches incorrect
268system.cpu.branchPred.BTBLookups 3714 # Number of BTB lookups
269system.cpu.branchPred.BTBHits 1183 # Number of BTB hits
270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
271system.cpu.branchPred.BTBHitPct 31.852450 # BTB Hit Percentage
272system.cpu.branchPred.usedRAS 710 # Number of times the RAS was used to get a target.
273system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions.
274system.cpu.branchPred.indirectLookups 762 # Number of indirect predictor lookups.
275system.cpu.branchPred.indirectHits 147 # Number of indirect target hits.
276system.cpu.branchPred.indirectMisses 615 # Number of indirect misses.
277system.cpu.branchPredindirectMispredicted 133 # Number of mispredicted indirect branches.
278system.cpu_clk_domain.clock 500 # Clock period in ticks
279system.cpu.dtb.fetch_hits 0 # ITB hits
280system.cpu.dtb.fetch_misses 0 # ITB misses
281system.cpu.dtb.fetch_acv 0 # ITB acv
282system.cpu.dtb.fetch_accesses 0 # ITB accesses
283system.cpu.dtb.read_hits 4130 # DTB read hits
283system.cpu.dtb.read_hits 4131 # DTB read hits
284system.cpu.dtb.read_misses 76 # DTB read misses
285system.cpu.dtb.read_acv 0 # DTB read access violations
284system.cpu.dtb.read_misses 76 # DTB read misses
285system.cpu.dtb.read_acv 0 # DTB read access violations
286system.cpu.dtb.read_accesses 4206 # DTB read accesses
286system.cpu.dtb.read_accesses 4207 # DTB read accesses
287system.cpu.dtb.write_hits 2011 # DTB write hits
288system.cpu.dtb.write_misses 48 # DTB write misses
289system.cpu.dtb.write_acv 0 # DTB write access violations
290system.cpu.dtb.write_accesses 2059 # DTB write accesses
287system.cpu.dtb.write_hits 2011 # DTB write hits
288system.cpu.dtb.write_misses 48 # DTB write misses
289system.cpu.dtb.write_acv 0 # DTB write access violations
290system.cpu.dtb.write_accesses 2059 # DTB write accesses
291system.cpu.dtb.data_hits 6141 # DTB hits
291system.cpu.dtb.data_hits 6142 # DTB hits
292system.cpu.dtb.data_misses 124 # DTB misses
293system.cpu.dtb.data_acv 0 # DTB access violations
292system.cpu.dtb.data_misses 124 # DTB misses
293system.cpu.dtb.data_acv 0 # DTB access violations
294system.cpu.dtb.data_accesses 6265 # DTB accesses
294system.cpu.dtb.data_accesses 6266 # DTB accesses
295system.cpu.itb.fetch_hits 3836 # ITB hits
296system.cpu.itb.fetch_misses 50 # ITB misses
297system.cpu.itb.fetch_acv 0 # ITB acv
298system.cpu.itb.fetch_accesses 3886 # ITB accesses
299system.cpu.itb.read_hits 0 # DTB read hits
300system.cpu.itb.read_misses 0 # DTB read misses
301system.cpu.itb.read_acv 0 # DTB read access violations
302system.cpu.itb.read_accesses 0 # DTB read accesses
303system.cpu.itb.write_hits 0 # DTB write hits
304system.cpu.itb.write_misses 0 # DTB write misses
305system.cpu.itb.write_acv 0 # DTB write access violations
306system.cpu.itb.write_accesses 0 # DTB write accesses
307system.cpu.itb.data_hits 0 # DTB hits
308system.cpu.itb.data_misses 0 # DTB misses
309system.cpu.itb.data_acv 0 # DTB access violations
310system.cpu.itb.data_accesses 0 # DTB accesses
311system.cpu.workload0.num_syscalls 17 # Number of system calls
312system.cpu.workload1.num_syscalls 17 # Number of system calls
313system.cpu.pwrStateResidencyTicks::ON 26661500 # Cumulative time (in ticks) in various power states
314system.cpu.numCycles 53324 # number of cpu cycles simulated
315system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
316system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
317system.cpu.fetch.icacheStallCycles 748 # Number of cycles fetch is stalled on an Icache miss
318system.cpu.fetch.Insts 27869 # Number of instructions fetch has processed
319system.cpu.fetch.Branches 4864 # Number of branches that fetch encountered
320system.cpu.fetch.predictedBranches 2040 # Number of branches that fetch has predicted taken
321system.cpu.fetch.Cycles 9408 # Number of cycles fetch has run and was not squashing or blocked
322system.cpu.fetch.SquashCycles 875 # Number of cycles fetch has spent squashing
323system.cpu.fetch.MiscStallCycles 344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
324system.cpu.fetch.CacheLines 3836 # Number of cache lines fetched
325system.cpu.fetch.IcacheSquashes 566 # Number of outstanding Icache misses that were squashed
295system.cpu.itb.fetch_hits 3836 # ITB hits
296system.cpu.itb.fetch_misses 50 # ITB misses
297system.cpu.itb.fetch_acv 0 # ITB acv
298system.cpu.itb.fetch_accesses 3886 # ITB accesses
299system.cpu.itb.read_hits 0 # DTB read hits
300system.cpu.itb.read_misses 0 # DTB read misses
301system.cpu.itb.read_acv 0 # DTB read access violations
302system.cpu.itb.read_accesses 0 # DTB read accesses
303system.cpu.itb.write_hits 0 # DTB write hits
304system.cpu.itb.write_misses 0 # DTB write misses
305system.cpu.itb.write_acv 0 # DTB write access violations
306system.cpu.itb.write_accesses 0 # DTB write accesses
307system.cpu.itb.data_hits 0 # DTB hits
308system.cpu.itb.data_misses 0 # DTB misses
309system.cpu.itb.data_acv 0 # DTB access violations
310system.cpu.itb.data_accesses 0 # DTB accesses
311system.cpu.workload0.num_syscalls 17 # Number of system calls
312system.cpu.workload1.num_syscalls 17 # Number of system calls
313system.cpu.pwrStateResidencyTicks::ON 26661500 # Cumulative time (in ticks) in various power states
314system.cpu.numCycles 53324 # number of cpu cycles simulated
315system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
316system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
317system.cpu.fetch.icacheStallCycles 748 # Number of cycles fetch is stalled on an Icache miss
318system.cpu.fetch.Insts 27869 # Number of instructions fetch has processed
319system.cpu.fetch.Branches 4864 # Number of branches that fetch encountered
320system.cpu.fetch.predictedBranches 2040 # Number of branches that fetch has predicted taken
321system.cpu.fetch.Cycles 9408 # Number of cycles fetch has run and was not squashing or blocked
322system.cpu.fetch.SquashCycles 875 # Number of cycles fetch has spent squashing
323system.cpu.fetch.MiscStallCycles 344 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
324system.cpu.fetch.CacheLines 3836 # Number of cache lines fetched
325system.cpu.fetch.IcacheSquashes 566 # Number of outstanding Icache misses that were squashed
326system.cpu.fetch.rateDist::samples 26300 # Number of instructions fetched each cycle (Total)
327system.cpu.fetch.rateDist::mean 1.059658 # Number of instructions fetched each cycle (Total)
328system.cpu.fetch.rateDist::stdev 2.449516 # Number of instructions fetched each cycle (Total)
326system.cpu.fetch.rateDist::samples 26305 # Number of instructions fetched each cycle (Total)
327system.cpu.fetch.rateDist::mean 1.059456 # Number of instructions fetched each cycle (Total)
328system.cpu.fetch.rateDist::stdev 2.449327 # Number of instructions fetched each cycle (Total)
329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
329system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
330system.cpu.fetch.rateDist::0 21275 80.89% 80.89% # Number of instructions fetched each cycle (Total)
330system.cpu.fetch.rateDist::0 21280 80.90% 80.90% # Number of instructions fetched each cycle (Total)
331system.cpu.fetch.rateDist::1 504 1.92% 82.81% # Number of instructions fetched each cycle (Total)
332system.cpu.fetch.rateDist::2 391 1.49% 84.30% # Number of instructions fetched each cycle (Total)
331system.cpu.fetch.rateDist::1 504 1.92% 82.81% # Number of instructions fetched each cycle (Total)
332system.cpu.fetch.rateDist::2 391 1.49% 84.30% # Number of instructions fetched each cycle (Total)
333system.cpu.fetch.rateDist::3 446 1.70% 85.99% # Number of instructions fetched each cycle (Total)
333system.cpu.fetch.rateDist::3 446 1.70% 86.00% # Number of instructions fetched each cycle (Total)
334system.cpu.fetch.rateDist::4 478 1.82% 87.81% # Number of instructions fetched each cycle (Total)
335system.cpu.fetch.rateDist::5 367 1.40% 89.21% # Number of instructions fetched each cycle (Total)
336system.cpu.fetch.rateDist::6 469 1.78% 90.99% # Number of instructions fetched each cycle (Total)
337system.cpu.fetch.rateDist::7 276 1.05% 92.04% # Number of instructions fetched each cycle (Total)
338system.cpu.fetch.rateDist::8 2094 7.96% 100.00% # Number of instructions fetched each cycle (Total)
339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
334system.cpu.fetch.rateDist::4 478 1.82% 87.81% # Number of instructions fetched each cycle (Total)
335system.cpu.fetch.rateDist::5 367 1.40% 89.21% # Number of instructions fetched each cycle (Total)
336system.cpu.fetch.rateDist::6 469 1.78% 90.99% # Number of instructions fetched each cycle (Total)
337system.cpu.fetch.rateDist::7 276 1.05% 92.04% # Number of instructions fetched each cycle (Total)
338system.cpu.fetch.rateDist::8 2094 7.96% 100.00% # Number of instructions fetched each cycle (Total)
339system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
340system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
341system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
342system.cpu.fetch.rateDist::total 26300 # Number of instructions fetched each cycle (Total)
342system.cpu.fetch.rateDist::total 26305 # Number of instructions fetched each cycle (Total)
343system.cpu.fetch.branchRate 0.091216 # Number of branch fetches per cycle
344system.cpu.fetch.rate 0.522635 # Number of inst fetches per cycle
343system.cpu.fetch.branchRate 0.091216 # Number of branch fetches per cycle
344system.cpu.fetch.rate 0.522635 # Number of inst fetches per cycle
345system.cpu.decode.IdleCycles 36528 # Number of cycles decode is idle
346system.cpu.decode.BlockedCycles 10375 # Number of cycles decode is blocked
345system.cpu.decode.IdleCycles 36539 # Number of cycles decode is idle
346system.cpu.decode.BlockedCycles 10373 # Number of cycles decode is blocked
347system.cpu.decode.RunCycles 3958 # Number of cycles decode is running
347system.cpu.decode.RunCycles 3958 # Number of cycles decode is running
348system.cpu.decode.UnblockCycles 495 # Number of cycles decode is unblocking
348system.cpu.decode.UnblockCycles 496 # Number of cycles decode is unblocking
349system.cpu.decode.SquashCycles 725 # Number of cycles decode is squashing
350system.cpu.decode.BranchResolved 405 # Number of times decode resolved a branch
351system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction
349system.cpu.decode.SquashCycles 725 # Number of cycles decode is squashing
350system.cpu.decode.BranchResolved 405 # Number of times decode resolved a branch
351system.cpu.decode.BranchMispred 151 # Number of times decode detected a branch misprediction
352system.cpu.decode.DecodedInsts 24583 # Number of instructions handled by decode
352system.cpu.decode.DecodedInsts 24588 # Number of instructions handled by decode
353system.cpu.decode.SquashedInsts 377 # Number of squashed instructions handled by decode
354system.cpu.rename.SquashCycles 725 # Number of cycles rename is squashing
353system.cpu.decode.SquashedInsts 377 # Number of squashed instructions handled by decode
354system.cpu.rename.SquashCycles 725 # Number of cycles rename is squashing
355system.cpu.rename.IdleCycles 36872 # Number of cycles rename is idle
355system.cpu.rename.IdleCycles 36883 # Number of cycles rename is idle
356system.cpu.rename.BlockCycles 3499 # Number of cycles rename is blocking
357system.cpu.rename.serializeStallCycles 1435 # count of cycles rename stalled for serializing inst
356system.cpu.rename.BlockCycles 3499 # Number of cycles rename is blocking
357system.cpu.rename.serializeStallCycles 1435 # count of cycles rename stalled for serializing inst
358system.cpu.rename.RunCycles 4116 # Number of cycles rename is running
358system.cpu.rename.RunCycles 4115 # Number of cycles rename is running
359system.cpu.rename.UnblockCycles 5434 # Number of cycles rename is unblocking
360system.cpu.rename.RenamedInsts 23584 # Number of instructions processed by rename
361system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
359system.cpu.rename.UnblockCycles 5434 # Number of cycles rename is unblocking
360system.cpu.rename.RenamedInsts 23584 # Number of instructions processed by rename
361system.cpu.rename.ROBFullEvents 36 # Number of times rename has blocked due to ROB full
362system.cpu.rename.IQFullEvents 223 # Number of times rename has blocked due to IQ full
363system.cpu.rename.LQFullEvents 328 # Number of times rename has blocked due to LQ full
362system.cpu.rename.IQFullEvents 222 # Number of times rename has blocked due to IQ full
363system.cpu.rename.LQFullEvents 329 # Number of times rename has blocked due to LQ full
364system.cpu.rename.SQFullEvents 4703 # Number of times rename has blocked due to SQ full
365system.cpu.rename.RenamedOperands 17574 # Number of destination operands rename has renamed
366system.cpu.rename.RenameLookups 29532 # Number of register rename lookups that rename has made
367system.cpu.rename.int_rename_lookups 29514 # Number of integer rename lookups
368system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
369system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed
370system.cpu.rename.UndoneMaps 8420 # Number of HB maps that are undone due to squashing
371system.cpu.rename.serializingInsts 57 # count of serializing insts renamed
372system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed
364system.cpu.rename.SQFullEvents 4703 # Number of times rename has blocked due to SQ full
365system.cpu.rename.RenamedOperands 17574 # Number of destination operands rename has renamed
366system.cpu.rename.RenameLookups 29532 # Number of register rename lookups that rename has made
367system.cpu.rename.int_rename_lookups 29514 # Number of integer rename lookups
368system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
369system.cpu.rename.CommittedMaps 9154 # Number of HB maps that are committed
370system.cpu.rename.UndoneMaps 8420 # Number of HB maps that are undone due to squashing
371system.cpu.rename.serializingInsts 57 # count of serializing insts renamed
372system.cpu.rename.tempSerializingInsts 45 # count of temporary serializing insts renamed
373system.cpu.rename.skidInsts 1621 # count of insts added to the skid buffer
373system.cpu.rename.skidInsts 1617 # count of insts added to the skid buffer
374system.cpu.memDep0.insertedLoads 1925 # Number of loads inserted to the mem dependence unit.
375system.cpu.memDep0.insertedStores 1093 # Number of stores inserted to the mem dependence unit.
376system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
377system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
378system.cpu.memDep1.insertedLoads 2578 # Number of loads inserted to the mem dependence unit.
379system.cpu.memDep1.insertedStores 1286 # Number of stores inserted to the mem dependence unit.
380system.cpu.memDep1.conflictingLoads 15 # Number of conflicting loads.
381system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores.
382system.cpu.iq.iqInstsAdded 21800 # Number of instructions added to the IQ (excludes non-spec)
383system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ
374system.cpu.memDep0.insertedLoads 1925 # Number of loads inserted to the mem dependence unit.
375system.cpu.memDep0.insertedStores 1093 # Number of stores inserted to the mem dependence unit.
376system.cpu.memDep0.conflictingLoads 7 # Number of conflicting loads.
377system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores.
378system.cpu.memDep1.insertedLoads 2578 # Number of loads inserted to the mem dependence unit.
379system.cpu.memDep1.insertedStores 1286 # Number of stores inserted to the mem dependence unit.
380system.cpu.memDep1.conflictingLoads 15 # Number of conflicting loads.
381system.cpu.memDep1.conflictingStores 4 # Number of conflicting stores.
382system.cpu.iq.iqInstsAdded 21800 # Number of instructions added to the IQ (excludes non-spec)
383system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ
384system.cpu.iq.iqInstsIssued 19296 # Number of instructions issued
384system.cpu.iq.iqInstsIssued 19298 # Number of instructions issued
385system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued
386system.cpu.iq.iqSquashedInstsExamined 9080 # Number of squashed instructions iterated over during squash; mainly for profiling
385system.cpu.iq.iqSquashedInstsIssued 51 # Number of squashed instructions issued
386system.cpu.iq.iqSquashedInstsExamined 9080 # Number of squashed instructions iterated over during squash; mainly for profiling
387system.cpu.iq.iqSquashedOperandsExamined 4753 # Number of squashed operands that are examined and possibly removed from graph
387system.cpu.iq.iqSquashedOperandsExamined 4750 # Number of squashed operands that are examined and possibly removed from graph
388system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
388system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed
389system.cpu.iq.issued_per_cycle::samples 26300 # Number of insts issued each cycle
390system.cpu.iq.issued_per_cycle::mean 0.733688 # Number of insts issued each cycle
391system.cpu.iq.issued_per_cycle::stdev 1.450617 # Number of insts issued each cycle
389system.cpu.iq.issued_per_cycle::samples 26305 # Number of insts issued each cycle
390system.cpu.iq.issued_per_cycle::mean 0.733625 # Number of insts issued each cycle
391system.cpu.iq.issued_per_cycle::stdev 1.450843 # Number of insts issued each cycle
392system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
392system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
393system.cpu.iq.issued_per_cycle::0 18970 72.13% 72.13% # Number of insts issued each cycle
394system.cpu.iq.issued_per_cycle::1 2362 8.98% 81.11% # Number of insts issued each cycle
395system.cpu.iq.issued_per_cycle::2 1626 6.18% 87.29% # Number of insts issued each cycle
396system.cpu.iq.issued_per_cycle::3 1294 4.92% 92.21% # Number of insts issued each cycle
397system.cpu.iq.issued_per_cycle::4 1061 4.03% 96.25% # Number of insts issued each cycle
398system.cpu.iq.issued_per_cycle::5 563 2.14% 98.39% # Number of insts issued each cycle
393system.cpu.iq.issued_per_cycle::0 18975 72.13% 72.13% # Number of insts issued each cycle
394system.cpu.iq.issued_per_cycle::1 2364 8.99% 81.12% # Number of insts issued each cycle
395system.cpu.iq.issued_per_cycle::2 1624 6.17% 87.30% # Number of insts issued each cycle
396system.cpu.iq.issued_per_cycle::3 1293 4.92% 92.21% # Number of insts issued each cycle
397system.cpu.iq.issued_per_cycle::4 1059 4.03% 96.24% # Number of insts issued each cycle
398system.cpu.iq.issued_per_cycle::5 566 2.15% 98.39% # Number of insts issued each cycle
399system.cpu.iq.issued_per_cycle::6 282 1.07% 99.46% # Number of insts issued each cycle
400system.cpu.iq.issued_per_cycle::7 87 0.33% 99.79% # Number of insts issued each cycle
401system.cpu.iq.issued_per_cycle::8 55 0.21% 100.00% # Number of insts issued each cycle
402system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
403system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
404system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
399system.cpu.iq.issued_per_cycle::6 282 1.07% 99.46% # Number of insts issued each cycle
400system.cpu.iq.issued_per_cycle::7 87 0.33% 99.79% # Number of insts issued each cycle
401system.cpu.iq.issued_per_cycle::8 55 0.21% 100.00% # Number of insts issued each cycle
402system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
403system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
404system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
405system.cpu.iq.issued_per_cycle::total 26300 # Number of insts issued each cycle
405system.cpu.iq.issued_per_cycle::total 26305 # Number of insts issued each cycle
406system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
406system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
407system.cpu.iq.fu_full::IntAlu 29 9.67% 9.67% # attempts to use FU when none available
408system.cpu.iq.fu_full::IntMult 0 0.00% 9.67% # attempts to use FU when none available
409system.cpu.iq.fu_full::IntDiv 0 0.00% 9.67% # attempts to use FU when none available
410system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.67% # attempts to use FU when none available
411system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.67% # attempts to use FU when none available
412system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.67% # attempts to use FU when none available
413system.cpu.iq.fu_full::FloatMult 0 0.00% 9.67% # attempts to use FU when none available
414system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available
415system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.67% # attempts to use FU when none available
416system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.67% # attempts to use FU when none available
417system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.67% # attempts to use FU when none available
418system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.67% # attempts to use FU when none available
419system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.67% # attempts to use FU when none available
420system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.67% # attempts to use FU when none available
421system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.67% # attempts to use FU when none available
422system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.67% # attempts to use FU when none available
423system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.67% # attempts to use FU when none available
424system.cpu.iq.fu_full::SimdMult 0 0.00% 9.67% # attempts to use FU when none available
425system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.67% # attempts to use FU when none available
426system.cpu.iq.fu_full::SimdShift 0 0.00% 9.67% # attempts to use FU when none available
427system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.67% # attempts to use FU when none available
428system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.67% # attempts to use FU when none available
429system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.67% # attempts to use FU when none available
430system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.67% # attempts to use FU when none available
431system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.67% # attempts to use FU when none available
432system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.67% # attempts to use FU when none available
433system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.67% # attempts to use FU when none available
434system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.67% # attempts to use FU when none available
435system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.67% # attempts to use FU when none available
436system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.67% # attempts to use FU when none available
437system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.67% # attempts to use FU when none available
438system.cpu.iq.fu_full::MemRead 191 63.67% 73.33% # attempts to use FU when none available
439system.cpu.iq.fu_full::MemWrite 77 25.67% 99.00% # attempts to use FU when none available
440system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.00% # attempts to use FU when none available
441system.cpu.iq.fu_full::FloatMemWrite 3 1.00% 100.00% # attempts to use FU when none available
407system.cpu.iq.fu_full::IntAlu 29 9.60% 9.60% # attempts to use FU when none available
408system.cpu.iq.fu_full::IntMult 0 0.00% 9.60% # attempts to use FU when none available
409system.cpu.iq.fu_full::IntDiv 0 0.00% 9.60% # attempts to use FU when none available
410system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.60% # attempts to use FU when none available
411system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.60% # attempts to use FU when none available
412system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.60% # attempts to use FU when none available
413system.cpu.iq.fu_full::FloatMult 0 0.00% 9.60% # attempts to use FU when none available
414system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available
415system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.60% # attempts to use FU when none available
416system.cpu.iq.fu_full::FloatMisc 0 0.00% 9.60% # attempts to use FU when none available
417system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.60% # attempts to use FU when none available
418system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.60% # attempts to use FU when none available
419system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.60% # attempts to use FU when none available
420system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.60% # attempts to use FU when none available
421system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.60% # attempts to use FU when none available
422system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.60% # attempts to use FU when none available
423system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.60% # attempts to use FU when none available
424system.cpu.iq.fu_full::SimdMult 0 0.00% 9.60% # attempts to use FU when none available
425system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.60% # attempts to use FU when none available
426system.cpu.iq.fu_full::SimdShift 0 0.00% 9.60% # attempts to use FU when none available
427system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.60% # attempts to use FU when none available
428system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.60% # attempts to use FU when none available
429system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.60% # attempts to use FU when none available
430system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.60% # attempts to use FU when none available
431system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.60% # attempts to use FU when none available
432system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.60% # attempts to use FU when none available
433system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.60% # attempts to use FU when none available
434system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.60% # attempts to use FU when none available
435system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.60% # attempts to use FU when none available
436system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.60% # attempts to use FU when none available
437system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.60% # attempts to use FU when none available
438system.cpu.iq.fu_full::MemRead 193 63.91% 73.51% # attempts to use FU when none available
439system.cpu.iq.fu_full::MemWrite 77 25.50% 99.01% # attempts to use FU when none available
440system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.01% # attempts to use FU when none available
441system.cpu.iq.fu_full::FloatMemWrite 3 0.99% 100.00% # attempts to use FU when none available
442system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
443system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
444system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
442system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
443system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
444system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
445system.cpu.iq.FU_type_0::IntAlu 5884 66.04% 66.06% # Type of FU issued
446system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.07% # Type of FU issued
447system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued
448system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.09% # Type of FU issued
449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.09% # Type of FU issued
450system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.09% # Type of FU issued
451system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.09% # Type of FU issued
452system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.09% # Type of FU issued
453system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.09% # Type of FU issued
454system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.09% # Type of FU issued
455system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.09% # Type of FU issued
456system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.09% # Type of FU issued
457system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.09% # Type of FU issued
458system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.09% # Type of FU issued
459system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.09% # Type of FU issued
460system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.09% # Type of FU issued
461system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.09% # Type of FU issued
462system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.09% # Type of FU issued
463system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.09% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.09% # Type of FU issued
465system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.09% # Type of FU issued
466system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.09% # Type of FU issued
467system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.09% # Type of FU issued
468system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.09% # Type of FU issued
469system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.09% # Type of FU issued
470system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.09% # Type of FU issued
471system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.09% # Type of FU issued
472system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.09% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.09% # Type of FU issued
474system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.09% # Type of FU issued
475system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.09% # Type of FU issued
445system.cpu.iq.FU_type_0::IntAlu 5886 66.05% 66.07% # Type of FU issued
446system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.08% # Type of FU issued
447system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.08% # Type of FU issued
448system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.10% # Type of FU issued
449system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.10% # Type of FU issued
450system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.10% # Type of FU issued
451system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.10% # Type of FU issued
452system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.10% # Type of FU issued
453system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.10% # Type of FU issued
454system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.10% # Type of FU issued
455system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.10% # Type of FU issued
456system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.10% # Type of FU issued
457system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.10% # Type of FU issued
458system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.10% # Type of FU issued
459system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.10% # Type of FU issued
460system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.10% # Type of FU issued
461system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.10% # Type of FU issued
462system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.10% # Type of FU issued
463system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.10% # Type of FU issued
464system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.10% # Type of FU issued
465system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.10% # Type of FU issued
466system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.10% # Type of FU issued
467system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.10% # Type of FU issued
468system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.10% # Type of FU issued
469system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.10% # Type of FU issued
470system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.10% # Type of FU issued
471system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.10% # Type of FU issued
472system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.10% # Type of FU issued
473system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.10% # Type of FU issued
474system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.10% # Type of FU issued
475system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.10% # Type of FU issued
476system.cpu.iq.FU_type_0::MemRead 2014 22.60% 88.70% # Type of FU issued
477system.cpu.iq.FU_type_0::MemWrite 999 11.21% 99.91% # Type of FU issued
478system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.92% # Type of FU issued
479system.cpu.iq.FU_type_0::FloatMemWrite 7 0.08% 100.00% # Type of FU issued
480system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
481system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
476system.cpu.iq.FU_type_0::MemRead 2014 22.60% 88.70% # Type of FU issued
477system.cpu.iq.FU_type_0::MemWrite 999 11.21% 99.91% # Type of FU issued
478system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.92% # Type of FU issued
479system.cpu.iq.FU_type_0::FloatMemWrite 7 0.08% 100.00% # Type of FU issued
480system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
481system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
482system.cpu.iq.FU_type_0::total 8910 # Type of FU issued
482system.cpu.iq.FU_type_0::total 8912 # Type of FU issued
483system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
484system.cpu.iq.FU_type_1::IntAlu 6849 65.94% 65.96% # Type of FU issued
485system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued
486system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.97% # Type of FU issued
487system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Type of FU issued
488system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued
489system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued
490system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued
491system.cpu.iq.FU_type_1::FloatMultAcc 0 0.00% 65.99% # Type of FU issued
492system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued
493system.cpu.iq.FU_type_1::FloatMisc 0 0.00% 65.99% # Type of FU issued
494system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued
495system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued
496system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued
497system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.99% # Type of FU issued
498system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.99% # Type of FU issued
499system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.99% # Type of FU issued
500system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.99% # Type of FU issued
501system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.99% # Type of FU issued
502system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.99% # Type of FU issued
503system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.99% # Type of FU issued
504system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued
505system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.99% # Type of FU issued
506system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued
507system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued
508system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued
509system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued
510system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued
511system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued
512system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued
513system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued
514system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued
515system.cpu.iq.FU_type_1::MemRead 2410 23.20% 89.20% # Type of FU issued
516system.cpu.iq.FU_type_1::MemWrite 1114 10.73% 99.92% # Type of FU issued
517system.cpu.iq.FU_type_1::FloatMemRead 1 0.01% 99.93% # Type of FU issued
518system.cpu.iq.FU_type_1::FloatMemWrite 7 0.07% 100.00% # Type of FU issued
519system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
520system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
521system.cpu.iq.FU_type_1::total 10386 # Type of FU issued
483system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
484system.cpu.iq.FU_type_1::IntAlu 6849 65.94% 65.96% # Type of FU issued
485system.cpu.iq.FU_type_1::IntMult 1 0.01% 65.97% # Type of FU issued
486system.cpu.iq.FU_type_1::IntDiv 0 0.00% 65.97% # Type of FU issued
487system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 65.99% # Type of FU issued
488system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 65.99% # Type of FU issued
489system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 65.99% # Type of FU issued
490system.cpu.iq.FU_type_1::FloatMult 0 0.00% 65.99% # Type of FU issued
491system.cpu.iq.FU_type_1::FloatMultAcc 0 0.00% 65.99% # Type of FU issued
492system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 65.99% # Type of FU issued
493system.cpu.iq.FU_type_1::FloatMisc 0 0.00% 65.99% # Type of FU issued
494system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 65.99% # Type of FU issued
495system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 65.99% # Type of FU issued
496system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 65.99% # Type of FU issued
497system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 65.99% # Type of FU issued
498system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 65.99% # Type of FU issued
499system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 65.99% # Type of FU issued
500system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 65.99% # Type of FU issued
501system.cpu.iq.FU_type_1::SimdMult 0 0.00% 65.99% # Type of FU issued
502system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 65.99% # Type of FU issued
503system.cpu.iq.FU_type_1::SimdShift 0 0.00% 65.99% # Type of FU issued
504system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 65.99% # Type of FU issued
505system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 65.99% # Type of FU issued
506system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 65.99% # Type of FU issued
507system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 65.99% # Type of FU issued
508system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 65.99% # Type of FU issued
509system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 65.99% # Type of FU issued
510system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 65.99% # Type of FU issued
511system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 65.99% # Type of FU issued
512system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 65.99% # Type of FU issued
513system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 65.99% # Type of FU issued
514system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 65.99% # Type of FU issued
515system.cpu.iq.FU_type_1::MemRead 2410 23.20% 89.20% # Type of FU issued
516system.cpu.iq.FU_type_1::MemWrite 1114 10.73% 99.92% # Type of FU issued
517system.cpu.iq.FU_type_1::FloatMemRead 1 0.01% 99.93% # Type of FU issued
518system.cpu.iq.FU_type_1::FloatMemWrite 7 0.07% 100.00% # Type of FU issued
519system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
520system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
521system.cpu.iq.FU_type_1::total 10386 # Type of FU issued
522system.cpu.iq.FU_type::total 19296 0.00% 0.00% # Type of FU issued
523system.cpu.iq.rate 0.361863 # Inst issue rate
524system.cpu.iq.fu_busy_cnt::0 152 # FU busy when requested
522system.cpu.iq.FU_type::total 19298 0.00% 0.00% # Type of FU issued
523system.cpu.iq.rate 0.361901 # Inst issue rate
524system.cpu.iq.fu_busy_cnt::0 154 # FU busy when requested
525system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested
525system.cpu.iq.fu_busy_cnt::1 148 # FU busy when requested
526system.cpu.iq.fu_busy_cnt::total 300 # FU busy when requested
527system.cpu.iq.fu_busy_rate::0 0.007877 # FU busy rate (busy events/executed inst)
528system.cpu.iq.fu_busy_rate::1 0.007670 # FU busy rate (busy events/executed inst)
529system.cpu.iq.fu_busy_rate::total 0.015547 # FU busy rate (busy events/executed inst)
530system.cpu.iq.int_inst_queue_reads 65200 # Number of integer instruction queue reads
526system.cpu.iq.fu_busy_cnt::total 302 # FU busy when requested
527system.cpu.iq.fu_busy_rate::0 0.007980 # FU busy rate (busy events/executed inst)
528system.cpu.iq.fu_busy_rate::1 0.007669 # FU busy rate (busy events/executed inst)
529system.cpu.iq.fu_busy_rate::total 0.015649 # FU busy rate (busy events/executed inst)
530system.cpu.iq.int_inst_queue_reads 65211 # Number of integer instruction queue reads
531system.cpu.iq.int_inst_queue_writes 30942 # Number of integer instruction queue writes
531system.cpu.iq.int_inst_queue_writes 30942 # Number of integer instruction queue writes
532system.cpu.iq.int_inst_queue_wakeup_accesses 17504 # Number of integer instruction queue wakeup accesses
532system.cpu.iq.int_inst_queue_wakeup_accesses 17509 # Number of integer instruction queue wakeup accesses
533system.cpu.iq.fp_inst_queue_reads 43 # Number of floating instruction queue reads
534system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
535system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
533system.cpu.iq.fp_inst_queue_reads 43 # Number of floating instruction queue reads
534system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
535system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
536system.cpu.iq.int_alu_accesses 19569 # Number of integer alu accesses
536system.cpu.iq.int_alu_accesses 19573 # Number of integer alu accesses
537system.cpu.iq.fp_alu_accesses 23 # Number of floating point alu accesses
538system.cpu.iew.lsq.thread0.forwLoads 39 # Number of loads that had data forwarded from stores
539system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
540system.cpu.iew.lsq.thread0.squashedLoads 740 # Number of loads squashed
541system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
542system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
543system.cpu.iew.lsq.thread0.squashedStores 228 # Number of stores squashed
544system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
545system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
546system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
547system.cpu.iew.lsq.thread0.cacheBlocked 290 # Number of times an access to memory failed due to the cache being blocked
548system.cpu.iew.lsq.thread1.forwLoads 97 # Number of loads that had data forwarded from stores
549system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
550system.cpu.iew.lsq.thread1.squashedLoads 1393 # Number of loads squashed
551system.cpu.iew.lsq.thread1.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed
552system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations
553system.cpu.iew.lsq.thread1.squashedStores 421 # Number of stores squashed
554system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
555system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
556system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
557system.cpu.iew.lsq.thread1.cacheBlocked 234 # Number of times an access to memory failed due to the cache being blocked
558system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
559system.cpu.iew.iewSquashCycles 725 # Number of cycles IEW is squashing
560system.cpu.iew.iewBlockCycles 1992 # Number of cycles IEW is blocking
561system.cpu.iew.iewUnblockCycles 420 # Number of cycles IEW is unblocking
562system.cpu.iew.iewDispatchedInsts 21985 # Number of instructions dispatched to IQ
563system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch
564system.cpu.iew.iewDispLoadInsts 4503 # Number of dispatched load instructions
565system.cpu.iew.iewDispStoreInsts 2379 # Number of dispatched store instructions
566system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions
567system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall
568system.cpu.iew.iewLSQFullEvents 390 # Number of times the LSQ has become full, causing a stall
569system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations
570system.cpu.iew.predictedTakenIncorrect 134 # Number of branches that were predicted taken incorrectly
571system.cpu.iew.predictedNotTakenIncorrect 638 # Number of branches that were predicted not taken incorrectly
572system.cpu.iew.branchMispredicts 772 # Number of branch mispredicts detected at execute
537system.cpu.iq.fp_alu_accesses 23 # Number of floating point alu accesses
538system.cpu.iew.lsq.thread0.forwLoads 39 # Number of loads that had data forwarded from stores
539system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
540system.cpu.iew.lsq.thread0.squashedLoads 740 # Number of loads squashed
541system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
542system.cpu.iew.lsq.thread0.memOrderViolation 13 # Number of memory ordering violations
543system.cpu.iew.lsq.thread0.squashedStores 228 # Number of stores squashed
544system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
545system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
546system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
547system.cpu.iew.lsq.thread0.cacheBlocked 290 # Number of times an access to memory failed due to the cache being blocked
548system.cpu.iew.lsq.thread1.forwLoads 97 # Number of loads that had data forwarded from stores
549system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
550system.cpu.iew.lsq.thread1.squashedLoads 1393 # Number of loads squashed
551system.cpu.iew.lsq.thread1.ignoredResponses 14 # Number of memory responses ignored because the instruction is squashed
552system.cpu.iew.lsq.thread1.memOrderViolation 19 # Number of memory ordering violations
553system.cpu.iew.lsq.thread1.squashedStores 421 # Number of stores squashed
554system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
555system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
556system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
557system.cpu.iew.lsq.thread1.cacheBlocked 234 # Number of times an access to memory failed due to the cache being blocked
558system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
559system.cpu.iew.iewSquashCycles 725 # Number of cycles IEW is squashing
560system.cpu.iew.iewBlockCycles 1992 # Number of cycles IEW is blocking
561system.cpu.iew.iewUnblockCycles 420 # Number of cycles IEW is unblocking
562system.cpu.iew.iewDispatchedInsts 21985 # Number of instructions dispatched to IQ
563system.cpu.iew.iewDispSquashedInsts 174 # Number of squashed instructions skipped by dispatch
564system.cpu.iew.iewDispLoadInsts 4503 # Number of dispatched load instructions
565system.cpu.iew.iewDispStoreInsts 2379 # Number of dispatched store instructions
566system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions
567system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall
568system.cpu.iew.iewLSQFullEvents 390 # Number of times the LSQ has become full, causing a stall
569system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations
570system.cpu.iew.predictedTakenIncorrect 134 # Number of branches that were predicted taken incorrectly
571system.cpu.iew.predictedNotTakenIncorrect 638 # Number of branches that were predicted not taken incorrectly
572system.cpu.iew.branchMispredicts 772 # Number of branch mispredicts detected at execute
573system.cpu.iew.iewExecutedInsts 18585 # Number of executed instructions
574system.cpu.iew.iewExecLoadInsts::0 1945 # Number of load instructions executed
573system.cpu.iew.iewExecutedInsts 18590 # Number of executed instructions
574system.cpu.iew.iewExecLoadInsts::0 1946 # Number of load instructions executed
575system.cpu.iew.iewExecLoadInsts::1 2264 # Number of load instructions executed
575system.cpu.iew.iewExecLoadInsts::1 2264 # Number of load instructions executed
576system.cpu.iew.iewExecLoadInsts::total 4209 # Number of load instructions executed
577system.cpu.iew.iewExecSquashedInsts 711 # Number of squashed instructions skipped in execute
576system.cpu.iew.iewExecLoadInsts::total 4210 # Number of load instructions executed
577system.cpu.iew.iewExecSquashedInsts 708 # Number of squashed instructions skipped in execute
578system.cpu.iew.exec_swp::0 0 # number of swp insts executed
579system.cpu.iew.exec_swp::1 0 # number of swp insts executed
580system.cpu.iew.exec_swp::total 0 # number of swp insts executed
581system.cpu.iew.exec_nop::0 63 # number of nop insts executed
582system.cpu.iew.exec_nop::1 71 # number of nop insts executed
583system.cpu.iew.exec_nop::total 134 # number of nop insts executed
578system.cpu.iew.exec_swp::0 0 # number of swp insts executed
579system.cpu.iew.exec_swp::1 0 # number of swp insts executed
580system.cpu.iew.exec_swp::total 0 # number of swp insts executed
581system.cpu.iew.exec_nop::0 63 # number of nop insts executed
582system.cpu.iew.exec_nop::1 71 # number of nop insts executed
583system.cpu.iew.exec_nop::total 134 # number of nop insts executed
584system.cpu.iew.exec_refs::0 2942 # number of memory reference insts executed
584system.cpu.iew.exec_refs::0 2943 # number of memory reference insts executed
585system.cpu.iew.exec_refs::1 3338 # number of memory reference insts executed
585system.cpu.iew.exec_refs::1 3338 # number of memory reference insts executed
586system.cpu.iew.exec_refs::total 6280 # number of memory reference insts executed
586system.cpu.iew.exec_refs::total 6281 # number of memory reference insts executed
587system.cpu.iew.exec_branches::0 1393 # Number of branches executed
588system.cpu.iew.exec_branches::1 1580 # Number of branches executed
589system.cpu.iew.exec_branches::total 2973 # Number of branches executed
590system.cpu.iew.exec_stores::0 997 # Number of stores executed
591system.cpu.iew.exec_stores::1 1074 # Number of stores executed
592system.cpu.iew.exec_stores::total 2071 # Number of stores executed
587system.cpu.iew.exec_branches::0 1393 # Number of branches executed
588system.cpu.iew.exec_branches::1 1580 # Number of branches executed
589system.cpu.iew.exec_branches::total 2973 # Number of branches executed
590system.cpu.iew.exec_stores::0 997 # Number of stores executed
591system.cpu.iew.exec_stores::1 1074 # Number of stores executed
592system.cpu.iew.exec_stores::total 2071 # Number of stores executed
593system.cpu.iew.exec_rate 0.348530 # Inst execution rate
594system.cpu.iew.wb_sent::0 8281 # cumulative count of insts sent to commit
593system.cpu.iew.exec_rate 0.348624 # Inst execution rate
594system.cpu.iew.wb_sent::0 8287 # cumulative count of insts sent to commit
595system.cpu.iew.wb_sent::1 9496 # cumulative count of insts sent to commit
595system.cpu.iew.wb_sent::1 9496 # cumulative count of insts sent to commit
596system.cpu.iew.wb_sent::total 17777 # cumulative count of insts sent to commit
597system.cpu.iew.wb_count::0 8197 # cumulative count of insts written-back
596system.cpu.iew.wb_sent::total 17783 # cumulative count of insts sent to commit
597system.cpu.iew.wb_count::0 8202 # cumulative count of insts written-back
598system.cpu.iew.wb_count::1 9327 # cumulative count of insts written-back
598system.cpu.iew.wb_count::1 9327 # cumulative count of insts written-back
599system.cpu.iew.wb_count::total 17524 # cumulative count of insts written-back
600system.cpu.iew.wb_producers::0 4340 # num instructions producing a value
601system.cpu.iew.wb_producers::1 4919 # num instructions producing a value
602system.cpu.iew.wb_producers::total 9259 # num instructions producing a value
603system.cpu.iew.wb_consumers::0 5879 # num instructions consuming a value
604system.cpu.iew.wb_consumers::1 6619 # num instructions consuming a value
605system.cpu.iew.wb_consumers::total 12498 # num instructions consuming a value
606system.cpu.iew.wb_rate::0 0.153721 # insts written-back per cycle
599system.cpu.iew.wb_count::total 17529 # cumulative count of insts written-back
600system.cpu.iew.wb_producers::0 4343 # num instructions producing a value
601system.cpu.iew.wb_producers::1 4920 # num instructions producing a value
602system.cpu.iew.wb_producers::total 9263 # num instructions producing a value
603system.cpu.iew.wb_consumers::0 5887 # num instructions consuming a value
604system.cpu.iew.wb_consumers::1 6620 # num instructions consuming a value
605system.cpu.iew.wb_consumers::total 12507 # num instructions consuming a value
606system.cpu.iew.wb_rate::0 0.153814 # insts written-back per cycle
607system.cpu.iew.wb_rate::1 0.174912 # insts written-back per cycle
607system.cpu.iew.wb_rate::1 0.174912 # insts written-back per cycle
608system.cpu.iew.wb_rate::total 0.328633 # insts written-back per cycle
609system.cpu.iew.wb_fanout::0 0.738221 # average fanout of values written-back
610system.cpu.iew.wb_fanout::1 0.743164 # average fanout of values written-back
611system.cpu.iew.wb_fanout::total 0.740839 # average fanout of values written-back
608system.cpu.iew.wb_rate::total 0.328726 # insts written-back per cycle
609system.cpu.iew.wb_fanout::0 0.737727 # average fanout of values written-back
610system.cpu.iew.wb_fanout::1 0.743202 # average fanout of values written-back
611system.cpu.iew.wb_fanout::total 0.740625 # average fanout of values written-back
612system.cpu.commit.commitSquashedInsts 9130 # The number of squashed insts skipped by commit
613system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
614system.cpu.commit.branchMispredicts 646 # The number of times a branch was mispredicted
612system.cpu.commit.commitSquashedInsts 9130 # The number of squashed insts skipped by commit
613system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
614system.cpu.commit.branchMispredicts 646 # The number of times a branch was mispredicted
615system.cpu.commit.committed_per_cycle::samples 26282 # Number of insts commited each cycle
616system.cpu.commit.committed_per_cycle::mean 0.487178 # Number of insts commited each cycle
617system.cpu.commit.committed_per_cycle::stdev 1.404713 # Number of insts commited each cycle
615system.cpu.commit.committed_per_cycle::samples 26287 # Number of insts commited each cycle
616system.cpu.commit.committed_per_cycle::mean 0.487085 # Number of insts commited each cycle
617system.cpu.commit.committed_per_cycle::stdev 1.404867 # Number of insts commited each cycle
618system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
618system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
619system.cpu.commit.committed_per_cycle::0 21298 81.04% 81.04% # Number of insts commited each cycle
620system.cpu.commit.committed_per_cycle::1 2499 9.51% 90.54% # Number of insts commited each cycle
619system.cpu.commit.committed_per_cycle::0 21303 81.04% 81.04% # Number of insts commited each cycle
620system.cpu.commit.committed_per_cycle::1 2500 9.51% 90.55% # Number of insts commited each cycle
621system.cpu.commit.committed_per_cycle::2 926 3.52% 94.07% # Number of insts commited each cycle
621system.cpu.commit.committed_per_cycle::2 926 3.52% 94.07% # Number of insts commited each cycle
622system.cpu.commit.committed_per_cycle::3 403 1.53% 95.60% # Number of insts commited each cycle
622system.cpu.commit.committed_per_cycle::3 402 1.53% 95.60% # Number of insts commited each cycle
623system.cpu.commit.committed_per_cycle::4 249 0.95% 96.55% # Number of insts commited each cycle
623system.cpu.commit.committed_per_cycle::4 249 0.95% 96.55% # Number of insts commited each cycle
624system.cpu.commit.committed_per_cycle::5 154 0.59% 97.13% # Number of insts commited each cycle
625system.cpu.commit.committed_per_cycle::6 215 0.82% 97.95% # Number of insts commited each cycle
624system.cpu.commit.committed_per_cycle::5 154 0.59% 97.14% # Number of insts commited each cycle
625system.cpu.commit.committed_per_cycle::6 214 0.81% 97.95% # Number of insts commited each cycle
626system.cpu.commit.committed_per_cycle::7 116 0.44% 98.39% # Number of insts commited each cycle
626system.cpu.commit.committed_per_cycle::7 116 0.44% 98.39% # Number of insts commited each cycle
627system.cpu.commit.committed_per_cycle::8 422 1.61% 100.00% # Number of insts commited each cycle
627system.cpu.commit.committed_per_cycle::8 423 1.61% 100.00% # Number of insts commited each cycle
628system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
629system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
630system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
628system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
629system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
630system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
631system.cpu.commit.committed_per_cycle::total 26282 # Number of insts commited each cycle
631system.cpu.commit.committed_per_cycle::total 26287 # Number of insts commited each cycle
632system.cpu.commit.committedInsts::0 6402 # Number of instructions committed
633system.cpu.commit.committedInsts::1 6402 # Number of instructions committed
634system.cpu.commit.committedInsts::total 12804 # Number of instructions committed
635system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed
636system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed
637system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed
638system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
639system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
640system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
641system.cpu.commit.refs::0 2050 # Number of memory references committed
642system.cpu.commit.refs::1 2050 # Number of memory references committed
643system.cpu.commit.refs::total 4100 # Number of memory references committed
644system.cpu.commit.loads::0 1185 # Number of loads committed
645system.cpu.commit.loads::1 1185 # Number of loads committed
646system.cpu.commit.loads::total 2370 # Number of loads committed
647system.cpu.commit.membars::0 0 # Number of memory barriers committed
648system.cpu.commit.membars::1 0 # Number of memory barriers committed
649system.cpu.commit.membars::total 0 # Number of memory barriers committed
650system.cpu.commit.branches::0 1056 # Number of branches committed
651system.cpu.commit.branches::1 1056 # Number of branches committed
652system.cpu.commit.branches::total 2112 # Number of branches committed
653system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
654system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
655system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
656system.cpu.commit.int_insts::0 6319 # Number of committed integer instructions.
657system.cpu.commit.int_insts::1 6319 # Number of committed integer instructions.
658system.cpu.commit.int_insts::total 12638 # Number of committed integer instructions.
659system.cpu.commit.function_calls::0 127 # Number of function calls committed.
660system.cpu.commit.function_calls::1 127 # Number of function calls committed.
661system.cpu.commit.function_calls::total 254 # Number of function calls committed.
662system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
663system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction
664system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction
665system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction
666system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction
667system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction
668system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction
669system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction
670system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction
671system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction
672system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction
673system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
674system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction
675system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
676system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction
677system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction
678system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction
679system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction
680system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction
681system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
682system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction
683system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
684system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
685system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
686system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
687system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
688system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
689system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
690system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
691system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
692system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
693system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
694system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction
695system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction
696system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction
697system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
698system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
699system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
700system.cpu.commit.op_class_0::total 6402 # Class of committed instruction
701system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction
702system.cpu.commit.op_class_1::IntAlu 4330 67.64% 67.93% # Class of committed instruction
703system.cpu.commit.op_class_1::IntMult 1 0.02% 67.95% # Class of committed instruction
704system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.95% # Class of committed instruction
705system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Class of committed instruction
706system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction
707system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction
708system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction
709system.cpu.commit.op_class_1::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction
710system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction
711system.cpu.commit.op_class_1::FloatMisc 0 0.00% 67.98% # Class of committed instruction
712system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
713system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction
714system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
715system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.98% # Class of committed instruction
716system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.98% # Class of committed instruction
717system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.98% # Class of committed instruction
718system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.98% # Class of committed instruction
719system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.98% # Class of committed instruction
720system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
721system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.98% # Class of committed instruction
722system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
723system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
724system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
725system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
726system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
727system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
728system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
729system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
730system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
731system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
732system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
733system.cpu.commit.op_class_1::MemRead 1184 18.49% 86.47% # Class of committed instruction
734system.cpu.commit.op_class_1::MemWrite 858 13.40% 99.88% # Class of committed instruction
735system.cpu.commit.op_class_1::FloatMemRead 1 0.02% 99.89% # Class of committed instruction
736system.cpu.commit.op_class_1::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
737system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction
738system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
739system.cpu.commit.op_class_1::total 6402 # Class of committed instruction
740system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction
632system.cpu.commit.committedInsts::0 6402 # Number of instructions committed
633system.cpu.commit.committedInsts::1 6402 # Number of instructions committed
634system.cpu.commit.committedInsts::total 12804 # Number of instructions committed
635system.cpu.commit.committedOps::0 6402 # Number of ops (including micro ops) committed
636system.cpu.commit.committedOps::1 6402 # Number of ops (including micro ops) committed
637system.cpu.commit.committedOps::total 12804 # Number of ops (including micro ops) committed
638system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
639system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
640system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
641system.cpu.commit.refs::0 2050 # Number of memory references committed
642system.cpu.commit.refs::1 2050 # Number of memory references committed
643system.cpu.commit.refs::total 4100 # Number of memory references committed
644system.cpu.commit.loads::0 1185 # Number of loads committed
645system.cpu.commit.loads::1 1185 # Number of loads committed
646system.cpu.commit.loads::total 2370 # Number of loads committed
647system.cpu.commit.membars::0 0 # Number of memory barriers committed
648system.cpu.commit.membars::1 0 # Number of memory barriers committed
649system.cpu.commit.membars::total 0 # Number of memory barriers committed
650system.cpu.commit.branches::0 1056 # Number of branches committed
651system.cpu.commit.branches::1 1056 # Number of branches committed
652system.cpu.commit.branches::total 2112 # Number of branches committed
653system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
654system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
655system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
656system.cpu.commit.int_insts::0 6319 # Number of committed integer instructions.
657system.cpu.commit.int_insts::1 6319 # Number of committed integer instructions.
658system.cpu.commit.int_insts::total 12638 # Number of committed integer instructions.
659system.cpu.commit.function_calls::0 127 # Number of function calls committed.
660system.cpu.commit.function_calls::1 127 # Number of function calls committed.
661system.cpu.commit.function_calls::total 254 # Number of function calls committed.
662system.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction
663system.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction
664system.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction
665system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction
666system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction
667system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction
668system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction
669system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction
670system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction
671system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction
672system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction
673system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
674system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction
675system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
676system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction
677system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction
678system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction
679system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction
680system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction
681system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
682system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction
683system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
684system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
685system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
686system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
687system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
688system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
689system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
690system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
691system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
692system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
693system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
694system.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction
695system.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction
696system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction
697system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
698system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
699system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
700system.cpu.commit.op_class_0::total 6402 # Class of committed instruction
701system.cpu.commit.op_class_1::No_OpClass 19 0.30% 0.30% # Class of committed instruction
702system.cpu.commit.op_class_1::IntAlu 4330 67.64% 67.93% # Class of committed instruction
703system.cpu.commit.op_class_1::IntMult 1 0.02% 67.95% # Class of committed instruction
704system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.95% # Class of committed instruction
705system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.98% # Class of committed instruction
706system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.98% # Class of committed instruction
707system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.98% # Class of committed instruction
708system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.98% # Class of committed instruction
709system.cpu.commit.op_class_1::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction
710system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.98% # Class of committed instruction
711system.cpu.commit.op_class_1::FloatMisc 0 0.00% 67.98% # Class of committed instruction
712system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.98% # Class of committed instruction
713system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.98% # Class of committed instruction
714system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction
715system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.98% # Class of committed instruction
716system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.98% # Class of committed instruction
717system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.98% # Class of committed instruction
718system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.98% # Class of committed instruction
719system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.98% # Class of committed instruction
720system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction
721system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.98% # Class of committed instruction
722system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction
723system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.98% # Class of committed instruction
724system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction
725system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction
726system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction
727system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction
728system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction
729system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction
730system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction
731system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction
732system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction
733system.cpu.commit.op_class_1::MemRead 1184 18.49% 86.47% # Class of committed instruction
734system.cpu.commit.op_class_1::MemWrite 858 13.40% 99.88% # Class of committed instruction
735system.cpu.commit.op_class_1::FloatMemRead 1 0.02% 99.89% # Class of committed instruction
736system.cpu.commit.op_class_1::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
737system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction
738system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
739system.cpu.commit.op_class_1::total 6402 # Class of committed instruction
740system.cpu.commit.op_class::total 12804 0.00% 0.00% # Class of committed instruction
741system.cpu.commit.bw_lim_events 422 # number cycles where commit BW limit reached
742system.cpu.rob.rob_reads 113054 # The number of ROB reads
741system.cpu.commit.bw_lim_events 423 # number cycles where commit BW limit reached
742system.cpu.rob.rob_reads 113065 # The number of ROB reads
743system.cpu.rob.rob_writes 45570 # The number of ROB writes
744system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself
743system.cpu.rob.rob_writes 45570 # The number of ROB writes
744system.cpu.timesIdled 413 # Number of times that the entire CPU went into an idle state and unscheduled itself
745system.cpu.idleCycles 27024 # Total number of cycles that the CPU has spent unscheduled due to idling
745system.cpu.idleCycles 27019 # Total number of cycles that the CPU has spent unscheduled due to idling
746system.cpu.committedInsts::0 6385 # Number of Instructions Simulated
747system.cpu.committedInsts::1 6385 # Number of Instructions Simulated
748system.cpu.committedInsts::total 12770 # Number of Instructions Simulated
749system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated
750system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated
751system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated
752system.cpu.cpi::0 8.351449 # CPI: Cycles Per Instruction
753system.cpu.cpi::1 8.351449 # CPI: Cycles Per Instruction
754system.cpu.cpi_total 4.175724 # CPI: Total CPI of All Threads
755system.cpu.ipc::0 0.119740 # IPC: Instructions Per Cycle
756system.cpu.ipc::1 0.119740 # IPC: Instructions Per Cycle
757system.cpu.ipc_total 0.239479 # IPC: Total IPC of All Threads
746system.cpu.committedInsts::0 6385 # Number of Instructions Simulated
747system.cpu.committedInsts::1 6385 # Number of Instructions Simulated
748system.cpu.committedInsts::total 12770 # Number of Instructions Simulated
749system.cpu.committedOps::0 6385 # Number of Ops (including micro ops) Simulated
750system.cpu.committedOps::1 6385 # Number of Ops (including micro ops) Simulated
751system.cpu.committedOps::total 12770 # Number of Ops (including micro ops) Simulated
752system.cpu.cpi::0 8.351449 # CPI: Cycles Per Instruction
753system.cpu.cpi::1 8.351449 # CPI: Cycles Per Instruction
754system.cpu.cpi_total 4.175724 # CPI: Total CPI of All Threads
755system.cpu.ipc::0 0.119740 # IPC: Instructions Per Cycle
756system.cpu.ipc::1 0.119740 # IPC: Instructions Per Cycle
757system.cpu.ipc_total 0.239479 # IPC: Total IPC of All Threads
758system.cpu.int_regfile_reads 23475 # number of integer regfile reads
759system.cpu.int_regfile_writes 13132 # number of integer regfile writes
758system.cpu.int_regfile_reads 23483 # number of integer regfile reads
759system.cpu.int_regfile_writes 13138 # number of integer regfile writes
760system.cpu.fp_regfile_reads 16 # number of floating regfile reads
761system.cpu.fp_regfile_writes 4 # number of floating regfile writes
762system.cpu.misc_regfile_reads 2 # number of misc regfile reads
763system.cpu.misc_regfile_writes 2 # number of misc regfile writes
764system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
765system.cpu.dcache.tags.replacements::0 0 # number of replacements
766system.cpu.dcache.tags.replacements::1 0 # number of replacements
767system.cpu.dcache.tags.replacements::total 0 # number of replacements
760system.cpu.fp_regfile_reads 16 # number of floating regfile reads
761system.cpu.fp_regfile_writes 4 # number of floating regfile writes
762system.cpu.misc_regfile_reads 2 # number of misc regfile reads
763system.cpu.misc_regfile_writes 2 # number of misc regfile writes
764system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
765system.cpu.dcache.tags.replacements::0 0 # number of replacements
766system.cpu.dcache.tags.replacements::1 0 # number of replacements
767system.cpu.dcache.tags.replacements::total 0 # number of replacements
768system.cpu.dcache.tags.tagsinuse 216.020971 # Cycle average of tags in use
769system.cpu.dcache.tags.total_refs 4236 # Total number of references to valid blocks.
768system.cpu.dcache.tags.tagsinuse 216.020896 # Cycle average of tags in use
769system.cpu.dcache.tags.total_refs 4237 # Total number of references to valid blocks.
770system.cpu.dcache.tags.sampled_refs 342 # Sample count of references to valid blocks.
770system.cpu.dcache.tags.sampled_refs 342 # Sample count of references to valid blocks.
771system.cpu.dcache.tags.avg_refs 12.385965 # Average number of references to valid blocks.
771system.cpu.dcache.tags.avg_refs 12.388889 # Average number of references to valid blocks.
772system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
772system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
773system.cpu.dcache.tags.occ_blocks::cpu.data 216.020971 # Average occupied blocks per requestor
773system.cpu.dcache.tags.occ_blocks::cpu.data 216.020896 # Average occupied blocks per requestor
774system.cpu.dcache.tags.occ_percent::cpu.data 0.052739 # Average percentage of cache occupancy
775system.cpu.dcache.tags.occ_percent::total 0.052739 # Average percentage of cache occupancy
776system.cpu.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id
777system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
778system.cpu.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id
779system.cpu.dcache.tags.occ_task_id_percent::1024 0.083496 # Percentage of cache occupancy per task id
774system.cpu.dcache.tags.occ_percent::cpu.data 0.052739 # Average percentage of cache occupancy
775system.cpu.dcache.tags.occ_percent::total 0.052739 # Average percentage of cache occupancy
776system.cpu.dcache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id
777system.cpu.dcache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
778system.cpu.dcache.tags.age_task_id_blocks_1024::1 270 # Occupied blocks per task id
779system.cpu.dcache.tags.occ_task_id_percent::1024 0.083496 # Percentage of cache occupancy per task id
780system.cpu.dcache.tags.tag_accesses 10868 # Number of tag accesses
781system.cpu.dcache.tags.data_accesses 10868 # Number of data accesses
780system.cpu.dcache.tags.tag_accesses 10870 # Number of tag accesses
781system.cpu.dcache.tags.data_accesses 10870 # Number of data accesses
782system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
782system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
783system.cpu.dcache.ReadReq_hits::cpu.data 3224 # number of ReadReq hits
784system.cpu.dcache.ReadReq_hits::total 3224 # number of ReadReq hits
783system.cpu.dcache.ReadReq_hits::cpu.data 3225 # number of ReadReq hits
784system.cpu.dcache.ReadReq_hits::total 3225 # number of ReadReq hits
785system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits
786system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits
785system.cpu.dcache.WriteReq_hits::cpu.data 1012 # number of WriteReq hits
786system.cpu.dcache.WriteReq_hits::total 1012 # number of WriteReq hits
787system.cpu.dcache.demand_hits::cpu.data 4236 # number of demand (read+write) hits
788system.cpu.dcache.demand_hits::total 4236 # number of demand (read+write) hits
789system.cpu.dcache.overall_hits::cpu.data 4236 # number of overall hits
790system.cpu.dcache.overall_hits::total 4236 # number of overall hits
787system.cpu.dcache.demand_hits::cpu.data 4237 # number of demand (read+write) hits
788system.cpu.dcache.demand_hits::total 4237 # number of demand (read+write) hits
789system.cpu.dcache.overall_hits::cpu.data 4237 # number of overall hits
790system.cpu.dcache.overall_hits::total 4237 # number of overall hits
791system.cpu.dcache.ReadReq_misses::cpu.data 309 # number of ReadReq misses
792system.cpu.dcache.ReadReq_misses::total 309 # number of ReadReq misses
793system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses
794system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses
795system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses
796system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses
797system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses
798system.cpu.dcache.overall_misses::total 1027 # number of overall misses
799system.cpu.dcache.ReadReq_miss_latency::cpu.data 24016000 # number of ReadReq miss cycles
800system.cpu.dcache.ReadReq_miss_latency::total 24016000 # number of ReadReq miss cycles
801system.cpu.dcache.WriteReq_miss_latency::cpu.data 51330451 # number of WriteReq miss cycles
802system.cpu.dcache.WriteReq_miss_latency::total 51330451 # number of WriteReq miss cycles
803system.cpu.dcache.demand_miss_latency::cpu.data 75346451 # number of demand (read+write) miss cycles
804system.cpu.dcache.demand_miss_latency::total 75346451 # number of demand (read+write) miss cycles
805system.cpu.dcache.overall_miss_latency::cpu.data 75346451 # number of overall miss cycles
806system.cpu.dcache.overall_miss_latency::total 75346451 # number of overall miss cycles
791system.cpu.dcache.ReadReq_misses::cpu.data 309 # number of ReadReq misses
792system.cpu.dcache.ReadReq_misses::total 309 # number of ReadReq misses
793system.cpu.dcache.WriteReq_misses::cpu.data 718 # number of WriteReq misses
794system.cpu.dcache.WriteReq_misses::total 718 # number of WriteReq misses
795system.cpu.dcache.demand_misses::cpu.data 1027 # number of demand (read+write) misses
796system.cpu.dcache.demand_misses::total 1027 # number of demand (read+write) misses
797system.cpu.dcache.overall_misses::cpu.data 1027 # number of overall misses
798system.cpu.dcache.overall_misses::total 1027 # number of overall misses
799system.cpu.dcache.ReadReq_miss_latency::cpu.data 24016000 # number of ReadReq miss cycles
800system.cpu.dcache.ReadReq_miss_latency::total 24016000 # number of ReadReq miss cycles
801system.cpu.dcache.WriteReq_miss_latency::cpu.data 51330451 # number of WriteReq miss cycles
802system.cpu.dcache.WriteReq_miss_latency::total 51330451 # number of WriteReq miss cycles
803system.cpu.dcache.demand_miss_latency::cpu.data 75346451 # number of demand (read+write) miss cycles
804system.cpu.dcache.demand_miss_latency::total 75346451 # number of demand (read+write) miss cycles
805system.cpu.dcache.overall_miss_latency::cpu.data 75346451 # number of overall miss cycles
806system.cpu.dcache.overall_miss_latency::total 75346451 # number of overall miss cycles
807system.cpu.dcache.ReadReq_accesses::cpu.data 3533 # number of ReadReq accesses(hits+misses)
808system.cpu.dcache.ReadReq_accesses::total 3533 # number of ReadReq accesses(hits+misses)
807system.cpu.dcache.ReadReq_accesses::cpu.data 3534 # number of ReadReq accesses(hits+misses)
808system.cpu.dcache.ReadReq_accesses::total 3534 # number of ReadReq accesses(hits+misses)
809system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
810system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
809system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses)
810system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses)
811system.cpu.dcache.demand_accesses::cpu.data 5263 # number of demand (read+write) accesses
812system.cpu.dcache.demand_accesses::total 5263 # number of demand (read+write) accesses
813system.cpu.dcache.overall_accesses::cpu.data 5263 # number of overall (read+write) accesses
814system.cpu.dcache.overall_accesses::total 5263 # number of overall (read+write) accesses
815system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087461 # miss rate for ReadReq accesses
816system.cpu.dcache.ReadReq_miss_rate::total 0.087461 # miss rate for ReadReq accesses
811system.cpu.dcache.demand_accesses::cpu.data 5264 # number of demand (read+write) accesses
812system.cpu.dcache.demand_accesses::total 5264 # number of demand (read+write) accesses
813system.cpu.dcache.overall_accesses::cpu.data 5264 # number of overall (read+write) accesses
814system.cpu.dcache.overall_accesses::total 5264 # number of overall (read+write) accesses
815system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087436 # miss rate for ReadReq accesses
816system.cpu.dcache.ReadReq_miss_rate::total 0.087436 # miss rate for ReadReq accesses
817system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
818system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
817system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses
818system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses
819system.cpu.dcache.demand_miss_rate::cpu.data 0.195136 # miss rate for demand accesses
820system.cpu.dcache.demand_miss_rate::total 0.195136 # miss rate for demand accesses
821system.cpu.dcache.overall_miss_rate::cpu.data 0.195136 # miss rate for overall accesses
822system.cpu.dcache.overall_miss_rate::total 0.195136 # miss rate for overall accesses
819system.cpu.dcache.demand_miss_rate::cpu.data 0.195099 # miss rate for demand accesses
820system.cpu.dcache.demand_miss_rate::total 0.195099 # miss rate for demand accesses
821system.cpu.dcache.overall_miss_rate::cpu.data 0.195099 # miss rate for overall accesses
822system.cpu.dcache.overall_miss_rate::total 0.195099 # miss rate for overall accesses
823system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77721.682848 # average ReadReq miss latency
824system.cpu.dcache.ReadReq_avg_miss_latency::total 77721.682848 # average ReadReq miss latency
825system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71490.878830 # average WriteReq miss latency
826system.cpu.dcache.WriteReq_avg_miss_latency::total 71490.878830 # average WriteReq miss latency
827system.cpu.dcache.demand_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency
828system.cpu.dcache.demand_avg_miss_latency::total 73365.580331 # average overall miss latency
829system.cpu.dcache.overall_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency
830system.cpu.dcache.overall_avg_miss_latency::total 73365.580331 # average overall miss latency
831system.cpu.dcache.blocked_cycles::no_mshrs 5997 # number of cycles access was blocked
832system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
833system.cpu.dcache.blocked::no_mshrs 108 # number of cycles access was blocked
834system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
835system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.527778 # average number of cycles each access was blocked
836system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
837system.cpu.dcache.ReadReq_mshr_hits::cpu.data 110 # number of ReadReq MSHR hits
838system.cpu.dcache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits
839system.cpu.dcache.WriteReq_mshr_hits::cpu.data 574 # number of WriteReq MSHR hits
840system.cpu.dcache.WriteReq_mshr_hits::total 574 # number of WriteReq MSHR hits
841system.cpu.dcache.demand_mshr_hits::cpu.data 684 # number of demand (read+write) MSHR hits
842system.cpu.dcache.demand_mshr_hits::total 684 # number of demand (read+write) MSHR hits
843system.cpu.dcache.overall_mshr_hits::cpu.data 684 # number of overall MSHR hits
844system.cpu.dcache.overall_mshr_hits::total 684 # number of overall MSHR hits
845system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses
846system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses
847system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses
848system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses
849system.cpu.dcache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses
850system.cpu.dcache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses
851system.cpu.dcache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses
852system.cpu.dcache.overall_mshr_misses::total 343 # number of overall MSHR misses
853system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17847000 # number of ReadReq MSHR miss cycles
854system.cpu.dcache.ReadReq_mshr_miss_latency::total 17847000 # number of ReadReq MSHR miss cycles
855system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12459487 # number of WriteReq MSHR miss cycles
856system.cpu.dcache.WriteReq_mshr_miss_latency::total 12459487 # number of WriteReq MSHR miss cycles
857system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30306487 # number of demand (read+write) MSHR miss cycles
858system.cpu.dcache.demand_mshr_miss_latency::total 30306487 # number of demand (read+write) MSHR miss cycles
859system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30306487 # number of overall MSHR miss cycles
860system.cpu.dcache.overall_mshr_miss_latency::total 30306487 # number of overall MSHR miss cycles
823system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77721.682848 # average ReadReq miss latency
824system.cpu.dcache.ReadReq_avg_miss_latency::total 77721.682848 # average ReadReq miss latency
825system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 71490.878830 # average WriteReq miss latency
826system.cpu.dcache.WriteReq_avg_miss_latency::total 71490.878830 # average WriteReq miss latency
827system.cpu.dcache.demand_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency
828system.cpu.dcache.demand_avg_miss_latency::total 73365.580331 # average overall miss latency
829system.cpu.dcache.overall_avg_miss_latency::cpu.data 73365.580331 # average overall miss latency
830system.cpu.dcache.overall_avg_miss_latency::total 73365.580331 # average overall miss latency
831system.cpu.dcache.blocked_cycles::no_mshrs 5997 # number of cycles access was blocked
832system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
833system.cpu.dcache.blocked::no_mshrs 108 # number of cycles access was blocked
834system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
835system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.527778 # average number of cycles each access was blocked
836system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
837system.cpu.dcache.ReadReq_mshr_hits::cpu.data 110 # number of ReadReq MSHR hits
838system.cpu.dcache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits
839system.cpu.dcache.WriteReq_mshr_hits::cpu.data 574 # number of WriteReq MSHR hits
840system.cpu.dcache.WriteReq_mshr_hits::total 574 # number of WriteReq MSHR hits
841system.cpu.dcache.demand_mshr_hits::cpu.data 684 # number of demand (read+write) MSHR hits
842system.cpu.dcache.demand_mshr_hits::total 684 # number of demand (read+write) MSHR hits
843system.cpu.dcache.overall_mshr_hits::cpu.data 684 # number of overall MSHR hits
844system.cpu.dcache.overall_mshr_hits::total 684 # number of overall MSHR hits
845system.cpu.dcache.ReadReq_mshr_misses::cpu.data 199 # number of ReadReq MSHR misses
846system.cpu.dcache.ReadReq_mshr_misses::total 199 # number of ReadReq MSHR misses
847system.cpu.dcache.WriteReq_mshr_misses::cpu.data 144 # number of WriteReq MSHR misses
848system.cpu.dcache.WriteReq_mshr_misses::total 144 # number of WriteReq MSHR misses
849system.cpu.dcache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses
850system.cpu.dcache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses
851system.cpu.dcache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses
852system.cpu.dcache.overall_mshr_misses::total 343 # number of overall MSHR misses
853system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 17847000 # number of ReadReq MSHR miss cycles
854system.cpu.dcache.ReadReq_mshr_miss_latency::total 17847000 # number of ReadReq MSHR miss cycles
855system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12459487 # number of WriteReq MSHR miss cycles
856system.cpu.dcache.WriteReq_mshr_miss_latency::total 12459487 # number of WriteReq MSHR miss cycles
857system.cpu.dcache.demand_mshr_miss_latency::cpu.data 30306487 # number of demand (read+write) MSHR miss cycles
858system.cpu.dcache.demand_mshr_miss_latency::total 30306487 # number of demand (read+write) MSHR miss cycles
859system.cpu.dcache.overall_mshr_miss_latency::cpu.data 30306487 # number of overall MSHR miss cycles
860system.cpu.dcache.overall_mshr_miss_latency::total 30306487 # number of overall MSHR miss cycles
861system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056326 # mshr miss rate for ReadReq accesses
862system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056326 # mshr miss rate for ReadReq accesses
861system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.056310 # mshr miss rate for ReadReq accesses
862system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.056310 # mshr miss rate for ReadReq accesses
863system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
864system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
863system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses
864system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses
865system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for demand accesses
866system.cpu.dcache.demand_mshr_miss_rate::total 0.065172 # mshr miss rate for demand accesses
867system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065172 # mshr miss rate for overall accesses
868system.cpu.dcache.overall_mshr_miss_rate::total 0.065172 # mshr miss rate for overall accesses
865system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for demand accesses
866system.cpu.dcache.demand_mshr_miss_rate::total 0.065160 # mshr miss rate for demand accesses
867system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.065160 # mshr miss rate for overall accesses
868system.cpu.dcache.overall_mshr_miss_rate::total 0.065160 # mshr miss rate for overall accesses
869system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89683.417085 # average ReadReq mshr miss latency
870system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89683.417085 # average ReadReq mshr miss latency
871system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86524.215278 # average WriteReq mshr miss latency
872system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86524.215278 # average WriteReq mshr miss latency
873system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency
874system.cpu.dcache.demand_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency
875system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency
876system.cpu.dcache.overall_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency
877system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
878system.cpu.icache.tags.replacements::0 7 # number of replacements
879system.cpu.icache.tags.replacements::1 0 # number of replacements
880system.cpu.icache.tags.replacements::total 7 # number of replacements
869system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89683.417085 # average ReadReq mshr miss latency
870system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89683.417085 # average ReadReq mshr miss latency
871system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 86524.215278 # average WriteReq mshr miss latency
872system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 86524.215278 # average WriteReq mshr miss latency
873system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency
874system.cpu.dcache.demand_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency
875system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 88357.104956 # average overall mshr miss latency
876system.cpu.dcache.overall_avg_mshr_miss_latency::total 88357.104956 # average overall mshr miss latency
877system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
878system.cpu.icache.tags.replacements::0 7 # number of replacements
879system.cpu.icache.tags.replacements::1 0 # number of replacements
880system.cpu.icache.tags.replacements::total 7 # number of replacements
881system.cpu.icache.tags.tagsinuse 318.055053 # Cycle average of tags in use
881system.cpu.icache.tags.tagsinuse 318.054191 # Cycle average of tags in use
882system.cpu.icache.tags.total_refs 2937 # Total number of references to valid blocks.
883system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks.
884system.cpu.icache.tags.avg_refs 4.676752 # Average number of references to valid blocks.
885system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
882system.cpu.icache.tags.total_refs 2937 # Total number of references to valid blocks.
883system.cpu.icache.tags.sampled_refs 628 # Sample count of references to valid blocks.
884system.cpu.icache.tags.avg_refs 4.676752 # Average number of references to valid blocks.
885system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
886system.cpu.icache.tags.occ_blocks::cpu.inst 318.055053 # Average occupied blocks per requestor
886system.cpu.icache.tags.occ_blocks::cpu.inst 318.054191 # Average occupied blocks per requestor
887system.cpu.icache.tags.occ_percent::cpu.inst 0.155300 # Average percentage of cache occupancy
888system.cpu.icache.tags.occ_percent::total 0.155300 # Average percentage of cache occupancy
889system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id
890system.cpu.icache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id
891system.cpu.icache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id
892system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id
893system.cpu.icache.tags.tag_accesses 8292 # Number of tag accesses
894system.cpu.icache.tags.data_accesses 8292 # Number of data accesses
895system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
896system.cpu.icache.ReadReq_hits::cpu.inst 2937 # number of ReadReq hits
897system.cpu.icache.ReadReq_hits::total 2937 # number of ReadReq hits
898system.cpu.icache.demand_hits::cpu.inst 2937 # number of demand (read+write) hits
899system.cpu.icache.demand_hits::total 2937 # number of demand (read+write) hits
900system.cpu.icache.overall_hits::cpu.inst 2937 # number of overall hits
901system.cpu.icache.overall_hits::total 2937 # number of overall hits
902system.cpu.icache.ReadReq_misses::cpu.inst 895 # number of ReadReq misses
903system.cpu.icache.ReadReq_misses::total 895 # number of ReadReq misses
904system.cpu.icache.demand_misses::cpu.inst 895 # number of demand (read+write) misses
905system.cpu.icache.demand_misses::total 895 # number of demand (read+write) misses
906system.cpu.icache.overall_misses::cpu.inst 895 # number of overall misses
907system.cpu.icache.overall_misses::total 895 # number of overall misses
887system.cpu.icache.tags.occ_percent::cpu.inst 0.155300 # Average percentage of cache occupancy
888system.cpu.icache.tags.occ_percent::total 0.155300 # Average percentage of cache occupancy
889system.cpu.icache.tags.occ_task_id_blocks::1024 621 # Occupied blocks per task id
890system.cpu.icache.tags.age_task_id_blocks_1024::0 238 # Occupied blocks per task id
891system.cpu.icache.tags.age_task_id_blocks_1024::1 383 # Occupied blocks per task id
892system.cpu.icache.tags.occ_task_id_percent::1024 0.303223 # Percentage of cache occupancy per task id
893system.cpu.icache.tags.tag_accesses 8292 # Number of tag accesses
894system.cpu.icache.tags.data_accesses 8292 # Number of data accesses
895system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
896system.cpu.icache.ReadReq_hits::cpu.inst 2937 # number of ReadReq hits
897system.cpu.icache.ReadReq_hits::total 2937 # number of ReadReq hits
898system.cpu.icache.demand_hits::cpu.inst 2937 # number of demand (read+write) hits
899system.cpu.icache.demand_hits::total 2937 # number of demand (read+write) hits
900system.cpu.icache.overall_hits::cpu.inst 2937 # number of overall hits
901system.cpu.icache.overall_hits::total 2937 # number of overall hits
902system.cpu.icache.ReadReq_misses::cpu.inst 895 # number of ReadReq misses
903system.cpu.icache.ReadReq_misses::total 895 # number of ReadReq misses
904system.cpu.icache.demand_misses::cpu.inst 895 # number of demand (read+write) misses
905system.cpu.icache.demand_misses::total 895 # number of demand (read+write) misses
906system.cpu.icache.overall_misses::cpu.inst 895 # number of overall misses
907system.cpu.icache.overall_misses::total 895 # number of overall misses
908system.cpu.icache.ReadReq_miss_latency::cpu.inst 72806995 # number of ReadReq miss cycles
909system.cpu.icache.ReadReq_miss_latency::total 72806995 # number of ReadReq miss cycles
910system.cpu.icache.demand_miss_latency::cpu.inst 72806995 # number of demand (read+write) miss cycles
911system.cpu.icache.demand_miss_latency::total 72806995 # number of demand (read+write) miss cycles
912system.cpu.icache.overall_miss_latency::cpu.inst 72806995 # number of overall miss cycles
913system.cpu.icache.overall_miss_latency::total 72806995 # number of overall miss cycles
908system.cpu.icache.ReadReq_miss_latency::cpu.inst 72804995 # number of ReadReq miss cycles
909system.cpu.icache.ReadReq_miss_latency::total 72804995 # number of ReadReq miss cycles
910system.cpu.icache.demand_miss_latency::cpu.inst 72804995 # number of demand (read+write) miss cycles
911system.cpu.icache.demand_miss_latency::total 72804995 # number of demand (read+write) miss cycles
912system.cpu.icache.overall_miss_latency::cpu.inst 72804995 # number of overall miss cycles
913system.cpu.icache.overall_miss_latency::total 72804995 # number of overall miss cycles
914system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses)
915system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses)
916system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses
917system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses
918system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses
919system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses
920system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233559 # miss rate for ReadReq accesses
921system.cpu.icache.ReadReq_miss_rate::total 0.233559 # miss rate for ReadReq accesses
922system.cpu.icache.demand_miss_rate::cpu.inst 0.233559 # miss rate for demand accesses
923system.cpu.icache.demand_miss_rate::total 0.233559 # miss rate for demand accesses
924system.cpu.icache.overall_miss_rate::cpu.inst 0.233559 # miss rate for overall accesses
925system.cpu.icache.overall_miss_rate::total 0.233559 # miss rate for overall accesses
914system.cpu.icache.ReadReq_accesses::cpu.inst 3832 # number of ReadReq accesses(hits+misses)
915system.cpu.icache.ReadReq_accesses::total 3832 # number of ReadReq accesses(hits+misses)
916system.cpu.icache.demand_accesses::cpu.inst 3832 # number of demand (read+write) accesses
917system.cpu.icache.demand_accesses::total 3832 # number of demand (read+write) accesses
918system.cpu.icache.overall_accesses::cpu.inst 3832 # number of overall (read+write) accesses
919system.cpu.icache.overall_accesses::total 3832 # number of overall (read+write) accesses
920system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233559 # miss rate for ReadReq accesses
921system.cpu.icache.ReadReq_miss_rate::total 0.233559 # miss rate for ReadReq accesses
922system.cpu.icache.demand_miss_rate::cpu.inst 0.233559 # miss rate for demand accesses
923system.cpu.icache.demand_miss_rate::total 0.233559 # miss rate for demand accesses
924system.cpu.icache.overall_miss_rate::cpu.inst 0.233559 # miss rate for overall accesses
925system.cpu.icache.overall_miss_rate::total 0.233559 # miss rate for overall accesses
926system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81348.597765 # average ReadReq miss latency
927system.cpu.icache.ReadReq_avg_miss_latency::total 81348.597765 # average ReadReq miss latency
928system.cpu.icache.demand_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency
929system.cpu.icache.demand_avg_miss_latency::total 81348.597765 # average overall miss latency
930system.cpu.icache.overall_avg_miss_latency::cpu.inst 81348.597765 # average overall miss latency
931system.cpu.icache.overall_avg_miss_latency::total 81348.597765 # average overall miss latency
926system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81346.363128 # average ReadReq miss latency
927system.cpu.icache.ReadReq_avg_miss_latency::total 81346.363128 # average ReadReq miss latency
928system.cpu.icache.demand_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency
929system.cpu.icache.demand_avg_miss_latency::total 81346.363128 # average overall miss latency
930system.cpu.icache.overall_avg_miss_latency::cpu.inst 81346.363128 # average overall miss latency
931system.cpu.icache.overall_avg_miss_latency::total 81346.363128 # average overall miss latency
932system.cpu.icache.blocked_cycles::no_mshrs 3504 # number of cycles access was blocked
933system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
934system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked
935system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
936system.cpu.icache.avg_blocked_cycles::no_mshrs 60.413793 # average number of cycles each access was blocked
937system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
938system.cpu.icache.writebacks::writebacks 7 # number of writebacks
939system.cpu.icache.writebacks::total 7 # number of writebacks
940system.cpu.icache.ReadReq_mshr_hits::cpu.inst 267 # number of ReadReq MSHR hits
941system.cpu.icache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits
942system.cpu.icache.demand_mshr_hits::cpu.inst 267 # number of demand (read+write) MSHR hits
943system.cpu.icache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits
944system.cpu.icache.overall_mshr_hits::cpu.inst 267 # number of overall MSHR hits
945system.cpu.icache.overall_mshr_hits::total 267 # number of overall MSHR hits
946system.cpu.icache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses
947system.cpu.icache.ReadReq_mshr_misses::total 628 # number of ReadReq MSHR misses
948system.cpu.icache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses
949system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses
950system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses
951system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses
932system.cpu.icache.blocked_cycles::no_mshrs 3504 # number of cycles access was blocked
933system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
934system.cpu.icache.blocked::no_mshrs 58 # number of cycles access was blocked
935system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
936system.cpu.icache.avg_blocked_cycles::no_mshrs 60.413793 # average number of cycles each access was blocked
937system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
938system.cpu.icache.writebacks::writebacks 7 # number of writebacks
939system.cpu.icache.writebacks::total 7 # number of writebacks
940system.cpu.icache.ReadReq_mshr_hits::cpu.inst 267 # number of ReadReq MSHR hits
941system.cpu.icache.ReadReq_mshr_hits::total 267 # number of ReadReq MSHR hits
942system.cpu.icache.demand_mshr_hits::cpu.inst 267 # number of demand (read+write) MSHR hits
943system.cpu.icache.demand_mshr_hits::total 267 # number of demand (read+write) MSHR hits
944system.cpu.icache.overall_mshr_hits::cpu.inst 267 # number of overall MSHR hits
945system.cpu.icache.overall_mshr_hits::total 267 # number of overall MSHR hits
946system.cpu.icache.ReadReq_mshr_misses::cpu.inst 628 # number of ReadReq MSHR misses
947system.cpu.icache.ReadReq_mshr_misses::total 628 # number of ReadReq MSHR misses
948system.cpu.icache.demand_mshr_misses::cpu.inst 628 # number of demand (read+write) MSHR misses
949system.cpu.icache.demand_mshr_misses::total 628 # number of demand (read+write) MSHR misses
950system.cpu.icache.overall_mshr_misses::cpu.inst 628 # number of overall MSHR misses
951system.cpu.icache.overall_mshr_misses::total 628 # number of overall MSHR misses
952system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54757996 # number of ReadReq MSHR miss cycles
953system.cpu.icache.ReadReq_mshr_miss_latency::total 54757996 # number of ReadReq MSHR miss cycles
954system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54757996 # number of demand (read+write) MSHR miss cycles
955system.cpu.icache.demand_mshr_miss_latency::total 54757996 # number of demand (read+write) MSHR miss cycles
956system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54757996 # number of overall MSHR miss cycles
957system.cpu.icache.overall_mshr_miss_latency::total 54757996 # number of overall MSHR miss cycles
952system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 54756996 # number of ReadReq MSHR miss cycles
953system.cpu.icache.ReadReq_mshr_miss_latency::total 54756996 # number of ReadReq MSHR miss cycles
954system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54756996 # number of demand (read+write) MSHR miss cycles
955system.cpu.icache.demand_mshr_miss_latency::total 54756996 # number of demand (read+write) MSHR miss cycles
956system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54756996 # number of overall MSHR miss cycles
957system.cpu.icache.overall_mshr_miss_latency::total 54756996 # number of overall MSHR miss cycles
958system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for ReadReq accesses
959system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163883 # mshr miss rate for ReadReq accesses
960system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for demand accesses
961system.cpu.icache.demand_mshr_miss_rate::total 0.163883 # mshr miss rate for demand accesses
962system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for overall accesses
963system.cpu.icache.overall_mshr_miss_rate::total 0.163883 # mshr miss rate for overall accesses
958system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for ReadReq accesses
959system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163883 # mshr miss rate for ReadReq accesses
960system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for demand accesses
961system.cpu.icache.demand_mshr_miss_rate::total 0.163883 # mshr miss rate for demand accesses
962system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163883 # mshr miss rate for overall accesses
963system.cpu.icache.overall_mshr_miss_rate::total 0.163883 # mshr miss rate for overall accesses
964system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87194.261146 # average ReadReq mshr miss latency
965system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87194.261146 # average ReadReq mshr miss latency
966system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency
967system.cpu.icache.demand_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency
968system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87194.261146 # average overall mshr miss latency
969system.cpu.icache.overall_avg_mshr_miss_latency::total 87194.261146 # average overall mshr miss latency
964system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 87192.668790 # average ReadReq mshr miss latency
965system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 87192.668790 # average ReadReq mshr miss latency
966system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency
967system.cpu.icache.demand_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency
968system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 87192.668790 # average overall mshr miss latency
969system.cpu.icache.overall_avg_mshr_miss_latency::total 87192.668790 # average overall mshr miss latency
970system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
971system.cpu.l2cache.tags.replacements::0 0 # number of replacements
972system.cpu.l2cache.tags.replacements::1 0 # number of replacements
973system.cpu.l2cache.tags.replacements::total 0 # number of replacements
970system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
971system.cpu.l2cache.tags.replacements::0 0 # number of replacements
972system.cpu.l2cache.tags.replacements::1 0 # number of replacements
973system.cpu.l2cache.tags.replacements::total 0 # number of replacements
974system.cpu.l2cache.tags.tagsinuse 534.674828 # Cycle average of tags in use
974system.cpu.l2cache.tags.tagsinuse 534.673891 # Cycle average of tags in use
975system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
976system.cpu.l2cache.tags.sampled_refs 967 # Sample count of references to valid blocks.
977system.cpu.l2cache.tags.avg_refs 0.010341 # Average number of references to valid blocks.
978system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
975system.cpu.l2cache.tags.total_refs 10 # Total number of references to valid blocks.
976system.cpu.l2cache.tags.sampled_refs 967 # Sample count of references to valid blocks.
977system.cpu.l2cache.tags.avg_refs 0.010341 # Average number of references to valid blocks.
978system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
979system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.519168 # Average occupied blocks per requestor
980system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155660 # Average occupied blocks per requestor
979system.cpu.l2cache.tags.occ_blocks::cpu.inst 318.518306 # Average occupied blocks per requestor
980system.cpu.l2cache.tags.occ_blocks::cpu.data 216.155585 # Average occupied blocks per requestor
981system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009720 # Average percentage of cache occupancy
982system.cpu.l2cache.tags.occ_percent::cpu.data 0.006597 # Average percentage of cache occupancy
983system.cpu.l2cache.tags.occ_percent::total 0.016317 # Average percentage of cache occupancy
984system.cpu.l2cache.tags.occ_task_id_blocks::1024 967 # Occupied blocks per task id
985system.cpu.l2cache.tags.age_task_id_blocks_1024::0 306 # Occupied blocks per task id
986system.cpu.l2cache.tags.age_task_id_blocks_1024::1 661 # Occupied blocks per task id
987system.cpu.l2cache.tags.occ_task_id_percent::1024 0.029510 # Percentage of cache occupancy per task id
988system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses
989system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses
990system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
991system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits
992system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits
993system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
994system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
995system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
996system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
997system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
998system.cpu.l2cache.overall_hits::total 3 # number of overall hits
999system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses
1000system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses
1001system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 625 # number of ReadCleanReq misses
1002system.cpu.l2cache.ReadCleanReq_misses::total 625 # number of ReadCleanReq misses
1003system.cpu.l2cache.ReadSharedReq_misses::cpu.data 198 # number of ReadSharedReq misses
1004system.cpu.l2cache.ReadSharedReq_misses::total 198 # number of ReadSharedReq misses
1005system.cpu.l2cache.demand_misses::cpu.inst 625 # number of demand (read+write) misses
1006system.cpu.l2cache.demand_misses::cpu.data 343 # number of demand (read+write) misses
1007system.cpu.l2cache.demand_misses::total 968 # number of demand (read+write) misses
1008system.cpu.l2cache.overall_misses::cpu.inst 625 # number of overall misses
1009system.cpu.l2cache.overall_misses::cpu.data 343 # number of overall misses
1010system.cpu.l2cache.overall_misses::total 968 # number of overall misses
1011system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12308500 # number of ReadExReq miss cycles
1012system.cpu.l2cache.ReadExReq_miss_latency::total 12308500 # number of ReadExReq miss cycles
981system.cpu.l2cache.tags.occ_percent::cpu.inst 0.009720 # Average percentage of cache occupancy
982system.cpu.l2cache.tags.occ_percent::cpu.data 0.006597 # Average percentage of cache occupancy
983system.cpu.l2cache.tags.occ_percent::total 0.016317 # Average percentage of cache occupancy
984system.cpu.l2cache.tags.occ_task_id_blocks::1024 967 # Occupied blocks per task id
985system.cpu.l2cache.tags.age_task_id_blocks_1024::0 306 # Occupied blocks per task id
986system.cpu.l2cache.tags.age_task_id_blocks_1024::1 661 # Occupied blocks per task id
987system.cpu.l2cache.tags.occ_task_id_percent::1024 0.029510 # Percentage of cache occupancy per task id
988system.cpu.l2cache.tags.tag_accesses 8791 # Number of tag accesses
989system.cpu.l2cache.tags.data_accesses 8791 # Number of data accesses
990system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
991system.cpu.l2cache.WritebackClean_hits::writebacks 7 # number of WritebackClean hits
992system.cpu.l2cache.WritebackClean_hits::total 7 # number of WritebackClean hits
993system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
994system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
995system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
996system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
997system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
998system.cpu.l2cache.overall_hits::total 3 # number of overall hits
999system.cpu.l2cache.ReadExReq_misses::cpu.data 145 # number of ReadExReq misses
1000system.cpu.l2cache.ReadExReq_misses::total 145 # number of ReadExReq misses
1001system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 625 # number of ReadCleanReq misses
1002system.cpu.l2cache.ReadCleanReq_misses::total 625 # number of ReadCleanReq misses
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1004system.cpu.l2cache.ReadSharedReq_misses::total 198 # number of ReadSharedReq misses
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1016system.cpu.l2cache.ReadSharedReq_miss_latency::total 17466000 # number of ReadSharedReq miss cycles
1015system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 17466000 # number of ReadSharedReq miss cycles
1016system.cpu.l2cache.ReadSharedReq_miss_latency::total 17466000 # number of ReadSharedReq miss cycles
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1017system.cpu.l2cache.demand_miss_latency::cpu.inst 53777000 # number of demand (read+write) miss cycles
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1018system.cpu.l2cache.demand_miss_latency::cpu.data 29774500 # number of demand (read+write) miss cycles
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1021system.cpu.l2cache.overall_miss_latency::cpu.data 29774500 # number of overall miss cycles
1021system.cpu.l2cache.overall_miss_latency::cpu.data 29774500 # number of overall miss cycles
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1022system.cpu.l2cache.overall_miss_latency::total 83551500 # number of overall miss cycles
1023system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses)
1024system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses)
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1026system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses)
1027system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 628 # number of ReadCleanReq accesses(hits+misses)
1028system.cpu.l2cache.ReadCleanReq_accesses::total 628 # number of ReadCleanReq accesses(hits+misses)
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1030system.cpu.l2cache.ReadSharedReq_accesses::total 198 # number of ReadSharedReq accesses(hits+misses)
1031system.cpu.l2cache.demand_accesses::cpu.inst 628 # number of demand (read+write) accesses
1032system.cpu.l2cache.demand_accesses::cpu.data 343 # number of demand (read+write) accesses
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1035system.cpu.l2cache.overall_accesses::cpu.data 343 # number of overall (read+write) accesses
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1038system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
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1040system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995223 # miss rate for ReadCleanReq accesses
1041system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
1042system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
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1044system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
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1046system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995223 # miss rate for overall accesses
1047system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
1048system.cpu.l2cache.overall_miss_rate::total 0.996910 # miss rate for overall accesses
1049system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84886.206897 # average ReadExReq miss latency
1050system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84886.206897 # average ReadExReq miss latency
1023system.cpu.l2cache.WritebackClean_accesses::writebacks 7 # number of WritebackClean accesses(hits+misses)
1024system.cpu.l2cache.WritebackClean_accesses::total 7 # number of WritebackClean accesses(hits+misses)
1025system.cpu.l2cache.ReadExReq_accesses::cpu.data 145 # number of ReadExReq accesses(hits+misses)
1026system.cpu.l2cache.ReadExReq_accesses::total 145 # number of ReadExReq accesses(hits+misses)
1027system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 628 # number of ReadCleanReq accesses(hits+misses)
1028system.cpu.l2cache.ReadCleanReq_accesses::total 628 # number of ReadCleanReq accesses(hits+misses)
1029system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 198 # number of ReadSharedReq accesses(hits+misses)
1030system.cpu.l2cache.ReadSharedReq_accesses::total 198 # number of ReadSharedReq accesses(hits+misses)
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1032system.cpu.l2cache.demand_accesses::cpu.data 343 # number of demand (read+write) accesses
1033system.cpu.l2cache.demand_accesses::total 971 # number of demand (read+write) accesses
1034system.cpu.l2cache.overall_accesses::cpu.inst 628 # number of overall (read+write) accesses
1035system.cpu.l2cache.overall_accesses::cpu.data 343 # number of overall (read+write) accesses
1036system.cpu.l2cache.overall_accesses::total 971 # number of overall (read+write) accesses
1037system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
1038system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
1039system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.995223 # miss rate for ReadCleanReq accesses
1040system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.995223 # miss rate for ReadCleanReq accesses
1041system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
1042system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
1043system.cpu.l2cache.demand_miss_rate::cpu.inst 0.995223 # miss rate for demand accesses
1044system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
1045system.cpu.l2cache.demand_miss_rate::total 0.996910 # miss rate for demand accesses
1046system.cpu.l2cache.overall_miss_rate::cpu.inst 0.995223 # miss rate for overall accesses
1047system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
1048system.cpu.l2cache.overall_miss_rate::total 0.996910 # miss rate for overall accesses
1049system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84886.206897 # average ReadExReq miss latency
1050system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84886.206897 # average ReadExReq miss latency
1051system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86044.800000 # average ReadCleanReq miss latency
1052system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86044.800000 # average ReadCleanReq miss latency
1051system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86043.200000 # average ReadCleanReq miss latency
1052system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86043.200000 # average ReadCleanReq miss latency
1053system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88212.121212 # average ReadSharedReq miss latency
1054system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88212.121212 # average ReadSharedReq miss latency
1053system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88212.121212 # average ReadSharedReq miss latency
1054system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88212.121212 # average ReadSharedReq miss latency
1055system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency
1055system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency
1056system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency
1056system.cpu.l2cache.demand_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency
1057system.cpu.l2cache.demand_avg_miss_latency::total 86314.566116 # average overall miss latency
1058system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86044.800000 # average overall miss latency
1057system.cpu.l2cache.demand_avg_miss_latency::total 86313.533058 # average overall miss latency
1058system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86043.200000 # average overall miss latency
1059system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency
1059system.cpu.l2cache.overall_avg_miss_latency::cpu.data 86806.122449 # average overall miss latency
1060system.cpu.l2cache.overall_avg_miss_latency::total 86314.566116 # average overall miss latency
1060system.cpu.l2cache.overall_avg_miss_latency::total 86313.533058 # average overall miss latency
1061system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1062system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1063system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1064system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1065system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1066system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1067system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses
1068system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses
1069system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 625 # number of ReadCleanReq MSHR misses
1070system.cpu.l2cache.ReadCleanReq_mshr_misses::total 625 # number of ReadCleanReq MSHR misses
1071system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses
1072system.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses
1073system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses
1074system.cpu.l2cache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses
1075system.cpu.l2cache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses
1076system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses
1077system.cpu.l2cache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses
1078system.cpu.l2cache.overall_mshr_misses::total 968 # number of overall MSHR misses
1079system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10858500 # number of ReadExReq MSHR miss cycles
1080system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10858500 # number of ReadExReq MSHR miss cycles
1061system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
1062system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1063system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
1064system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1065system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
1066system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1067system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 145 # number of ReadExReq MSHR misses
1068system.cpu.l2cache.ReadExReq_mshr_misses::total 145 # number of ReadExReq MSHR misses
1069system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 625 # number of ReadCleanReq MSHR misses
1070system.cpu.l2cache.ReadCleanReq_mshr_misses::total 625 # number of ReadCleanReq MSHR misses
1071system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 198 # number of ReadSharedReq MSHR misses
1072system.cpu.l2cache.ReadSharedReq_mshr_misses::total 198 # number of ReadSharedReq MSHR misses
1073system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses
1074system.cpu.l2cache.demand_mshr_misses::cpu.data 343 # number of demand (read+write) MSHR misses
1075system.cpu.l2cache.demand_mshr_misses::total 968 # number of demand (read+write) MSHR misses
1076system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses
1077system.cpu.l2cache.overall_mshr_misses::cpu.data 343 # number of overall MSHR misses
1078system.cpu.l2cache.overall_mshr_misses::total 968 # number of overall MSHR misses
1079system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 10858500 # number of ReadExReq MSHR miss cycles
1080system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 10858500 # number of ReadExReq MSHR miss cycles
1081system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47528000 # number of ReadCleanReq MSHR miss cycles
1082system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47528000 # number of ReadCleanReq MSHR miss cycles
1081system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 47527000 # number of ReadCleanReq MSHR miss cycles
1082system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 47527000 # number of ReadCleanReq MSHR miss cycles
1083system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15496000 # number of ReadSharedReq MSHR miss cycles
1084system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15496000 # number of ReadSharedReq MSHR miss cycles
1083system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 15496000 # number of ReadSharedReq MSHR miss cycles
1084system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 15496000 # number of ReadSharedReq MSHR miss cycles
1085system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47528000 # number of demand (read+write) MSHR miss cycles
1085system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 47527000 # number of demand (read+write) MSHR miss cycles
1086system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26354500 # number of demand (read+write) MSHR miss cycles
1086system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 26354500 # number of demand (read+write) MSHR miss cycles
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1088system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47528000 # number of overall MSHR miss cycles
1087system.cpu.l2cache.demand_mshr_miss_latency::total 73881500 # number of demand (read+write) MSHR miss cycles
1088system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 47527000 # number of overall MSHR miss cycles
1089system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26354500 # number of overall MSHR miss cycles
1089system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 26354500 # number of overall MSHR miss cycles
1090system.cpu.l2cache.overall_mshr_miss_latency::total 73882500 # number of overall MSHR miss cycles
1090system.cpu.l2cache.overall_mshr_miss_latency::total 73881500 # number of overall MSHR miss cycles
1091system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
1092system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
1093system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for ReadCleanReq accesses
1094system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995223 # mshr miss rate for ReadCleanReq accesses
1095system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
1096system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
1097system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for demand accesses
1098system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
1099system.cpu.l2cache.demand_mshr_miss_rate::total 0.996910 # mshr miss rate for demand accesses
1100system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for overall accesses
1101system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
1102system.cpu.l2cache.overall_mshr_miss_rate::total 0.996910 # mshr miss rate for overall accesses
1103system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74886.206897 # average ReadExReq mshr miss latency
1104system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74886.206897 # average ReadExReq mshr miss latency
1091system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
1092system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
1093system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for ReadCleanReq accesses
1094system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.995223 # mshr miss rate for ReadCleanReq accesses
1095system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
1096system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
1097system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for demand accesses
1098system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
1099system.cpu.l2cache.demand_mshr_miss_rate::total 0.996910 # mshr miss rate for demand accesses
1100system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995223 # mshr miss rate for overall accesses
1101system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
1102system.cpu.l2cache.overall_mshr_miss_rate::total 0.996910 # mshr miss rate for overall accesses
1103system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74886.206897 # average ReadExReq mshr miss latency
1104system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74886.206897 # average ReadExReq mshr miss latency
1105system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76044.800000 # average ReadCleanReq mshr miss latency
1106system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76044.800000 # average ReadCleanReq mshr miss latency
1105system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 76043.200000 # average ReadCleanReq mshr miss latency
1106system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 76043.200000 # average ReadCleanReq mshr miss latency
1107system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78262.626263 # average ReadSharedReq mshr miss latency
1108system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78262.626263 # average ReadSharedReq mshr miss latency
1107system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78262.626263 # average ReadSharedReq mshr miss latency
1108system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78262.626263 # average ReadSharedReq mshr miss latency
1109system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency
1109system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency
1110system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency
1110system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency
1111system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency
1112system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76044.800000 # average overall mshr miss latency
1111system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency
1112system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76043.200000 # average overall mshr miss latency
1113system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency
1113system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 76835.276968 # average overall mshr miss latency
1114system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76324.896694 # average overall mshr miss latency
1114system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76323.863636 # average overall mshr miss latency
1115system.cpu.toL2Bus.snoop_filter.tot_requests 978 # Total number of requests made to the snoop filter.
1116system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1117system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1118system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1119system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1120system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1121system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
1122system.cpu.toL2Bus.trans_dist::ReadResp 825 # Transaction distribution
1123system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
1124system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution
1125system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution
1126system.cpu.toL2Bus.trans_dist::ReadCleanReq 628 # Transaction distribution
1127system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution
1128system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1263 # Packet count per connected master and slave (bytes)
1129system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 685 # Packet count per connected master and slave (bytes)
1130system.cpu.toL2Bus.pkt_count::total 1948 # Packet count per connected master and slave (bytes)
1131system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40640 # Cumulative packet size per connected master and slave (bytes)
1132system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21888 # Cumulative packet size per connected master and slave (bytes)
1133system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes)
1134system.cpu.toL2Bus.snoops 0 # Total snoops (count)
1135system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
1136system.cpu.toL2Bus.snoop_fanout::samples 971 # Request fanout histogram
1137system.cpu.toL2Bus.snoop_fanout::mean 0.002060 # Request fanout histogram
1138system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram
1139system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1140system.cpu.toL2Bus.snoop_fanout::0 969 99.79% 99.79% # Request fanout histogram
1141system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram
1142system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1143system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1144system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1145system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1146system.cpu.toL2Bus.snoop_fanout::total 971 # Request fanout histogram
1147system.cpu.toL2Bus.reqLayer0.occupancy 496000 # Layer occupancy (ticks)
1148system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
1149system.cpu.toL2Bus.respLayer0.occupancy 942000 # Layer occupancy (ticks)
1150system.cpu.toL2Bus.respLayer0.utilization 3.5 # Layer utilization (%)
1151system.cpu.toL2Bus.respLayer1.occupancy 513000 # Layer occupancy (ticks)
1152system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%)
1153system.membus.snoop_filter.tot_requests 968 # Total number of requests made to the snoop filter.
1154system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1155system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1156system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1157system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1158system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1159system.membus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
1160system.membus.trans_dist::ReadResp 822 # Transaction distribution
1161system.membus.trans_dist::ReadExReq 145 # Transaction distribution
1162system.membus.trans_dist::ReadExResp 145 # Transaction distribution
1163system.membus.trans_dist::ReadSharedReq 823 # Transaction distribution
1164system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1935 # Packet count per connected master and slave (bytes)
1165system.membus.pkt_count::total 1935 # Packet count per connected master and slave (bytes)
1166system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61888 # Cumulative packet size per connected master and slave (bytes)
1167system.membus.pkt_size::total 61888 # Cumulative packet size per connected master and slave (bytes)
1168system.membus.snoops 0 # Total snoops (count)
1169system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
1170system.membus.snoop_fanout::samples 968 # Request fanout histogram
1171system.membus.snoop_fanout::mean 0 # Request fanout histogram
1172system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1173system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1174system.membus.snoop_fanout::0 968 100.00% 100.00% # Request fanout histogram
1175system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1176system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1177system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1178system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1179system.membus.snoop_fanout::total 968 # Request fanout histogram
1180system.membus.reqLayer0.occupancy 1179500 # Layer occupancy (ticks)
1181system.membus.reqLayer0.utilization 4.4 # Layer utilization (%)
1182system.membus.respLayer1.occupancy 5127250 # Layer occupancy (ticks)
1183system.membus.respLayer1.utilization 19.2 # Layer utilization (%)
1184
1185---------- End Simulation Statistics ----------
1115system.cpu.toL2Bus.snoop_filter.tot_requests 978 # Total number of requests made to the snoop filter.
1116system.cpu.toL2Bus.snoop_filter.hit_single_requests 9 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1117system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1118system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1119system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1120system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1121system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
1122system.cpu.toL2Bus.trans_dist::ReadResp 825 # Transaction distribution
1123system.cpu.toL2Bus.trans_dist::WritebackClean 7 # Transaction distribution
1124system.cpu.toL2Bus.trans_dist::ReadExReq 145 # Transaction distribution
1125system.cpu.toL2Bus.trans_dist::ReadExResp 145 # Transaction distribution
1126system.cpu.toL2Bus.trans_dist::ReadCleanReq 628 # Transaction distribution
1127system.cpu.toL2Bus.trans_dist::ReadSharedReq 198 # Transaction distribution
1128system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1263 # Packet count per connected master and slave (bytes)
1129system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 685 # Packet count per connected master and slave (bytes)
1130system.cpu.toL2Bus.pkt_count::total 1948 # Packet count per connected master and slave (bytes)
1131system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40640 # Cumulative packet size per connected master and slave (bytes)
1132system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21888 # Cumulative packet size per connected master and slave (bytes)
1133system.cpu.toL2Bus.pkt_size::total 62528 # Cumulative packet size per connected master and slave (bytes)
1134system.cpu.toL2Bus.snoops 0 # Total snoops (count)
1135system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
1136system.cpu.toL2Bus.snoop_fanout::samples 971 # Request fanout histogram
1137system.cpu.toL2Bus.snoop_fanout::mean 0.002060 # Request fanout histogram
1138system.cpu.toL2Bus.snoop_fanout::stdev 0.045361 # Request fanout histogram
1139system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1140system.cpu.toL2Bus.snoop_fanout::0 969 99.79% 99.79% # Request fanout histogram
1141system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00% # Request fanout histogram
1142system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
1143system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1144system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1145system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
1146system.cpu.toL2Bus.snoop_fanout::total 971 # Request fanout histogram
1147system.cpu.toL2Bus.reqLayer0.occupancy 496000 # Layer occupancy (ticks)
1148system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%)
1149system.cpu.toL2Bus.respLayer0.occupancy 942000 # Layer occupancy (ticks)
1150system.cpu.toL2Bus.respLayer0.utilization 3.5 # Layer utilization (%)
1151system.cpu.toL2Bus.respLayer1.occupancy 513000 # Layer occupancy (ticks)
1152system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%)
1153system.membus.snoop_filter.tot_requests 968 # Total number of requests made to the snoop filter.
1154system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1155system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1156system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
1157system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1158system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1159system.membus.pwrStateResidencyTicks::UNDEFINED 26661500 # Cumulative time (in ticks) in various power states
1160system.membus.trans_dist::ReadResp 822 # Transaction distribution
1161system.membus.trans_dist::ReadExReq 145 # Transaction distribution
1162system.membus.trans_dist::ReadExResp 145 # Transaction distribution
1163system.membus.trans_dist::ReadSharedReq 823 # Transaction distribution
1164system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1935 # Packet count per connected master and slave (bytes)
1165system.membus.pkt_count::total 1935 # Packet count per connected master and slave (bytes)
1166system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 61888 # Cumulative packet size per connected master and slave (bytes)
1167system.membus.pkt_size::total 61888 # Cumulative packet size per connected master and slave (bytes)
1168system.membus.snoops 0 # Total snoops (count)
1169system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
1170system.membus.snoop_fanout::samples 968 # Request fanout histogram
1171system.membus.snoop_fanout::mean 0 # Request fanout histogram
1172system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1173system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1174system.membus.snoop_fanout::0 968 100.00% 100.00% # Request fanout histogram
1175system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1176system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1177system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1178system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1179system.membus.snoop_fanout::total 968 # Request fanout histogram
1180system.membus.reqLayer0.occupancy 1179500 # Layer occupancy (ticks)
1181system.membus.reqLayer0.utilization 4.4 # Layer utilization (%)
1182system.membus.respLayer1.occupancy 5127250 # Layer occupancy (ticks)
1183system.membus.respLayer1.utilization 19.2 # Layer utilization (%)
1184
1185---------- End Simulation Statistics ----------