| config.ini (11440:76b5639162af) | config.ini (11570:4aac82f10951) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17default_p_state=UNDEFINED |
|
| 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=true 29num_work_ids=16 | 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=true 30num_work_ids=16 |
| 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null |
|
| 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 --- 29 unchanged lines hidden (view full) --- 67commitToFetchDelay=1 68commitToIEWDelay=1 69commitToRenameDelay=1 70commitWidth=8 71cpu_id=0 72decodeToFetchDelay=1 73decodeToRenameDelay=1 74decodeWidth=8 | 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 --- 29 unchanged lines hidden (view full) --- 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 |
| 80default_p_state=UNDEFINED |
|
| 75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu.dtb 80eventq_index=0 81fetchBufferSize=64 82fetchQueueSize=32 --- 20 unchanged lines hidden (view full) --- 103needsTSO=false 104numIQEntries=64 105numPhysCCRegs=0 106numPhysFloatRegs=256 107numPhysIntRegs=256 108numROBEntries=192 109numRobs=1 110numThreads=2 | 81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 --- 20 unchanged lines hidden (view full) --- 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=2 |
| 117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null |
|
| 111profile=0 112progress_interval=0 113renameToDecodeDelay=1 114renameToFetchDelay=1 115renameToIEWDelay=2 116renameToROBDelay=1 117renameWidth=8 118simpoint_start_insts= --- 43 unchanged lines hidden (view full) --- 162 163[system.cpu.dcache] 164type=Cache 165children=tags 166addr_ranges=0:18446744073709551615 167assoc=2 168clk_domain=system.cpu_clk_domain 169clusivity=mostly_incl | 121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= --- 43 unchanged lines hidden (view full) --- 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl |
| 180default_p_state=UNDEFINED |
|
| 170demand_mshr_reserve=1 171eventq_index=0 172hit_latency=2 173is_read_only=false 174max_miss_count=0 175mshrs=4 | 181demand_mshr_reserve=1 182eventq_index=0 183hit_latency=2 184is_read_only=false 185max_miss_count=0 186mshrs=4 |
| 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null |
|
| 176prefetch_on_access=false 177prefetcher=Null 178response_latency=2 179sequential_access=false 180size=262144 181system=system 182tags=system.cpu.dcache.tags 183tgts_per_mshr=20 184write_buffers=8 185writeback_clean=false 186cpu_side=system.cpu.dcache_port 187mem_side=system.cpu.toL2Bus.slave[1] 188 189[system.cpu.dcache.tags] 190type=LRU 191assoc=2 192block_size=64 193clk_domain=system.cpu_clk_domain | 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=262144 196system=system 197tags=system.cpu.dcache.tags 198tgts_per_mshr=20 199write_buffers=8 200writeback_clean=false 201cpu_side=system.cpu.dcache_port 202mem_side=system.cpu.toL2Bus.slave[1] 203 204[system.cpu.dcache.tags] 205type=LRU 206assoc=2 207block_size=64 208clk_domain=system.cpu_clk_domain |
| 209default_p_state=UNDEFINED |
|
| 194eventq_index=0 195hit_latency=2 | 210eventq_index=0 211hit_latency=2 |
| 212p_state_clk_gate_bins=20 213p_state_clk_gate_max=1000000000000 214p_state_clk_gate_min=1000 215power_model=Null |
|
| 196sequential_access=false 197size=262144 198 199[system.cpu.dtb] 200type=AlphaTLB 201eventq_index=0 202size=64 203 --- 306 unchanged lines hidden (view full) --- 510 511[system.cpu.icache] 512type=Cache 513children=tags 514addr_ranges=0:18446744073709551615 515assoc=2 516clk_domain=system.cpu_clk_domain 517clusivity=mostly_incl | 216sequential_access=false 217size=262144 218 219[system.cpu.dtb] 220type=AlphaTLB 221eventq_index=0 222size=64 223 --- 306 unchanged lines hidden (view full) --- 530 531[system.cpu.icache] 532type=Cache 533children=tags 534addr_ranges=0:18446744073709551615 535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl |
| 538default_p_state=UNDEFINED |
|
| 518demand_mshr_reserve=1 519eventq_index=0 520hit_latency=2 521is_read_only=true 522max_miss_count=0 523mshrs=4 | 539demand_mshr_reserve=1 540eventq_index=0 541hit_latency=2 542is_read_only=true 543max_miss_count=0 544mshrs=4 |
| 545p_state_clk_gate_bins=20 546p_state_clk_gate_max=1000000000000 547p_state_clk_gate_min=1000 548power_model=Null |
|
| 524prefetch_on_access=false 525prefetcher=Null 526response_latency=2 527sequential_access=false 528size=131072 529system=system 530tags=system.cpu.icache.tags 531tgts_per_mshr=20 532write_buffers=8 533writeback_clean=true 534cpu_side=system.cpu.icache_port 535mem_side=system.cpu.toL2Bus.slave[0] 536 537[system.cpu.icache.tags] 538type=LRU 539assoc=2 540block_size=64 541clk_domain=system.cpu_clk_domain | 549prefetch_on_access=false 550prefetcher=Null 551response_latency=2 552sequential_access=false 553size=131072 554system=system 555tags=system.cpu.icache.tags 556tgts_per_mshr=20 557write_buffers=8 558writeback_clean=true 559cpu_side=system.cpu.icache_port 560mem_side=system.cpu.toL2Bus.slave[0] 561 562[system.cpu.icache.tags] 563type=LRU 564assoc=2 565block_size=64 566clk_domain=system.cpu_clk_domain |
| 567default_p_state=UNDEFINED |
|
| 542eventq_index=0 543hit_latency=2 | 568eventq_index=0 569hit_latency=2 |
| 570p_state_clk_gate_bins=20 571p_state_clk_gate_max=1000000000000 572p_state_clk_gate_min=1000 573power_model=Null |
|
| 544sequential_access=false 545size=131072 546 547[system.cpu.interrupts0] 548type=AlphaInterrupts 549eventq_index=0 550 551[system.cpu.interrupts1] --- 17 unchanged lines hidden (view full) --- 569 570[system.cpu.l2cache] 571type=Cache 572children=tags 573addr_ranges=0:18446744073709551615 574assoc=8 575clk_domain=system.cpu_clk_domain 576clusivity=mostly_incl | 574sequential_access=false 575size=131072 576 577[system.cpu.interrupts0] 578type=AlphaInterrupts 579eventq_index=0 580 581[system.cpu.interrupts1] --- 17 unchanged lines hidden (view full) --- 599 600[system.cpu.l2cache] 601type=Cache 602children=tags 603addr_ranges=0:18446744073709551615 604assoc=8 605clk_domain=system.cpu_clk_domain 606clusivity=mostly_incl |
| 607default_p_state=UNDEFINED |
|
| 577demand_mshr_reserve=1 578eventq_index=0 579hit_latency=20 580is_read_only=false 581max_miss_count=0 582mshrs=20 | 608demand_mshr_reserve=1 609eventq_index=0 610hit_latency=20 611is_read_only=false 612max_miss_count=0 613mshrs=20 |
| 614p_state_clk_gate_bins=20 615p_state_clk_gate_max=1000000000000 616p_state_clk_gate_min=1000 617power_model=Null |
|
| 583prefetch_on_access=false 584prefetcher=Null 585response_latency=20 586sequential_access=false 587size=2097152 588system=system 589tags=system.cpu.l2cache.tags 590tgts_per_mshr=12 591write_buffers=8 592writeback_clean=false 593cpu_side=system.cpu.toL2Bus.master[0] 594mem_side=system.membus.slave[1] 595 596[system.cpu.l2cache.tags] 597type=LRU 598assoc=8 599block_size=64 600clk_domain=system.cpu_clk_domain | 618prefetch_on_access=false 619prefetcher=Null 620response_latency=20 621sequential_access=false 622size=2097152 623system=system 624tags=system.cpu.l2cache.tags 625tgts_per_mshr=12 626write_buffers=8 627writeback_clean=false 628cpu_side=system.cpu.toL2Bus.master[0] 629mem_side=system.membus.slave[1] 630 631[system.cpu.l2cache.tags] 632type=LRU 633assoc=8 634block_size=64 635clk_domain=system.cpu_clk_domain |
| 636default_p_state=UNDEFINED |
|
| 601eventq_index=0 602hit_latency=20 | 637eventq_index=0 638hit_latency=20 |
| 639p_state_clk_gate_bins=20 640p_state_clk_gate_max=1000000000000 641p_state_clk_gate_min=1000 642power_model=Null |
|
| 603sequential_access=false 604size=2097152 605 606[system.cpu.toL2Bus] 607type=CoherentXBar 608children=snoop_filter 609clk_domain=system.cpu_clk_domain | 643sequential_access=false 644size=2097152 645 646[system.cpu.toL2Bus] 647type=CoherentXBar 648children=snoop_filter 649clk_domain=system.cpu_clk_domain |
| 650default_p_state=UNDEFINED |
|
| 610eventq_index=0 611forward_latency=0 612frontend_latency=1 | 651eventq_index=0 652forward_latency=0 653frontend_latency=1 |
| 654p_state_clk_gate_bins=20 655p_state_clk_gate_max=1000000000000 656p_state_clk_gate_min=1000 |
|
| 613point_of_coherency=false | 657point_of_coherency=false |
| 658power_model=Null |
|
| 614response_latency=1 615snoop_filter=system.cpu.toL2Bus.snoop_filter 616snoop_response_latency=1 617system=system 618use_default_range=false 619width=32 620master=system.cpu.l2cache.cpu_side 621slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 14 unchanged lines hidden (view full) --- 636cmd=hello 637cwd= 638drivers= 639egid=100 640env= 641errout=cerr 642euid=100 643eventq_index=0 | 659response_latency=1 660snoop_filter=system.cpu.toL2Bus.snoop_filter 661snoop_response_latency=1 662system=system 663use_default_range=false 664width=32 665master=system.cpu.l2cache.cpu_side 666slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 14 unchanged lines hidden (view full) --- 681cmd=hello 682cwd= 683drivers= 684egid=100 685env= 686errout=cerr 687euid=100 688eventq_index=0 |
| 644executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello | 689executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello |
| 645gid=100 646input=cin 647kvmInSE=false 648max_stack_size=67108864 649output=cout 650pid=100 651ppid=99 652simpoint=0 --- 6 unchanged lines hidden (view full) --- 659cmd=hello 660cwd= 661drivers= 662egid=100 663env= 664errout=cerr 665euid=100 666eventq_index=0 | 690gid=100 691input=cin 692kvmInSE=false 693max_stack_size=67108864 694output=cout 695pid=100 696ppid=99 697simpoint=0 --- 6 unchanged lines hidden (view full) --- 704cmd=hello 705cwd= 706drivers= 707egid=100 708env= 709errout=cerr 710euid=100 711eventq_index=0 |
| 667executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello | 712executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello |
| 668gid=100 669input=cin 670kvmInSE=false 671max_stack_size=67108864 672output=cout 673pid=100 674ppid=99 675simpoint=0 --- 15 unchanged lines hidden (view full) --- 691enable=false 692eventq_index=0 693sys_clk_domain=system.clk_domain 694transition_latency=100000000 695 696[system.membus] 697type=CoherentXBar 698clk_domain=system.clk_domain | 713gid=100 714input=cin 715kvmInSE=false 716max_stack_size=67108864 717output=cout 718pid=100 719ppid=99 720simpoint=0 --- 15 unchanged lines hidden (view full) --- 736enable=false 737eventq_index=0 738sys_clk_domain=system.clk_domain 739transition_latency=100000000 740 741[system.membus] 742type=CoherentXBar 743clk_domain=system.clk_domain |
| 744default_p_state=UNDEFINED |
|
| 699eventq_index=0 700forward_latency=4 701frontend_latency=3 | 745eventq_index=0 746forward_latency=4 747frontend_latency=3 |
| 748p_state_clk_gate_bins=20 749p_state_clk_gate_max=1000000000000 750p_state_clk_gate_min=1000 |
|
| 702point_of_coherency=true | 751point_of_coherency=true |
| 752power_model=Null |
|
| 703response_latency=2 704snoop_filter=Null 705snoop_response_latency=4 706system=system 707use_default_range=false 708width=16 709master=system.physmem.port 710slave=system.system_port system.cpu.l2cache.mem_side --- 27 unchanged lines hidden (view full) --- 738activation_limit=4 739addr_mapping=RoRaBaCoCh 740bank_groups_per_rank=0 741banks_per_rank=8 742burst_length=8 743channels=1 744clk_domain=system.clk_domain 745conf_table_reported=true | 753response_latency=2 754snoop_filter=Null 755snoop_response_latency=4 756system=system 757use_default_range=false 758width=16 759master=system.physmem.port 760slave=system.system_port system.cpu.l2cache.mem_side --- 27 unchanged lines hidden (view full) --- 788activation_limit=4 789addr_mapping=RoRaBaCoCh 790bank_groups_per_rank=0 791banks_per_rank=8 792burst_length=8 793channels=1 794clk_domain=system.clk_domain 795conf_table_reported=true |
| 796default_p_state=UNDEFINED |
|
| 746device_bus_width=8 747device_rowbuffer_size=1024 748device_size=536870912 749devices_per_rank=8 750dll=true 751eventq_index=0 752in_addr_map=true 753max_accesses_per_row=16 754mem_sched_policy=frfcfs 755min_writes_per_switch=16 756null=false | 797device_bus_width=8 798device_rowbuffer_size=1024 799device_size=536870912 800devices_per_rank=8 801dll=true 802eventq_index=0 803in_addr_map=true 804max_accesses_per_row=16 805mem_sched_policy=frfcfs 806min_writes_per_switch=16 807null=false |
| 808p_state_clk_gate_bins=20 809p_state_clk_gate_max=1000000000000 810p_state_clk_gate_min=1000 |
|
| 757page_policy=open_adaptive | 811page_policy=open_adaptive |
| 812power_model=Null |
|
| 758range=0:134217727 759ranks_per_channel=2 760read_buffer_size=32 761static_backend_latency=10000 762static_frontend_latency=10000 763tBURST=5000 764tCCD_L=0 765tCK=1250 --- 28 unchanged lines hidden --- | 813range=0:134217727 814ranks_per_channel=2 815read_buffer_size=32 816static_backend_latency=10000 817static_frontend_latency=10000 818tBURST=5000 819tCCD_L=0 820tCK=1250 --- 28 unchanged lines hidden --- |