1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
17default_p_state=UNDEFINED |
18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=true 30num_work_ids=16 |
31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null |
35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 --- 29 unchanged lines hidden (view full) --- 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8 |
80default_p_state=UNDEFINED |
81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 --- 20 unchanged lines hidden (view full) --- 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=2 |
117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null |
121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= --- 43 unchanged lines hidden (view full) --- 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl |
180default_p_state=UNDEFINED |
181demand_mshr_reserve=1 182eventq_index=0 183hit_latency=2 184is_read_only=false 185max_miss_count=0 186mshrs=4 |
187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null |
191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=262144 196system=system 197tags=system.cpu.dcache.tags 198tgts_per_mshr=20 199write_buffers=8 200writeback_clean=false 201cpu_side=system.cpu.dcache_port 202mem_side=system.cpu.toL2Bus.slave[1] 203 204[system.cpu.dcache.tags] 205type=LRU 206assoc=2 207block_size=64 208clk_domain=system.cpu_clk_domain |
209default_p_state=UNDEFINED |
210eventq_index=0 211hit_latency=2 |
212p_state_clk_gate_bins=20 213p_state_clk_gate_max=1000000000000 214p_state_clk_gate_min=1000 215power_model=Null |
216sequential_access=false 217size=262144 218 219[system.cpu.dtb] 220type=AlphaTLB 221eventq_index=0 222size=64 223 --- 306 unchanged lines hidden (view full) --- 530 531[system.cpu.icache] 532type=Cache 533children=tags 534addr_ranges=0:18446744073709551615 535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl |
538default_p_state=UNDEFINED |
539demand_mshr_reserve=1 540eventq_index=0 541hit_latency=2 542is_read_only=true 543max_miss_count=0 544mshrs=4 |
545p_state_clk_gate_bins=20 546p_state_clk_gate_max=1000000000000 547p_state_clk_gate_min=1000 548power_model=Null |
549prefetch_on_access=false 550prefetcher=Null 551response_latency=2 552sequential_access=false 553size=131072 554system=system 555tags=system.cpu.icache.tags 556tgts_per_mshr=20 557write_buffers=8 558writeback_clean=true 559cpu_side=system.cpu.icache_port 560mem_side=system.cpu.toL2Bus.slave[0] 561 562[system.cpu.icache.tags] 563type=LRU 564assoc=2 565block_size=64 566clk_domain=system.cpu_clk_domain |
567default_p_state=UNDEFINED |
568eventq_index=0 569hit_latency=2 |
570p_state_clk_gate_bins=20 571p_state_clk_gate_max=1000000000000 572p_state_clk_gate_min=1000 573power_model=Null |
574sequential_access=false 575size=131072 576 577[system.cpu.interrupts0] 578type=AlphaInterrupts 579eventq_index=0 580 581[system.cpu.interrupts1] --- 17 unchanged lines hidden (view full) --- 599 600[system.cpu.l2cache] 601type=Cache 602children=tags 603addr_ranges=0:18446744073709551615 604assoc=8 605clk_domain=system.cpu_clk_domain 606clusivity=mostly_incl |
607default_p_state=UNDEFINED |
608demand_mshr_reserve=1 609eventq_index=0 610hit_latency=20 611is_read_only=false 612max_miss_count=0 613mshrs=20 |
614p_state_clk_gate_bins=20 615p_state_clk_gate_max=1000000000000 616p_state_clk_gate_min=1000 617power_model=Null |
618prefetch_on_access=false 619prefetcher=Null 620response_latency=20 621sequential_access=false 622size=2097152 623system=system 624tags=system.cpu.l2cache.tags 625tgts_per_mshr=12 626write_buffers=8 627writeback_clean=false 628cpu_side=system.cpu.toL2Bus.master[0] 629mem_side=system.membus.slave[1] 630 631[system.cpu.l2cache.tags] 632type=LRU 633assoc=8 634block_size=64 635clk_domain=system.cpu_clk_domain |
636default_p_state=UNDEFINED |
637eventq_index=0 638hit_latency=20 |
639p_state_clk_gate_bins=20 640p_state_clk_gate_max=1000000000000 641p_state_clk_gate_min=1000 642power_model=Null |
643sequential_access=false 644size=2097152 645 646[system.cpu.toL2Bus] 647type=CoherentXBar 648children=snoop_filter 649clk_domain=system.cpu_clk_domain |
650default_p_state=UNDEFINED |
651eventq_index=0 652forward_latency=0 653frontend_latency=1 |
654p_state_clk_gate_bins=20 655p_state_clk_gate_max=1000000000000 656p_state_clk_gate_min=1000 |
657point_of_coherency=false |
658power_model=Null |
659response_latency=1 660snoop_filter=system.cpu.toL2Bus.snoop_filter 661snoop_response_latency=1 662system=system 663use_default_range=false 664width=32 665master=system.cpu.l2cache.cpu_side 666slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 14 unchanged lines hidden (view full) --- 681cmd=hello 682cwd= 683drivers= 684egid=100 685env= 686errout=cerr 687euid=100 688eventq_index=0 |
689executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello |
690gid=100 691input=cin 692kvmInSE=false 693max_stack_size=67108864 694output=cout 695pid=100 696ppid=99 697simpoint=0 --- 6 unchanged lines hidden (view full) --- 704cmd=hello 705cwd= 706drivers= 707egid=100 708env= 709errout=cerr 710euid=100 711eventq_index=0 |
712executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello |
713gid=100 714input=cin 715kvmInSE=false 716max_stack_size=67108864 717output=cout 718pid=100 719ppid=99 720simpoint=0 --- 15 unchanged lines hidden (view full) --- 736enable=false 737eventq_index=0 738sys_clk_domain=system.clk_domain 739transition_latency=100000000 740 741[system.membus] 742type=CoherentXBar 743clk_domain=system.clk_domain |
744default_p_state=UNDEFINED |
745eventq_index=0 746forward_latency=4 747frontend_latency=3 |
748p_state_clk_gate_bins=20 749p_state_clk_gate_max=1000000000000 750p_state_clk_gate_min=1000 |
751point_of_coherency=true |
752power_model=Null |
753response_latency=2 754snoop_filter=Null 755snoop_response_latency=4 756system=system 757use_default_range=false 758width=16 759master=system.physmem.port 760slave=system.system_port system.cpu.l2cache.mem_side --- 27 unchanged lines hidden (view full) --- 788activation_limit=4 789addr_mapping=RoRaBaCoCh 790bank_groups_per_rank=0 791banks_per_rank=8 792burst_length=8 793channels=1 794clk_domain=system.clk_domain 795conf_table_reported=true |
796default_p_state=UNDEFINED |
797device_bus_width=8 798device_rowbuffer_size=1024 799device_size=536870912 800devices_per_rank=8 801dll=true 802eventq_index=0 803in_addr_map=true 804max_accesses_per_row=16 805mem_sched_policy=frfcfs 806min_writes_per_switch=16 807null=false |
808p_state_clk_gate_bins=20 809p_state_clk_gate_max=1000000000000 810p_state_clk_gate_min=1000 |
811page_policy=open_adaptive |
812power_model=Null |
813range=0:134217727 814ranks_per_channel=2 815read_buffer_size=32 816static_backend_latency=10000 817static_frontend_latency=10000 818tBURST=5000 819tCCD_L=0 820tCK=1250 --- 28 unchanged lines hidden --- |