Cross Reference: /gem5/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini

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config.ini (11440:76b5639162af)	config.ini (11570:4aac82f10951)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain
	17default_p_state=UNDEFINED
17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=true 29num_work_ids=16	18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=true 30num_work_ids=16
	31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null
30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 38work_end_ckpt_count=0 39work_end_exit_count=0 40work_item_id=-1 41system_port=system.membus.slave[0] 42 43[system.clk_domain] 44type=SrcClockDomain 45clock=1000 46domain_id=-1 47eventq_index=0 48init_perf_level=0 49voltage_domain=system.voltage_domain 50 51[system.cpu] 52type=DerivO3CPU 53children=branchPred dcache dtb fuPool icache interrupts0 interrupts1 isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1 54LFSTSize=1024 55LQEntries=32 56LSQCheckLoads=true 57LSQDepCheckShift=4 58SQEntries=32 59SSITSize=1024 60activity=0 61backComSize=5 62branchPred=system.cpu.branchPred 63cachePorts=200 64checker=Null 65clk_domain=system.cpu_clk_domain 66commitToDecodeDelay=1 67commitToFetchDelay=1 68commitToIEWDelay=1 69commitToRenameDelay=1 70commitWidth=8 71cpu_id=0 72decodeToFetchDelay=1 73decodeToRenameDelay=1 74decodeWidth=8	35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 43work_end_ckpt_count=0 44work_end_exit_count=0 45work_item_id=-1 46system_port=system.membus.slave[0] 47 48[system.clk_domain] 49type=SrcClockDomain 50clock=1000 51domain_id=-1 52eventq_index=0 53init_perf_level=0 54voltage_domain=system.voltage_domain 55 56[system.cpu] 57type=DerivO3CPU 58children=branchPred dcache dtb fuPool icache interrupts0 interrupts1 isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1 59LFSTSize=1024 60LQEntries=32 61LSQCheckLoads=true 62LSQDepCheckShift=4 63SQEntries=32 64SSITSize=1024 65activity=0 66backComSize=5 67branchPred=system.cpu.branchPred 68cachePorts=200 69checker=Null 70clk_domain=system.cpu_clk_domain 71commitToDecodeDelay=1 72commitToFetchDelay=1 73commitToIEWDelay=1 74commitToRenameDelay=1 75commitWidth=8 76cpu_id=0 77decodeToFetchDelay=1 78decodeToRenameDelay=1 79decodeWidth=8
	80default_p_state=UNDEFINED
75dispatchWidth=8 76do_checkpoint_insts=true 77do_quiesce=true 78do_statistics_insts=true 79dtb=system.cpu.dtb 80eventq_index=0 81fetchBufferSize=64 82fetchQueueSize=32 83fetchToDecodeDelay=1 84fetchTrapLatency=1 85fetchWidth=8 86forwardComSize=5 87fuPool=system.cpu.fuPool 88function_trace=false 89function_trace_start=0 90iewToCommitDelay=1 91iewToDecodeDelay=1 92iewToFetchDelay=1 93iewToRenameDelay=1 94interrupts=system.cpu.interrupts0 system.cpu.interrupts1 95isa=system.cpu.isa0 system.cpu.isa1 96issueToExecuteDelay=1 97issueWidth=8 98itb=system.cpu.itb 99max_insts_all_threads=0 100max_insts_any_thread=0 101max_loads_all_threads=0 102max_loads_any_thread=0 103needsTSO=false 104numIQEntries=64 105numPhysCCRegs=0 106numPhysFloatRegs=256 107numPhysIntRegs=256 108numROBEntries=192 109numRobs=1 110numThreads=2	81dispatchWidth=8 82do_checkpoint_insts=true 83do_quiesce=true 84do_statistics_insts=true 85dtb=system.cpu.dtb 86eventq_index=0 87fetchBufferSize=64 88fetchQueueSize=32 89fetchToDecodeDelay=1 90fetchTrapLatency=1 91fetchWidth=8 92forwardComSize=5 93fuPool=system.cpu.fuPool 94function_trace=false 95function_trace_start=0 96iewToCommitDelay=1 97iewToDecodeDelay=1 98iewToFetchDelay=1 99iewToRenameDelay=1 100interrupts=system.cpu.interrupts0 system.cpu.interrupts1 101isa=system.cpu.isa0 system.cpu.isa1 102issueToExecuteDelay=1 103issueWidth=8 104itb=system.cpu.itb 105max_insts_all_threads=0 106max_insts_any_thread=0 107max_loads_all_threads=0 108max_loads_any_thread=0 109needsTSO=false 110numIQEntries=64 111numPhysCCRegs=0 112numPhysFloatRegs=256 113numPhysIntRegs=256 114numROBEntries=192 115numRobs=1 116numThreads=2
	117p_state_clk_gate_bins=20 118p_state_clk_gate_max=1000000000000 119p_state_clk_gate_min=1000 120power_model=Null
111profile=0 112progress_interval=0 113renameToDecodeDelay=1 114renameToFetchDelay=1 115renameToIEWDelay=2 116renameToROBDelay=1 117renameWidth=8 118simpoint_start_insts= 119smtCommitPolicy=RoundRobin 120smtFetchPolicy=SingleThread 121smtIQPolicy=Partitioned 122smtIQThreshold=100 123smtLSQPolicy=Partitioned 124smtLSQThreshold=100 125smtNumFetchingThreads=1 126smtROBPolicy=Partitioned 127smtROBThreshold=100 128socket_id=0 129squashWidth=8 130store_set_clear_period=250000 131switched_out=false 132system=system 133tracer=system.cpu.tracer 134trapLatency=13 135wbWidth=8 136workload=system.cpu.workload0 system.cpu.workload1 137dcache_port=system.cpu.dcache.cpu_side 138icache_port=system.cpu.icache.cpu_side 139 140[system.cpu.branchPred] 141type=TournamentBP 142BTBEntries=4096 143BTBTagSize=16 144RASSize=16 145choiceCtrBits=2 146choicePredictorSize=8192 147eventq_index=0 148globalCtrBits=2 149globalPredictorSize=8192 150indirectHashGHR=true 151indirectHashTargets=true 152indirectPathLength=3 153indirectSets=256 154indirectTagSize=16 155indirectWays=2 156instShiftAmt=2 157localCtrBits=2 158localHistoryTableSize=2048 159localPredictorSize=2048 160numThreads=2 161useIndirect=true 162 163[system.cpu.dcache] 164type=Cache 165children=tags 166addr_ranges=0:18446744073709551615 167assoc=2 168clk_domain=system.cpu_clk_domain 169clusivity=mostly_incl	121profile=0 122progress_interval=0 123renameToDecodeDelay=1 124renameToFetchDelay=1 125renameToIEWDelay=2 126renameToROBDelay=1 127renameWidth=8 128simpoint_start_insts= 129smtCommitPolicy=RoundRobin 130smtFetchPolicy=SingleThread 131smtIQPolicy=Partitioned 132smtIQThreshold=100 133smtLSQPolicy=Partitioned 134smtLSQThreshold=100 135smtNumFetchingThreads=1 136smtROBPolicy=Partitioned 137smtROBThreshold=100 138socket_id=0 139squashWidth=8 140store_set_clear_period=250000 141switched_out=false 142system=system 143tracer=system.cpu.tracer 144trapLatency=13 145wbWidth=8 146workload=system.cpu.workload0 system.cpu.workload1 147dcache_port=system.cpu.dcache.cpu_side 148icache_port=system.cpu.icache.cpu_side 149 150[system.cpu.branchPred] 151type=TournamentBP 152BTBEntries=4096 153BTBTagSize=16 154RASSize=16 155choiceCtrBits=2 156choicePredictorSize=8192 157eventq_index=0 158globalCtrBits=2 159globalPredictorSize=8192 160indirectHashGHR=true 161indirectHashTargets=true 162indirectPathLength=3 163indirectSets=256 164indirectTagSize=16 165indirectWays=2 166instShiftAmt=2 167localCtrBits=2 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=2 171useIndirect=true 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl
	180default_p_state=UNDEFINED
170demand_mshr_reserve=1 171eventq_index=0 172hit_latency=2 173is_read_only=false 174max_miss_count=0 175mshrs=4	181demand_mshr_reserve=1 182eventq_index=0 183hit_latency=2 184is_read_only=false 185max_miss_count=0 186mshrs=4
	187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null
176prefetch_on_access=false 177prefetcher=Null 178response_latency=2 179sequential_access=false 180size=262144 181system=system 182tags=system.cpu.dcache.tags 183tgts_per_mshr=20 184write_buffers=8 185writeback_clean=false 186cpu_side=system.cpu.dcache_port 187mem_side=system.cpu.toL2Bus.slave[1] 188 189[system.cpu.dcache.tags] 190type=LRU 191assoc=2 192block_size=64 193clk_domain=system.cpu_clk_domain	191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=262144 196system=system 197tags=system.cpu.dcache.tags 198tgts_per_mshr=20 199write_buffers=8 200writeback_clean=false 201cpu_side=system.cpu.dcache_port 202mem_side=system.cpu.toL2Bus.slave[1] 203 204[system.cpu.dcache.tags] 205type=LRU 206assoc=2 207block_size=64 208clk_domain=system.cpu_clk_domain
	209default_p_state=UNDEFINED
194eventq_index=0 195hit_latency=2	210eventq_index=0 211hit_latency=2
	212p_state_clk_gate_bins=20 213p_state_clk_gate_max=1000000000000 214p_state_clk_gate_min=1000 215power_model=Null
196sequential_access=false 197size=262144 198 199[system.cpu.dtb] 200type=AlphaTLB 201eventq_index=0 202size=64 203 204[system.cpu.fuPool] 205type=FUPool 206children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 207FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 208eventq_index=0 209 210[system.cpu.fuPool.FUList0] 211type=FUDesc 212children=opList 213count=6 214eventq_index=0 215opList=system.cpu.fuPool.FUList0.opList 216 217[system.cpu.fuPool.FUList0.opList] 218type=OpDesc 219eventq_index=0 220opClass=IntAlu 221opLat=1 222pipelined=true 223 224[system.cpu.fuPool.FUList1] 225type=FUDesc 226children=opList0 opList1 227count=2 228eventq_index=0 229opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 230 231[system.cpu.fuPool.FUList1.opList0] 232type=OpDesc 233eventq_index=0 234opClass=IntMult 235opLat=3 236pipelined=true 237 238[system.cpu.fuPool.FUList1.opList1] 239type=OpDesc 240eventq_index=0 241opClass=IntDiv 242opLat=20 243pipelined=false 244 245[system.cpu.fuPool.FUList2] 246type=FUDesc 247children=opList0 opList1 opList2 248count=4 249eventq_index=0 250opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 251 252[system.cpu.fuPool.FUList2.opList0] 253type=OpDesc 254eventq_index=0 255opClass=FloatAdd 256opLat=2 257pipelined=true 258 259[system.cpu.fuPool.FUList2.opList1] 260type=OpDesc 261eventq_index=0 262opClass=FloatCmp 263opLat=2 264pipelined=true 265 266[system.cpu.fuPool.FUList2.opList2] 267type=OpDesc 268eventq_index=0 269opClass=FloatCvt 270opLat=2 271pipelined=true 272 273[system.cpu.fuPool.FUList3] 274type=FUDesc 275children=opList0 opList1 opList2 276count=2 277eventq_index=0 278opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 279 280[system.cpu.fuPool.FUList3.opList0] 281type=OpDesc 282eventq_index=0 283opClass=FloatMult 284opLat=4 285pipelined=true 286 287[system.cpu.fuPool.FUList3.opList1] 288type=OpDesc 289eventq_index=0 290opClass=FloatDiv 291opLat=12 292pipelined=false 293 294[system.cpu.fuPool.FUList3.opList2] 295type=OpDesc 296eventq_index=0 297opClass=FloatSqrt 298opLat=24 299pipelined=false 300 301[system.cpu.fuPool.FUList4] 302type=FUDesc 303children=opList 304count=0 305eventq_index=0 306opList=system.cpu.fuPool.FUList4.opList 307 308[system.cpu.fuPool.FUList4.opList] 309type=OpDesc 310eventq_index=0 311opClass=MemRead 312opLat=1 313pipelined=true 314 315[system.cpu.fuPool.FUList5] 316type=FUDesc 317children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 318count=4 319eventq_index=0 320opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 321 322[system.cpu.fuPool.FUList5.opList00] 323type=OpDesc 324eventq_index=0 325opClass=SimdAdd 326opLat=1 327pipelined=true 328 329[system.cpu.fuPool.FUList5.opList01] 330type=OpDesc 331eventq_index=0 332opClass=SimdAddAcc 333opLat=1 334pipelined=true 335 336[system.cpu.fuPool.FUList5.opList02] 337type=OpDesc 338eventq_index=0 339opClass=SimdAlu 340opLat=1 341pipelined=true 342 343[system.cpu.fuPool.FUList5.opList03] 344type=OpDesc 345eventq_index=0 346opClass=SimdCmp 347opLat=1 348pipelined=true 349 350[system.cpu.fuPool.FUList5.opList04] 351type=OpDesc 352eventq_index=0 353opClass=SimdCvt 354opLat=1 355pipelined=true 356 357[system.cpu.fuPool.FUList5.opList05] 358type=OpDesc 359eventq_index=0 360opClass=SimdMisc 361opLat=1 362pipelined=true 363 364[system.cpu.fuPool.FUList5.opList06] 365type=OpDesc 366eventq_index=0 367opClass=SimdMult 368opLat=1 369pipelined=true 370 371[system.cpu.fuPool.FUList5.opList07] 372type=OpDesc 373eventq_index=0 374opClass=SimdMultAcc 375opLat=1 376pipelined=true 377 378[system.cpu.fuPool.FUList5.opList08] 379type=OpDesc 380eventq_index=0 381opClass=SimdShift 382opLat=1 383pipelined=true 384 385[system.cpu.fuPool.FUList5.opList09] 386type=OpDesc 387eventq_index=0 388opClass=SimdShiftAcc 389opLat=1 390pipelined=true 391 392[system.cpu.fuPool.FUList5.opList10] 393type=OpDesc 394eventq_index=0 395opClass=SimdSqrt 396opLat=1 397pipelined=true 398 399[system.cpu.fuPool.FUList5.opList11] 400type=OpDesc 401eventq_index=0 402opClass=SimdFloatAdd 403opLat=1 404pipelined=true 405 406[system.cpu.fuPool.FUList5.opList12] 407type=OpDesc 408eventq_index=0 409opClass=SimdFloatAlu 410opLat=1 411pipelined=true 412 413[system.cpu.fuPool.FUList5.opList13] 414type=OpDesc 415eventq_index=0 416opClass=SimdFloatCmp 417opLat=1 418pipelined=true 419 420[system.cpu.fuPool.FUList5.opList14] 421type=OpDesc 422eventq_index=0 423opClass=SimdFloatCvt 424opLat=1 425pipelined=true 426 427[system.cpu.fuPool.FUList5.opList15] 428type=OpDesc 429eventq_index=0 430opClass=SimdFloatDiv 431opLat=1 432pipelined=true 433 434[system.cpu.fuPool.FUList5.opList16] 435type=OpDesc 436eventq_index=0 437opClass=SimdFloatMisc 438opLat=1 439pipelined=true 440 441[system.cpu.fuPool.FUList5.opList17] 442type=OpDesc 443eventq_index=0 444opClass=SimdFloatMult 445opLat=1 446pipelined=true 447 448[system.cpu.fuPool.FUList5.opList18] 449type=OpDesc 450eventq_index=0 451opClass=SimdFloatMultAcc 452opLat=1 453pipelined=true 454 455[system.cpu.fuPool.FUList5.opList19] 456type=OpDesc 457eventq_index=0 458opClass=SimdFloatSqrt 459opLat=1 460pipelined=true 461 462[system.cpu.fuPool.FUList6] 463type=FUDesc 464children=opList 465count=0 466eventq_index=0 467opList=system.cpu.fuPool.FUList6.opList 468 469[system.cpu.fuPool.FUList6.opList] 470type=OpDesc 471eventq_index=0 472opClass=MemWrite 473opLat=1 474pipelined=true 475 476[system.cpu.fuPool.FUList7] 477type=FUDesc 478children=opList0 opList1 479count=4 480eventq_index=0 481opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 482 483[system.cpu.fuPool.FUList7.opList0] 484type=OpDesc 485eventq_index=0 486opClass=MemRead 487opLat=1 488pipelined=true 489 490[system.cpu.fuPool.FUList7.opList1] 491type=OpDesc 492eventq_index=0 493opClass=MemWrite 494opLat=1 495pipelined=true 496 497[system.cpu.fuPool.FUList8] 498type=FUDesc 499children=opList 500count=1 501eventq_index=0 502opList=system.cpu.fuPool.FUList8.opList 503 504[system.cpu.fuPool.FUList8.opList] 505type=OpDesc 506eventq_index=0 507opClass=IprAccess 508opLat=3 509pipelined=false 510 511[system.cpu.icache] 512type=Cache 513children=tags 514addr_ranges=0:18446744073709551615 515assoc=2 516clk_domain=system.cpu_clk_domain 517clusivity=mostly_incl	216sequential_access=false 217size=262144 218 219[system.cpu.dtb] 220type=AlphaTLB 221eventq_index=0 222size=64 223 224[system.cpu.fuPool] 225type=FUPool 226children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 227FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 228eventq_index=0 229 230[system.cpu.fuPool.FUList0] 231type=FUDesc 232children=opList 233count=6 234eventq_index=0 235opList=system.cpu.fuPool.FUList0.opList 236 237[system.cpu.fuPool.FUList0.opList] 238type=OpDesc 239eventq_index=0 240opClass=IntAlu 241opLat=1 242pipelined=true 243 244[system.cpu.fuPool.FUList1] 245type=FUDesc 246children=opList0 opList1 247count=2 248eventq_index=0 249opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 250 251[system.cpu.fuPool.FUList1.opList0] 252type=OpDesc 253eventq_index=0 254opClass=IntMult 255opLat=3 256pipelined=true 257 258[system.cpu.fuPool.FUList1.opList1] 259type=OpDesc 260eventq_index=0 261opClass=IntDiv 262opLat=20 263pipelined=false 264 265[system.cpu.fuPool.FUList2] 266type=FUDesc 267children=opList0 opList1 opList2 268count=4 269eventq_index=0 270opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 271 272[system.cpu.fuPool.FUList2.opList0] 273type=OpDesc 274eventq_index=0 275opClass=FloatAdd 276opLat=2 277pipelined=true 278 279[system.cpu.fuPool.FUList2.opList1] 280type=OpDesc 281eventq_index=0 282opClass=FloatCmp 283opLat=2 284pipelined=true 285 286[system.cpu.fuPool.FUList2.opList2] 287type=OpDesc 288eventq_index=0 289opClass=FloatCvt 290opLat=2 291pipelined=true 292 293[system.cpu.fuPool.FUList3] 294type=FUDesc 295children=opList0 opList1 opList2 296count=2 297eventq_index=0 298opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 299 300[system.cpu.fuPool.FUList3.opList0] 301type=OpDesc 302eventq_index=0 303opClass=FloatMult 304opLat=4 305pipelined=true 306 307[system.cpu.fuPool.FUList3.opList1] 308type=OpDesc 309eventq_index=0 310opClass=FloatDiv 311opLat=12 312pipelined=false 313 314[system.cpu.fuPool.FUList3.opList2] 315type=OpDesc 316eventq_index=0 317opClass=FloatSqrt 318opLat=24 319pipelined=false 320 321[system.cpu.fuPool.FUList4] 322type=FUDesc 323children=opList 324count=0 325eventq_index=0 326opList=system.cpu.fuPool.FUList4.opList 327 328[system.cpu.fuPool.FUList4.opList] 329type=OpDesc 330eventq_index=0 331opClass=MemRead 332opLat=1 333pipelined=true 334 335[system.cpu.fuPool.FUList5] 336type=FUDesc 337children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 338count=4 339eventq_index=0 340opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 341 342[system.cpu.fuPool.FUList5.opList00] 343type=OpDesc 344eventq_index=0 345opClass=SimdAdd 346opLat=1 347pipelined=true 348 349[system.cpu.fuPool.FUList5.opList01] 350type=OpDesc 351eventq_index=0 352opClass=SimdAddAcc 353opLat=1 354pipelined=true 355 356[system.cpu.fuPool.FUList5.opList02] 357type=OpDesc 358eventq_index=0 359opClass=SimdAlu 360opLat=1 361pipelined=true 362 363[system.cpu.fuPool.FUList5.opList03] 364type=OpDesc 365eventq_index=0 366opClass=SimdCmp 367opLat=1 368pipelined=true 369 370[system.cpu.fuPool.FUList5.opList04] 371type=OpDesc 372eventq_index=0 373opClass=SimdCvt 374opLat=1 375pipelined=true 376 377[system.cpu.fuPool.FUList5.opList05] 378type=OpDesc 379eventq_index=0 380opClass=SimdMisc 381opLat=1 382pipelined=true 383 384[system.cpu.fuPool.FUList5.opList06] 385type=OpDesc 386eventq_index=0 387opClass=SimdMult 388opLat=1 389pipelined=true 390 391[system.cpu.fuPool.FUList5.opList07] 392type=OpDesc 393eventq_index=0 394opClass=SimdMultAcc 395opLat=1 396pipelined=true 397 398[system.cpu.fuPool.FUList5.opList08] 399type=OpDesc 400eventq_index=0 401opClass=SimdShift 402opLat=1 403pipelined=true 404 405[system.cpu.fuPool.FUList5.opList09] 406type=OpDesc 407eventq_index=0 408opClass=SimdShiftAcc 409opLat=1 410pipelined=true 411 412[system.cpu.fuPool.FUList5.opList10] 413type=OpDesc 414eventq_index=0 415opClass=SimdSqrt 416opLat=1 417pipelined=true 418 419[system.cpu.fuPool.FUList5.opList11] 420type=OpDesc 421eventq_index=0 422opClass=SimdFloatAdd 423opLat=1 424pipelined=true 425 426[system.cpu.fuPool.FUList5.opList12] 427type=OpDesc 428eventq_index=0 429opClass=SimdFloatAlu 430opLat=1 431pipelined=true 432 433[system.cpu.fuPool.FUList5.opList13] 434type=OpDesc 435eventq_index=0 436opClass=SimdFloatCmp 437opLat=1 438pipelined=true 439 440[system.cpu.fuPool.FUList5.opList14] 441type=OpDesc 442eventq_index=0 443opClass=SimdFloatCvt 444opLat=1 445pipelined=true 446 447[system.cpu.fuPool.FUList5.opList15] 448type=OpDesc 449eventq_index=0 450opClass=SimdFloatDiv 451opLat=1 452pipelined=true 453 454[system.cpu.fuPool.FUList5.opList16] 455type=OpDesc 456eventq_index=0 457opClass=SimdFloatMisc 458opLat=1 459pipelined=true 460 461[system.cpu.fuPool.FUList5.opList17] 462type=OpDesc 463eventq_index=0 464opClass=SimdFloatMult 465opLat=1 466pipelined=true 467 468[system.cpu.fuPool.FUList5.opList18] 469type=OpDesc 470eventq_index=0 471opClass=SimdFloatMultAcc 472opLat=1 473pipelined=true 474 475[system.cpu.fuPool.FUList5.opList19] 476type=OpDesc 477eventq_index=0 478opClass=SimdFloatSqrt 479opLat=1 480pipelined=true 481 482[system.cpu.fuPool.FUList6] 483type=FUDesc 484children=opList 485count=0 486eventq_index=0 487opList=system.cpu.fuPool.FUList6.opList 488 489[system.cpu.fuPool.FUList6.opList] 490type=OpDesc 491eventq_index=0 492opClass=MemWrite 493opLat=1 494pipelined=true 495 496[system.cpu.fuPool.FUList7] 497type=FUDesc 498children=opList0 opList1 499count=4 500eventq_index=0 501opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 502 503[system.cpu.fuPool.FUList7.opList0] 504type=OpDesc 505eventq_index=0 506opClass=MemRead 507opLat=1 508pipelined=true 509 510[system.cpu.fuPool.FUList7.opList1] 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516 517[system.cpu.fuPool.FUList8] 518type=FUDesc 519children=opList 520count=1 521eventq_index=0 522opList=system.cpu.fuPool.FUList8.opList 523 524[system.cpu.fuPool.FUList8.opList] 525type=OpDesc 526eventq_index=0 527opClass=IprAccess 528opLat=3 529pipelined=false 530 531[system.cpu.icache] 532type=Cache 533children=tags 534addr_ranges=0:18446744073709551615 535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl
	538default_p_state=UNDEFINED
518demand_mshr_reserve=1 519eventq_index=0 520hit_latency=2 521is_read_only=true 522max_miss_count=0 523mshrs=4	539demand_mshr_reserve=1 540eventq_index=0 541hit_latency=2 542is_read_only=true 543max_miss_count=0 544mshrs=4
	545p_state_clk_gate_bins=20 546p_state_clk_gate_max=1000000000000 547p_state_clk_gate_min=1000 548power_model=Null
524prefetch_on_access=false 525prefetcher=Null 526response_latency=2 527sequential_access=false 528size=131072 529system=system 530tags=system.cpu.icache.tags 531tgts_per_mshr=20 532write_buffers=8 533writeback_clean=true 534cpu_side=system.cpu.icache_port 535mem_side=system.cpu.toL2Bus.slave[0] 536 537[system.cpu.icache.tags] 538type=LRU 539assoc=2 540block_size=64 541clk_domain=system.cpu_clk_domain	549prefetch_on_access=false 550prefetcher=Null 551response_latency=2 552sequential_access=false 553size=131072 554system=system 555tags=system.cpu.icache.tags 556tgts_per_mshr=20 557write_buffers=8 558writeback_clean=true 559cpu_side=system.cpu.icache_port 560mem_side=system.cpu.toL2Bus.slave[0] 561 562[system.cpu.icache.tags] 563type=LRU 564assoc=2 565block_size=64 566clk_domain=system.cpu_clk_domain
	567default_p_state=UNDEFINED
542eventq_index=0 543hit_latency=2	568eventq_index=0 569hit_latency=2
	570p_state_clk_gate_bins=20 571p_state_clk_gate_max=1000000000000 572p_state_clk_gate_min=1000 573power_model=Null
544sequential_access=false 545size=131072 546 547[system.cpu.interrupts0] 548type=AlphaInterrupts 549eventq_index=0 550 551[system.cpu.interrupts1] 552type=AlphaInterrupts 553eventq_index=0 554 555[system.cpu.isa0] 556type=AlphaISA 557eventq_index=0 558system=system 559 560[system.cpu.isa1] 561type=AlphaISA 562eventq_index=0 563system=system 564 565[system.cpu.itb] 566type=AlphaTLB 567eventq_index=0 568size=48 569 570[system.cpu.l2cache] 571type=Cache 572children=tags 573addr_ranges=0:18446744073709551615 574assoc=8 575clk_domain=system.cpu_clk_domain 576clusivity=mostly_incl	574sequential_access=false 575size=131072 576 577[system.cpu.interrupts0] 578type=AlphaInterrupts 579eventq_index=0 580 581[system.cpu.interrupts1] 582type=AlphaInterrupts 583eventq_index=0 584 585[system.cpu.isa0] 586type=AlphaISA 587eventq_index=0 588system=system 589 590[system.cpu.isa1] 591type=AlphaISA 592eventq_index=0 593system=system 594 595[system.cpu.itb] 596type=AlphaTLB 597eventq_index=0 598size=48 599 600[system.cpu.l2cache] 601type=Cache 602children=tags 603addr_ranges=0:18446744073709551615 604assoc=8 605clk_domain=system.cpu_clk_domain 606clusivity=mostly_incl
	607default_p_state=UNDEFINED
577demand_mshr_reserve=1 578eventq_index=0 579hit_latency=20 580is_read_only=false 581max_miss_count=0 582mshrs=20	608demand_mshr_reserve=1 609eventq_index=0 610hit_latency=20 611is_read_only=false 612max_miss_count=0 613mshrs=20
	614p_state_clk_gate_bins=20 615p_state_clk_gate_max=1000000000000 616p_state_clk_gate_min=1000 617power_model=Null
583prefetch_on_access=false 584prefetcher=Null 585response_latency=20 586sequential_access=false 587size=2097152 588system=system 589tags=system.cpu.l2cache.tags 590tgts_per_mshr=12 591write_buffers=8 592writeback_clean=false 593cpu_side=system.cpu.toL2Bus.master[0] 594mem_side=system.membus.slave[1] 595 596[system.cpu.l2cache.tags] 597type=LRU 598assoc=8 599block_size=64 600clk_domain=system.cpu_clk_domain	618prefetch_on_access=false 619prefetcher=Null 620response_latency=20 621sequential_access=false 622size=2097152 623system=system 624tags=system.cpu.l2cache.tags 625tgts_per_mshr=12 626write_buffers=8 627writeback_clean=false 628cpu_side=system.cpu.toL2Bus.master[0] 629mem_side=system.membus.slave[1] 630 631[system.cpu.l2cache.tags] 632type=LRU 633assoc=8 634block_size=64 635clk_domain=system.cpu_clk_domain
	636default_p_state=UNDEFINED
601eventq_index=0 602hit_latency=20	637eventq_index=0 638hit_latency=20
	639p_state_clk_gate_bins=20 640p_state_clk_gate_max=1000000000000 641p_state_clk_gate_min=1000 642power_model=Null
603sequential_access=false 604size=2097152 605 606[system.cpu.toL2Bus] 607type=CoherentXBar 608children=snoop_filter 609clk_domain=system.cpu_clk_domain	643sequential_access=false 644size=2097152 645 646[system.cpu.toL2Bus] 647type=CoherentXBar 648children=snoop_filter 649clk_domain=system.cpu_clk_domain
	650default_p_state=UNDEFINED
610eventq_index=0 611forward_latency=0 612frontend_latency=1	651eventq_index=0 652forward_latency=0 653frontend_latency=1
	654p_state_clk_gate_bins=20 655p_state_clk_gate_max=1000000000000 656p_state_clk_gate_min=1000
613point_of_coherency=false	657point_of_coherency=false
	658power_model=Null
614response_latency=1 615snoop_filter=system.cpu.toL2Bus.snoop_filter 616snoop_response_latency=1 617system=system 618use_default_range=false 619width=32 620master=system.cpu.l2cache.cpu_side 621slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 622 623[system.cpu.toL2Bus.snoop_filter] 624type=SnoopFilter 625eventq_index=0 626lookup_latency=0 627max_capacity=8388608 628system=system 629 630[system.cpu.tracer] 631type=ExeTracer 632eventq_index=0 633 634[system.cpu.workload0] 635type=LiveProcess 636cmd=hello 637cwd= 638drivers= 639egid=100 640env= 641errout=cerr 642euid=100 643eventq_index=0	659response_latency=1 660snoop_filter=system.cpu.toL2Bus.snoop_filter 661snoop_response_latency=1 662system=system 663use_default_range=false 664width=32 665master=system.cpu.l2cache.cpu_side 666slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 667 668[system.cpu.toL2Bus.snoop_filter] 669type=SnoopFilter 670eventq_index=0 671lookup_latency=0 672max_capacity=8388608 673system=system 674 675[system.cpu.tracer] 676type=ExeTracer 677eventq_index=0 678 679[system.cpu.workload0] 680type=LiveProcess 681cmd=hello 682cwd= 683drivers= 684egid=100 685env= 686errout=cerr 687euid=100 688eventq_index=0
644executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello	689executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
645gid=100 646input=cin 647kvmInSE=false 648max_stack_size=67108864 649output=cout 650pid=100 651ppid=99 652simpoint=0 653system=system 654uid=100 655useArchPT=false 656 657[system.cpu.workload1] 658type=LiveProcess 659cmd=hello 660cwd= 661drivers= 662egid=100 663env= 664errout=cerr 665euid=100 666eventq_index=0	690gid=100 691input=cin 692kvmInSE=false 693max_stack_size=67108864 694output=cout 695pid=100 696ppid=99 697simpoint=0 698system=system 699uid=100 700useArchPT=false 701 702[system.cpu.workload1] 703type=LiveProcess 704cmd=hello 705cwd= 706drivers= 707egid=100 708env= 709errout=cerr 710euid=100 711eventq_index=0
667executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello	712executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/alpha/linux/hello
668gid=100 669input=cin 670kvmInSE=false 671max_stack_size=67108864 672output=cout 673pid=100 674ppid=99 675simpoint=0 676system=system 677uid=100 678useArchPT=false 679 680[system.cpu_clk_domain] 681type=SrcClockDomain 682clock=500 683domain_id=-1 684eventq_index=0 685init_perf_level=0 686voltage_domain=system.voltage_domain 687 688[system.dvfs_handler] 689type=DVFSHandler 690domains= 691enable=false 692eventq_index=0 693sys_clk_domain=system.clk_domain 694transition_latency=100000000 695 696[system.membus] 697type=CoherentXBar 698clk_domain=system.clk_domain	713gid=100 714input=cin 715kvmInSE=false 716max_stack_size=67108864 717output=cout 718pid=100 719ppid=99 720simpoint=0 721system=system 722uid=100 723useArchPT=false 724 725[system.cpu_clk_domain] 726type=SrcClockDomain 727clock=500 728domain_id=-1 729eventq_index=0 730init_perf_level=0 731voltage_domain=system.voltage_domain 732 733[system.dvfs_handler] 734type=DVFSHandler 735domains= 736enable=false 737eventq_index=0 738sys_clk_domain=system.clk_domain 739transition_latency=100000000 740 741[system.membus] 742type=CoherentXBar 743clk_domain=system.clk_domain
	744default_p_state=UNDEFINED
699eventq_index=0 700forward_latency=4 701frontend_latency=3	745eventq_index=0 746forward_latency=4 747frontend_latency=3
	748p_state_clk_gate_bins=20 749p_state_clk_gate_max=1000000000000 750p_state_clk_gate_min=1000
702point_of_coherency=true	751point_of_coherency=true
	752power_model=Null
703response_latency=2 704snoop_filter=Null 705snoop_response_latency=4 706system=system 707use_default_range=false 708width=16 709master=system.physmem.port 710slave=system.system_port system.cpu.l2cache.mem_side 711 712[system.physmem] 713type=DRAMCtrl 714IDD0=0.075000 715IDD02=0.000000 716IDD2N=0.050000 717IDD2N2=0.000000 718IDD2P0=0.000000 719IDD2P02=0.000000 720IDD2P1=0.000000 721IDD2P12=0.000000 722IDD3N=0.057000 723IDD3N2=0.000000 724IDD3P0=0.000000 725IDD3P02=0.000000 726IDD3P1=0.000000 727IDD3P12=0.000000 728IDD4R=0.187000 729IDD4R2=0.000000 730IDD4W=0.165000 731IDD4W2=0.000000 732IDD5=0.220000 733IDD52=0.000000 734IDD6=0.000000 735IDD62=0.000000 736VDD=1.500000 737VDD2=0.000000 738activation_limit=4 739addr_mapping=RoRaBaCoCh 740bank_groups_per_rank=0 741banks_per_rank=8 742burst_length=8 743channels=1 744clk_domain=system.clk_domain 745conf_table_reported=true	753response_latency=2 754snoop_filter=Null 755snoop_response_latency=4 756system=system 757use_default_range=false 758width=16 759master=system.physmem.port 760slave=system.system_port system.cpu.l2cache.mem_side 761 762[system.physmem] 763type=DRAMCtrl 764IDD0=0.075000 765IDD02=0.000000 766IDD2N=0.050000 767IDD2N2=0.000000 768IDD2P0=0.000000 769IDD2P02=0.000000 770IDD2P1=0.000000 771IDD2P12=0.000000 772IDD3N=0.057000 773IDD3N2=0.000000 774IDD3P0=0.000000 775IDD3P02=0.000000 776IDD3P1=0.000000 777IDD3P12=0.000000 778IDD4R=0.187000 779IDD4R2=0.000000 780IDD4W=0.165000 781IDD4W2=0.000000 782IDD5=0.220000 783IDD52=0.000000 784IDD6=0.000000 785IDD62=0.000000 786VDD=1.500000 787VDD2=0.000000 788activation_limit=4 789addr_mapping=RoRaBaCoCh 790bank_groups_per_rank=0 791banks_per_rank=8 792burst_length=8 793channels=1 794clk_domain=system.clk_domain 795conf_table_reported=true
	796default_p_state=UNDEFINED
746device_bus_width=8 747device_rowbuffer_size=1024 748device_size=536870912 749devices_per_rank=8 750dll=true 751eventq_index=0 752in_addr_map=true 753max_accesses_per_row=16 754mem_sched_policy=frfcfs 755min_writes_per_switch=16 756null=false	797device_bus_width=8 798device_rowbuffer_size=1024 799device_size=536870912 800devices_per_rank=8 801dll=true 802eventq_index=0 803in_addr_map=true 804max_accesses_per_row=16 805mem_sched_policy=frfcfs 806min_writes_per_switch=16 807null=false
	808p_state_clk_gate_bins=20 809p_state_clk_gate_max=1000000000000 810p_state_clk_gate_min=1000
757page_policy=open_adaptive	811page_policy=open_adaptive
	812power_model=Null
758range=0:134217727 759ranks_per_channel=2 760read_buffer_size=32 761static_backend_latency=10000 762static_frontend_latency=10000 763tBURST=5000 764tCCD_L=0 765tCK=1250 766tCL=13750 767tCS=2500 768tRAS=35000 769tRCD=13750 770tREFI=7800000 771tRFC=260000 772tRP=13750 773tRRD=6000 774tRRD_L=0 775tRTP=7500 776tRTW=2500 777tWR=15000 778tWTR=7500 779tXAW=30000 780tXP=0 781tXPDLL=0 782tXS=0 783tXSDLL=0 784write_buffer_size=64 785write_high_thresh_perc=85 786write_low_thresh_perc=50 787port=system.membus.master[0] 788 789[system.voltage_domain] 790type=VoltageDomain 791eventq_index=0 792voltage=1.000000 793	813range=0:134217727 814ranks_per_channel=2 815read_buffer_size=32 816static_backend_latency=10000 817static_frontend_latency=10000 818tBURST=5000 819tCCD_L=0 820tCK=1250 821tCL=13750 822tCS=2500 823tRAS=35000 824tRCD=13750 825tREFI=7800000 826tRFC=260000 827tRP=13750 828tRRD=6000 829tRRD_L=0 830tRTP=7500 831tRTW=2500 832tWR=15000 833tWTR=7500 834tXAW=30000 835tXP=0 836tXPDLL=0 837tXS=0 838tXSDLL=0 839write_buffer_size=64 840write_high_thresh_perc=85 841write_low_thresh_perc=50 842port=system.membus.master[0] 843 844[system.voltage_domain] 845type=VoltageDomain 846eventq_index=0 847voltage=1.000000 848