1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=System
13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17eventq_index=0
18exit_on_work_items=false
19init_param=0
20kernel=
21kernel_addr_check=true
22load_addr_mask=1099511627775
23load_offset=0
24mem_mode=timing
25mem_ranges=
26memories=system.physmem
27mmap_using_noreserve=false
28multi_thread=true
29num_work_ids=16
30readfile=
31symbolfile=
32thermal_components=
33thermal_model=Null
34work_begin_ckpt_count=0
35work_begin_cpu_id_exit=-1
36work_begin_exit_count=0
37work_cpus_ckpt_count=0
38work_end_ckpt_count=0
39work_end_exit_count=0
40work_item_id=-1
41system_port=system.membus.slave[0]
42
43[system.clk_domain]
44type=SrcClockDomain
45clock=1000
46domain_id=-1
47eventq_index=0
48init_perf_level=0
49voltage_domain=system.voltage_domain
50
51[system.cpu]
52type=DerivO3CPU
53children=branchPred dcache dtb fuPool icache interrupts0 interrupts1 isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1
54LFSTSize=1024
55LQEntries=32
56LSQCheckLoads=true
57LSQDepCheckShift=4
58SQEntries=32
59SSITSize=1024
60activity=0
61backComSize=5
62branchPred=system.cpu.branchPred
63cachePorts=200
64checker=Null
65clk_domain=system.cpu_clk_domain
66commitToDecodeDelay=1
67commitToFetchDelay=1
68commitToIEWDelay=1
69commitToRenameDelay=1
70commitWidth=8
71cpu_id=0
72decodeToFetchDelay=1
73decodeToRenameDelay=1
74decodeWidth=8
75dispatchWidth=8
76do_checkpoint_insts=true
77do_quiesce=true
78do_statistics_insts=true
79dtb=system.cpu.dtb
80eventq_index=0
81fetchBufferSize=64
82fetchQueueSize=32
83fetchToDecodeDelay=1
84fetchTrapLatency=1
85fetchWidth=8
86forwardComSize=5
87fuPool=system.cpu.fuPool
88function_trace=false
89function_trace_start=0
90iewToCommitDelay=1
91iewToDecodeDelay=1
92iewToFetchDelay=1
93iewToRenameDelay=1
94interrupts=system.cpu.interrupts0 system.cpu.interrupts1
95isa=system.cpu.isa0 system.cpu.isa1
96issueToExecuteDelay=1
97issueWidth=8
98itb=system.cpu.itb
99max_insts_all_threads=0
100max_insts_any_thread=0
101max_loads_all_threads=0
102max_loads_any_thread=0
103needsTSO=false
104numIQEntries=64
105numPhysCCRegs=0
106numPhysFloatRegs=256
107numPhysIntRegs=256
108numROBEntries=192
109numRobs=1
110numThreads=2
111profile=0
112progress_interval=0
113renameToDecodeDelay=1
114renameToFetchDelay=1
115renameToIEWDelay=2
116renameToROBDelay=1
117renameWidth=8
118simpoint_start_insts=
119smtCommitPolicy=RoundRobin
120smtFetchPolicy=SingleThread
121smtIQPolicy=Partitioned
122smtIQThreshold=100
123smtLSQPolicy=Partitioned
124smtLSQThreshold=100
125smtNumFetchingThreads=1
126smtROBPolicy=Partitioned
127smtROBThreshold=100
128socket_id=0
129squashWidth=8
130store_set_clear_period=250000
131switched_out=false
132system=system
133tracer=system.cpu.tracer
134trapLatency=13
135wbWidth=8
136workload=system.cpu.workload0 system.cpu.workload1
137dcache_port=system.cpu.dcache.cpu_side
138icache_port=system.cpu.icache.cpu_side
139
140[system.cpu.branchPred]
141type=TournamentBP
142BTBEntries=4096
143BTBTagSize=16
144RASSize=16
145choiceCtrBits=2
146choicePredictorSize=8192
147eventq_index=0
148globalCtrBits=2
149globalPredictorSize=8192
150indirectHashGHR=true
151indirectHashTargets=true
152indirectPathLength=3
153indirectSets=256
154indirectTagSize=16
155indirectWays=2
156instShiftAmt=2
157localCtrBits=2
158localHistoryTableSize=2048
159localPredictorSize=2048
160numThreads=2
161useIndirect=true
162
163[system.cpu.dcache]
164type=Cache
165children=tags
166addr_ranges=0:18446744073709551615
167assoc=2
168clk_domain=system.cpu_clk_domain
169clusivity=mostly_incl
170demand_mshr_reserve=1
171eventq_index=0
172hit_latency=2
173is_read_only=false
174max_miss_count=0
175mshrs=4
176prefetch_on_access=false
177prefetcher=Null
178response_latency=2
179sequential_access=false
180size=262144
181system=system
182tags=system.cpu.dcache.tags
183tgts_per_mshr=20
184write_buffers=8
185writeback_clean=false
186cpu_side=system.cpu.dcache_port
187mem_side=system.cpu.toL2Bus.slave[1]
188
189[system.cpu.dcache.tags]
190type=LRU
191assoc=2
192block_size=64
193clk_domain=system.cpu_clk_domain
194eventq_index=0
195hit_latency=2
196sequential_access=false
197size=262144
198
199[system.cpu.dtb]
200type=AlphaTLB
201eventq_index=0
202size=64
203
204[system.cpu.fuPool]
205type=FUPool
206children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
207FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
208eventq_index=0
209
210[system.cpu.fuPool.FUList0]
211type=FUDesc
212children=opList
213count=6
214eventq_index=0
215opList=system.cpu.fuPool.FUList0.opList
216
217[system.cpu.fuPool.FUList0.opList]
218type=OpDesc
219eventq_index=0
220opClass=IntAlu
221opLat=1
222pipelined=true
223
224[system.cpu.fuPool.FUList1]
225type=FUDesc
226children=opList0 opList1
227count=2
228eventq_index=0
229opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
230
231[system.cpu.fuPool.FUList1.opList0]
232type=OpDesc
233eventq_index=0
234opClass=IntMult
235opLat=3
236pipelined=true
237
238[system.cpu.fuPool.FUList1.opList1]
239type=OpDesc
240eventq_index=0
241opClass=IntDiv
242opLat=20
243pipelined=false
244
245[system.cpu.fuPool.FUList2]
246type=FUDesc
247children=opList0 opList1 opList2
248count=4
249eventq_index=0
250opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
251
252[system.cpu.fuPool.FUList2.opList0]
253type=OpDesc
254eventq_index=0
255opClass=FloatAdd
256opLat=2
257pipelined=true
258
259[system.cpu.fuPool.FUList2.opList1]
260type=OpDesc
261eventq_index=0
262opClass=FloatCmp
263opLat=2
264pipelined=true
265
266[system.cpu.fuPool.FUList2.opList2]
267type=OpDesc
268eventq_index=0
269opClass=FloatCvt
270opLat=2
271pipelined=true
272
273[system.cpu.fuPool.FUList3]
274type=FUDesc
275children=opList0 opList1 opList2
276count=2
277eventq_index=0
278opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
279
280[system.cpu.fuPool.FUList3.opList0]
281type=OpDesc
282eventq_index=0
283opClass=FloatMult
284opLat=4
285pipelined=true
286
287[system.cpu.fuPool.FUList3.opList1]
288type=OpDesc
289eventq_index=0
290opClass=FloatDiv
291opLat=12
292pipelined=false
293
294[system.cpu.fuPool.FUList3.opList2]
295type=OpDesc
296eventq_index=0
297opClass=FloatSqrt
298opLat=24
299pipelined=false
300
301[system.cpu.fuPool.FUList4]
302type=FUDesc
303children=opList
304count=0
305eventq_index=0
306opList=system.cpu.fuPool.FUList4.opList
307
308[system.cpu.fuPool.FUList4.opList]
309type=OpDesc
310eventq_index=0
311opClass=MemRead
312opLat=1
313pipelined=true
314
315[system.cpu.fuPool.FUList5]
316type=FUDesc
317children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
318count=4
319eventq_index=0
320opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
321
322[system.cpu.fuPool.FUList5.opList00]
323type=OpDesc
324eventq_index=0
325opClass=SimdAdd
326opLat=1
327pipelined=true
328
329[system.cpu.fuPool.FUList5.opList01]
330type=OpDesc
331eventq_index=0
332opClass=SimdAddAcc
333opLat=1
334pipelined=true
335
336[system.cpu.fuPool.FUList5.opList02]
337type=OpDesc
338eventq_index=0
339opClass=SimdAlu
340opLat=1
341pipelined=true
342
343[system.cpu.fuPool.FUList5.opList03]
344type=OpDesc
345eventq_index=0
346opClass=SimdCmp
347opLat=1
348pipelined=true
349
350[system.cpu.fuPool.FUList5.opList04]
351type=OpDesc
352eventq_index=0
353opClass=SimdCvt
354opLat=1
355pipelined=true
356
357[system.cpu.fuPool.FUList5.opList05]
358type=OpDesc
359eventq_index=0
360opClass=SimdMisc
361opLat=1
362pipelined=true
363
364[system.cpu.fuPool.FUList5.opList06]
365type=OpDesc
366eventq_index=0
367opClass=SimdMult
368opLat=1
369pipelined=true
370
371[system.cpu.fuPool.FUList5.opList07]
372type=OpDesc
373eventq_index=0
374opClass=SimdMultAcc
375opLat=1
376pipelined=true
377
378[system.cpu.fuPool.FUList5.opList08]
379type=OpDesc
380eventq_index=0
381opClass=SimdShift
382opLat=1
383pipelined=true
384
385[system.cpu.fuPool.FUList5.opList09]
386type=OpDesc
387eventq_index=0
388opClass=SimdShiftAcc
389opLat=1
390pipelined=true
391
392[system.cpu.fuPool.FUList5.opList10]
393type=OpDesc
394eventq_index=0
395opClass=SimdSqrt
396opLat=1
397pipelined=true
398
399[system.cpu.fuPool.FUList5.opList11]
400type=OpDesc
401eventq_index=0
402opClass=SimdFloatAdd
403opLat=1
404pipelined=true
405
406[system.cpu.fuPool.FUList5.opList12]
407type=OpDesc
408eventq_index=0
409opClass=SimdFloatAlu
410opLat=1
411pipelined=true
412
413[system.cpu.fuPool.FUList5.opList13]
414type=OpDesc
415eventq_index=0
416opClass=SimdFloatCmp
417opLat=1
418pipelined=true
419
420[system.cpu.fuPool.FUList5.opList14]
421type=OpDesc
422eventq_index=0
423opClass=SimdFloatCvt
424opLat=1
425pipelined=true
426
427[system.cpu.fuPool.FUList5.opList15]
428type=OpDesc
429eventq_index=0
430opClass=SimdFloatDiv
431opLat=1
432pipelined=true
433
434[system.cpu.fuPool.FUList5.opList16]
435type=OpDesc
436eventq_index=0
437opClass=SimdFloatMisc
438opLat=1
439pipelined=true
440
441[system.cpu.fuPool.FUList5.opList17]
442type=OpDesc
443eventq_index=0
444opClass=SimdFloatMult
445opLat=1
446pipelined=true
447
448[system.cpu.fuPool.FUList5.opList18]
449type=OpDesc
450eventq_index=0
451opClass=SimdFloatMultAcc
452opLat=1
453pipelined=true
454
455[system.cpu.fuPool.FUList5.opList19]
456type=OpDesc
457eventq_index=0
458opClass=SimdFloatSqrt
459opLat=1
460pipelined=true
461
462[system.cpu.fuPool.FUList6]
463type=FUDesc
464children=opList
465count=0
466eventq_index=0
467opList=system.cpu.fuPool.FUList6.opList
468
469[system.cpu.fuPool.FUList6.opList]
470type=OpDesc
471eventq_index=0
472opClass=MemWrite
473opLat=1
474pipelined=true
475
476[system.cpu.fuPool.FUList7]
477type=FUDesc
478children=opList0 opList1
479count=4
480eventq_index=0
481opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
482
483[system.cpu.fuPool.FUList7.opList0]
484type=OpDesc
485eventq_index=0
486opClass=MemRead
487opLat=1
488pipelined=true
489
490[system.cpu.fuPool.FUList7.opList1]
491type=OpDesc
492eventq_index=0
493opClass=MemWrite
494opLat=1
495pipelined=true
496
497[system.cpu.fuPool.FUList8]
498type=FUDesc
499children=opList
500count=1
501eventq_index=0
502opList=system.cpu.fuPool.FUList8.opList
503
504[system.cpu.fuPool.FUList8.opList]
505type=OpDesc
506eventq_index=0
507opClass=IprAccess
508opLat=3
509pipelined=false
510
511[system.cpu.icache]
512type=Cache
513children=tags
514addr_ranges=0:18446744073709551615
515assoc=2
516clk_domain=system.cpu_clk_domain
517clusivity=mostly_incl
518demand_mshr_reserve=1
519eventq_index=0
520hit_latency=2
521is_read_only=true
522max_miss_count=0
523mshrs=4
524prefetch_on_access=false
525prefetcher=Null
526response_latency=2
527sequential_access=false
528size=131072
529system=system
530tags=system.cpu.icache.tags
531tgts_per_mshr=20
532write_buffers=8
533writeback_clean=true
534cpu_side=system.cpu.icache_port
535mem_side=system.cpu.toL2Bus.slave[0]
536
537[system.cpu.icache.tags]
538type=LRU
539assoc=2
540block_size=64
541clk_domain=system.cpu_clk_domain
542eventq_index=0
543hit_latency=2
544sequential_access=false
545size=131072
546
547[system.cpu.interrupts0]
548type=AlphaInterrupts
549eventq_index=0
550
551[system.cpu.interrupts1]
552type=AlphaInterrupts
553eventq_index=0
554
555[system.cpu.isa0]
556type=AlphaISA
557eventq_index=0
558system=system
559
560[system.cpu.isa1]
561type=AlphaISA
562eventq_index=0
563system=system
564
565[system.cpu.itb]
566type=AlphaTLB
567eventq_index=0
568size=48
569
570[system.cpu.l2cache]
571type=Cache
572children=tags
573addr_ranges=0:18446744073709551615
574assoc=8
575clk_domain=system.cpu_clk_domain
576clusivity=mostly_incl
577demand_mshr_reserve=1
578eventq_index=0
579hit_latency=20
580is_read_only=false
581max_miss_count=0
582mshrs=20
583prefetch_on_access=false
584prefetcher=Null
585response_latency=20
586sequential_access=false
587size=2097152
588system=system
589tags=system.cpu.l2cache.tags
590tgts_per_mshr=12
591write_buffers=8
592writeback_clean=false
593cpu_side=system.cpu.toL2Bus.master[0]
594mem_side=system.membus.slave[1]
595
596[system.cpu.l2cache.tags]
597type=LRU
598assoc=8
599block_size=64
600clk_domain=system.cpu_clk_domain
601eventq_index=0
602hit_latency=20
603sequential_access=false
604size=2097152
605
606[system.cpu.toL2Bus]
607type=CoherentXBar
608children=snoop_filter
609clk_domain=system.cpu_clk_domain
610eventq_index=0
611forward_latency=0
612frontend_latency=1
613point_of_coherency=false
614response_latency=1
615snoop_filter=system.cpu.toL2Bus.snoop_filter
616snoop_response_latency=1
617system=system
618use_default_range=false
619width=32
620master=system.cpu.l2cache.cpu_side
621slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
622
623[system.cpu.toL2Bus.snoop_filter]
624type=SnoopFilter
625eventq_index=0
626lookup_latency=0
627max_capacity=8388608
628system=system
629
630[system.cpu.tracer]
631type=ExeTracer
632eventq_index=0
633
634[system.cpu.workload0]
635type=LiveProcess
636cmd=hello
637cwd=
638drivers=
639egid=100
640env=
641errout=cerr
642euid=100
643eventq_index=0
644executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
645gid=100
646input=cin
647kvmInSE=false
648max_stack_size=67108864
649output=cout
650pid=100
651ppid=99
652simpoint=0
653system=system
654uid=100
655useArchPT=false
656
657[system.cpu.workload1]
658type=LiveProcess
659cmd=hello
660cwd=
661drivers=
662egid=100
663env=
664errout=cerr
665euid=100
666eventq_index=0
667executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
668gid=100
669input=cin
670kvmInSE=false
671max_stack_size=67108864
672output=cout
673pid=100
674ppid=99
675simpoint=0
676system=system
677uid=100
678useArchPT=false
679
680[system.cpu_clk_domain]
681type=SrcClockDomain
682clock=500
683domain_id=-1
684eventq_index=0
685init_perf_level=0
686voltage_domain=system.voltage_domain
687
688[system.dvfs_handler]
689type=DVFSHandler
690domains=
691enable=false
692eventq_index=0
693sys_clk_domain=system.clk_domain
694transition_latency=100000000
695
696[system.membus]
697type=CoherentXBar
698clk_domain=system.clk_domain
699eventq_index=0
700forward_latency=4
701frontend_latency=3
702point_of_coherency=true
703response_latency=2
704snoop_filter=Null
705snoop_response_latency=4
706system=system
707use_default_range=false
708width=16
709master=system.physmem.port
710slave=system.system_port system.cpu.l2cache.mem_side
711
712[system.physmem]
713type=DRAMCtrl
714IDD0=0.075000
715IDD02=0.000000
716IDD2N=0.050000
717IDD2N2=0.000000
718IDD2P0=0.000000
719IDD2P02=0.000000
720IDD2P1=0.000000
721IDD2P12=0.000000
722IDD3N=0.057000
723IDD3N2=0.000000
724IDD3P0=0.000000
725IDD3P02=0.000000
726IDD3P1=0.000000
727IDD3P12=0.000000
728IDD4R=0.187000
729IDD4R2=0.000000
730IDD4W=0.165000
731IDD4W2=0.000000
732IDD5=0.220000
733IDD52=0.000000
734IDD6=0.000000
735IDD62=0.000000
736VDD=1.500000
737VDD2=0.000000
738activation_limit=4
739addr_mapping=RoRaBaCoCh
740bank_groups_per_rank=0
741banks_per_rank=8
742burst_length=8
743channels=1
744clk_domain=system.clk_domain
745conf_table_reported=true
746device_bus_width=8
747device_rowbuffer_size=1024
748device_size=536870912
749devices_per_rank=8
750dll=true
751eventq_index=0
752in_addr_map=true
753max_accesses_per_row=16
754mem_sched_policy=frfcfs
755min_writes_per_switch=16
756null=false
757page_policy=open_adaptive
758range=0:134217727
759ranks_per_channel=2
760read_buffer_size=32
761static_backend_latency=10000
762static_frontend_latency=10000
763tBURST=5000
764tCCD_L=0
765tCK=1250
766tCL=13750
767tCS=2500
768tRAS=35000
769tRCD=13750
770tREFI=7800000
771tRFC=260000
772tRP=13750
773tRRD=6000
774tRRD_L=0
775tRTP=7500
776tRTW=2500
777tWR=15000
778tWTR=7500
779tXAW=30000
780tXP=0
781tXPDLL=0
782tXS=0
783tXSDLL=0
784write_buffer_size=64
785write_high_thresh_perc=85
786write_low_thresh_perc=50
787port=system.membus.master[0]
788
789[system.voltage_domain]
790type=VoltageDomain
791eventq_index=0
792voltage=1.000000
793
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=System
13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17eventq_index=0
18exit_on_work_items=false
19init_param=0
20kernel=
21kernel_addr_check=true
22load_addr_mask=1099511627775
23load_offset=0
24mem_mode=timing
25mem_ranges=
26memories=system.physmem
27mmap_using_noreserve=false
28multi_thread=true
29num_work_ids=16
30readfile=
31symbolfile=
32thermal_components=
33thermal_model=Null
34work_begin_ckpt_count=0
35work_begin_cpu_id_exit=-1
36work_begin_exit_count=0
37work_cpus_ckpt_count=0
38work_end_ckpt_count=0
39work_end_exit_count=0
40work_item_id=-1
41system_port=system.membus.slave[0]
42
43[system.clk_domain]
44type=SrcClockDomain
45clock=1000
46domain_id=-1
47eventq_index=0
48init_perf_level=0
49voltage_domain=system.voltage_domain
50
51[system.cpu]
52type=DerivO3CPU
53children=branchPred dcache dtb fuPool icache interrupts0 interrupts1 isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1
54LFSTSize=1024
55LQEntries=32
56LSQCheckLoads=true
57LSQDepCheckShift=4
58SQEntries=32
59SSITSize=1024
60activity=0
61backComSize=5
62branchPred=system.cpu.branchPred
63cachePorts=200
64checker=Null
65clk_domain=system.cpu_clk_domain
66commitToDecodeDelay=1
67commitToFetchDelay=1
68commitToIEWDelay=1
69commitToRenameDelay=1
70commitWidth=8
71cpu_id=0
72decodeToFetchDelay=1
73decodeToRenameDelay=1
74decodeWidth=8
75dispatchWidth=8
76do_checkpoint_insts=true
77do_quiesce=true
78do_statistics_insts=true
79dtb=system.cpu.dtb
80eventq_index=0
81fetchBufferSize=64
82fetchQueueSize=32
83fetchToDecodeDelay=1
84fetchTrapLatency=1
85fetchWidth=8
86forwardComSize=5
87fuPool=system.cpu.fuPool
88function_trace=false
89function_trace_start=0
90iewToCommitDelay=1
91iewToDecodeDelay=1
92iewToFetchDelay=1
93iewToRenameDelay=1
94interrupts=system.cpu.interrupts0 system.cpu.interrupts1
95isa=system.cpu.isa0 system.cpu.isa1
96issueToExecuteDelay=1
97issueWidth=8
98itb=system.cpu.itb
99max_insts_all_threads=0
100max_insts_any_thread=0
101max_loads_all_threads=0
102max_loads_any_thread=0
103needsTSO=false
104numIQEntries=64
105numPhysCCRegs=0
106numPhysFloatRegs=256
107numPhysIntRegs=256
108numROBEntries=192
109numRobs=1
110numThreads=2
111profile=0
112progress_interval=0
113renameToDecodeDelay=1
114renameToFetchDelay=1
115renameToIEWDelay=2
116renameToROBDelay=1
117renameWidth=8
118simpoint_start_insts=
119smtCommitPolicy=RoundRobin
120smtFetchPolicy=SingleThread
121smtIQPolicy=Partitioned
122smtIQThreshold=100
123smtLSQPolicy=Partitioned
124smtLSQThreshold=100
125smtNumFetchingThreads=1
126smtROBPolicy=Partitioned
127smtROBThreshold=100
128socket_id=0
129squashWidth=8
130store_set_clear_period=250000
131switched_out=false
132system=system
133tracer=system.cpu.tracer
134trapLatency=13
135wbWidth=8
136workload=system.cpu.workload0 system.cpu.workload1
137dcache_port=system.cpu.dcache.cpu_side
138icache_port=system.cpu.icache.cpu_side
139
140[system.cpu.branchPred]
141type=TournamentBP
142BTBEntries=4096
143BTBTagSize=16
144RASSize=16
145choiceCtrBits=2
146choicePredictorSize=8192
147eventq_index=0
148globalCtrBits=2
149globalPredictorSize=8192
150indirectHashGHR=true
151indirectHashTargets=true
152indirectPathLength=3
153indirectSets=256
154indirectTagSize=16
155indirectWays=2
156instShiftAmt=2
157localCtrBits=2
158localHistoryTableSize=2048
159localPredictorSize=2048
160numThreads=2
161useIndirect=true
162
163[system.cpu.dcache]
164type=Cache
165children=tags
166addr_ranges=0:18446744073709551615
167assoc=2
168clk_domain=system.cpu_clk_domain
169clusivity=mostly_incl
170demand_mshr_reserve=1
171eventq_index=0
172hit_latency=2
173is_read_only=false
174max_miss_count=0
175mshrs=4
176prefetch_on_access=false
177prefetcher=Null
178response_latency=2
179sequential_access=false
180size=262144
181system=system
182tags=system.cpu.dcache.tags
183tgts_per_mshr=20
184write_buffers=8
185writeback_clean=false
186cpu_side=system.cpu.dcache_port
187mem_side=system.cpu.toL2Bus.slave[1]
188
189[system.cpu.dcache.tags]
190type=LRU
191assoc=2
192block_size=64
193clk_domain=system.cpu_clk_domain
194eventq_index=0
195hit_latency=2
196sequential_access=false
197size=262144
198
199[system.cpu.dtb]
200type=AlphaTLB
201eventq_index=0
202size=64
203
204[system.cpu.fuPool]
205type=FUPool
206children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
207FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
208eventq_index=0
209
210[system.cpu.fuPool.FUList0]
211type=FUDesc
212children=opList
213count=6
214eventq_index=0
215opList=system.cpu.fuPool.FUList0.opList
216
217[system.cpu.fuPool.FUList0.opList]
218type=OpDesc
219eventq_index=0
220opClass=IntAlu
221opLat=1
222pipelined=true
223
224[system.cpu.fuPool.FUList1]
225type=FUDesc
226children=opList0 opList1
227count=2
228eventq_index=0
229opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
230
231[system.cpu.fuPool.FUList1.opList0]
232type=OpDesc
233eventq_index=0
234opClass=IntMult
235opLat=3
236pipelined=true
237
238[system.cpu.fuPool.FUList1.opList1]
239type=OpDesc
240eventq_index=0
241opClass=IntDiv
242opLat=20
243pipelined=false
244
245[system.cpu.fuPool.FUList2]
246type=FUDesc
247children=opList0 opList1 opList2
248count=4
249eventq_index=0
250opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
251
252[system.cpu.fuPool.FUList2.opList0]
253type=OpDesc
254eventq_index=0
255opClass=FloatAdd
256opLat=2
257pipelined=true
258
259[system.cpu.fuPool.FUList2.opList1]
260type=OpDesc
261eventq_index=0
262opClass=FloatCmp
263opLat=2
264pipelined=true
265
266[system.cpu.fuPool.FUList2.opList2]
267type=OpDesc
268eventq_index=0
269opClass=FloatCvt
270opLat=2
271pipelined=true
272
273[system.cpu.fuPool.FUList3]
274type=FUDesc
275children=opList0 opList1 opList2
276count=2
277eventq_index=0
278opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
279
280[system.cpu.fuPool.FUList3.opList0]
281type=OpDesc
282eventq_index=0
283opClass=FloatMult
284opLat=4
285pipelined=true
286
287[system.cpu.fuPool.FUList3.opList1]
288type=OpDesc
289eventq_index=0
290opClass=FloatDiv
291opLat=12
292pipelined=false
293
294[system.cpu.fuPool.FUList3.opList2]
295type=OpDesc
296eventq_index=0
297opClass=FloatSqrt
298opLat=24
299pipelined=false
300
301[system.cpu.fuPool.FUList4]
302type=FUDesc
303children=opList
304count=0
305eventq_index=0
306opList=system.cpu.fuPool.FUList4.opList
307
308[system.cpu.fuPool.FUList4.opList]
309type=OpDesc
310eventq_index=0
311opClass=MemRead
312opLat=1
313pipelined=true
314
315[system.cpu.fuPool.FUList5]
316type=FUDesc
317children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
318count=4
319eventq_index=0
320opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
321
322[system.cpu.fuPool.FUList5.opList00]
323type=OpDesc
324eventq_index=0
325opClass=SimdAdd
326opLat=1
327pipelined=true
328
329[system.cpu.fuPool.FUList5.opList01]
330type=OpDesc
331eventq_index=0
332opClass=SimdAddAcc
333opLat=1
334pipelined=true
335
336[system.cpu.fuPool.FUList5.opList02]
337type=OpDesc
338eventq_index=0
339opClass=SimdAlu
340opLat=1
341pipelined=true
342
343[system.cpu.fuPool.FUList5.opList03]
344type=OpDesc
345eventq_index=0
346opClass=SimdCmp
347opLat=1
348pipelined=true
349
350[system.cpu.fuPool.FUList5.opList04]
351type=OpDesc
352eventq_index=0
353opClass=SimdCvt
354opLat=1
355pipelined=true
356
357[system.cpu.fuPool.FUList5.opList05]
358type=OpDesc
359eventq_index=0
360opClass=SimdMisc
361opLat=1
362pipelined=true
363
364[system.cpu.fuPool.FUList5.opList06]
365type=OpDesc
366eventq_index=0
367opClass=SimdMult
368opLat=1
369pipelined=true
370
371[system.cpu.fuPool.FUList5.opList07]
372type=OpDesc
373eventq_index=0
374opClass=SimdMultAcc
375opLat=1
376pipelined=true
377
378[system.cpu.fuPool.FUList5.opList08]
379type=OpDesc
380eventq_index=0
381opClass=SimdShift
382opLat=1
383pipelined=true
384
385[system.cpu.fuPool.FUList5.opList09]
386type=OpDesc
387eventq_index=0
388opClass=SimdShiftAcc
389opLat=1
390pipelined=true
391
392[system.cpu.fuPool.FUList5.opList10]
393type=OpDesc
394eventq_index=0
395opClass=SimdSqrt
396opLat=1
397pipelined=true
398
399[system.cpu.fuPool.FUList5.opList11]
400type=OpDesc
401eventq_index=0
402opClass=SimdFloatAdd
403opLat=1
404pipelined=true
405
406[system.cpu.fuPool.FUList5.opList12]
407type=OpDesc
408eventq_index=0
409opClass=SimdFloatAlu
410opLat=1
411pipelined=true
412
413[system.cpu.fuPool.FUList5.opList13]
414type=OpDesc
415eventq_index=0
416opClass=SimdFloatCmp
417opLat=1
418pipelined=true
419
420[system.cpu.fuPool.FUList5.opList14]
421type=OpDesc
422eventq_index=0
423opClass=SimdFloatCvt
424opLat=1
425pipelined=true
426
427[system.cpu.fuPool.FUList5.opList15]
428type=OpDesc
429eventq_index=0
430opClass=SimdFloatDiv
431opLat=1
432pipelined=true
433
434[system.cpu.fuPool.FUList5.opList16]
435type=OpDesc
436eventq_index=0
437opClass=SimdFloatMisc
438opLat=1
439pipelined=true
440
441[system.cpu.fuPool.FUList5.opList17]
442type=OpDesc
443eventq_index=0
444opClass=SimdFloatMult
445opLat=1
446pipelined=true
447
448[system.cpu.fuPool.FUList5.opList18]
449type=OpDesc
450eventq_index=0
451opClass=SimdFloatMultAcc
452opLat=1
453pipelined=true
454
455[system.cpu.fuPool.FUList5.opList19]
456type=OpDesc
457eventq_index=0
458opClass=SimdFloatSqrt
459opLat=1
460pipelined=true
461
462[system.cpu.fuPool.FUList6]
463type=FUDesc
464children=opList
465count=0
466eventq_index=0
467opList=system.cpu.fuPool.FUList6.opList
468
469[system.cpu.fuPool.FUList6.opList]
470type=OpDesc
471eventq_index=0
472opClass=MemWrite
473opLat=1
474pipelined=true
475
476[system.cpu.fuPool.FUList7]
477type=FUDesc
478children=opList0 opList1
479count=4
480eventq_index=0
481opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
482
483[system.cpu.fuPool.FUList7.opList0]
484type=OpDesc
485eventq_index=0
486opClass=MemRead
487opLat=1
488pipelined=true
489
490[system.cpu.fuPool.FUList7.opList1]
491type=OpDesc
492eventq_index=0
493opClass=MemWrite
494opLat=1
495pipelined=true
496
497[system.cpu.fuPool.FUList8]
498type=FUDesc
499children=opList
500count=1
501eventq_index=0
502opList=system.cpu.fuPool.FUList8.opList
503
504[system.cpu.fuPool.FUList8.opList]
505type=OpDesc
506eventq_index=0
507opClass=IprAccess
508opLat=3
509pipelined=false
510
511[system.cpu.icache]
512type=Cache
513children=tags
514addr_ranges=0:18446744073709551615
515assoc=2
516clk_domain=system.cpu_clk_domain
517clusivity=mostly_incl
518demand_mshr_reserve=1
519eventq_index=0
520hit_latency=2
521is_read_only=true
522max_miss_count=0
523mshrs=4
524prefetch_on_access=false
525prefetcher=Null
526response_latency=2
527sequential_access=false
528size=131072
529system=system
530tags=system.cpu.icache.tags
531tgts_per_mshr=20
532write_buffers=8
533writeback_clean=true
534cpu_side=system.cpu.icache_port
535mem_side=system.cpu.toL2Bus.slave[0]
536
537[system.cpu.icache.tags]
538type=LRU
539assoc=2
540block_size=64
541clk_domain=system.cpu_clk_domain
542eventq_index=0
543hit_latency=2
544sequential_access=false
545size=131072
546
547[system.cpu.interrupts0]
548type=AlphaInterrupts
549eventq_index=0
550
551[system.cpu.interrupts1]
552type=AlphaInterrupts
553eventq_index=0
554
555[system.cpu.isa0]
556type=AlphaISA
557eventq_index=0
558system=system
559
560[system.cpu.isa1]
561type=AlphaISA
562eventq_index=0
563system=system
564
565[system.cpu.itb]
566type=AlphaTLB
567eventq_index=0
568size=48
569
570[system.cpu.l2cache]
571type=Cache
572children=tags
573addr_ranges=0:18446744073709551615
574assoc=8
575clk_domain=system.cpu_clk_domain
576clusivity=mostly_incl
577demand_mshr_reserve=1
578eventq_index=0
579hit_latency=20
580is_read_only=false
581max_miss_count=0
582mshrs=20
583prefetch_on_access=false
584prefetcher=Null
585response_latency=20
586sequential_access=false
587size=2097152
588system=system
589tags=system.cpu.l2cache.tags
590tgts_per_mshr=12
591write_buffers=8
592writeback_clean=false
593cpu_side=system.cpu.toL2Bus.master[0]
594mem_side=system.membus.slave[1]
595
596[system.cpu.l2cache.tags]
597type=LRU
598assoc=8
599block_size=64
600clk_domain=system.cpu_clk_domain
601eventq_index=0
602hit_latency=20
603sequential_access=false
604size=2097152
605
606[system.cpu.toL2Bus]
607type=CoherentXBar
608children=snoop_filter
609clk_domain=system.cpu_clk_domain
610eventq_index=0
611forward_latency=0
612frontend_latency=1
613point_of_coherency=false
614response_latency=1
615snoop_filter=system.cpu.toL2Bus.snoop_filter
616snoop_response_latency=1
617system=system
618use_default_range=false
619width=32
620master=system.cpu.l2cache.cpu_side
621slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
622
623[system.cpu.toL2Bus.snoop_filter]
624type=SnoopFilter
625eventq_index=0
626lookup_latency=0
627max_capacity=8388608
628system=system
629
630[system.cpu.tracer]
631type=ExeTracer
632eventq_index=0
633
634[system.cpu.workload0]
635type=LiveProcess
636cmd=hello
637cwd=
638drivers=
639egid=100
640env=
641errout=cerr
642euid=100
643eventq_index=0
644executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
645gid=100
646input=cin
647kvmInSE=false
648max_stack_size=67108864
649output=cout
650pid=100
651ppid=99
652simpoint=0
653system=system
654uid=100
655useArchPT=false
656
657[system.cpu.workload1]
658type=LiveProcess
659cmd=hello
660cwd=
661drivers=
662egid=100
663env=
664errout=cerr
665euid=100
666eventq_index=0
667executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
668gid=100
669input=cin
670kvmInSE=false
671max_stack_size=67108864
672output=cout
673pid=100
674ppid=99
675simpoint=0
676system=system
677uid=100
678useArchPT=false
679
680[system.cpu_clk_domain]
681type=SrcClockDomain
682clock=500
683domain_id=-1
684eventq_index=0
685init_perf_level=0
686voltage_domain=system.voltage_domain
687
688[system.dvfs_handler]
689type=DVFSHandler
690domains=
691enable=false
692eventq_index=0
693sys_clk_domain=system.clk_domain
694transition_latency=100000000
695
696[system.membus]
697type=CoherentXBar
698clk_domain=system.clk_domain
699eventq_index=0
700forward_latency=4
701frontend_latency=3
702point_of_coherency=true
703response_latency=2
704snoop_filter=Null
705snoop_response_latency=4
706system=system
707use_default_range=false
708width=16
709master=system.physmem.port
710slave=system.system_port system.cpu.l2cache.mem_side
711
712[system.physmem]
713type=DRAMCtrl
714IDD0=0.075000
715IDD02=0.000000
716IDD2N=0.050000
717IDD2N2=0.000000
718IDD2P0=0.000000
719IDD2P02=0.000000
720IDD2P1=0.000000
721IDD2P12=0.000000
722IDD3N=0.057000
723IDD3N2=0.000000
724IDD3P0=0.000000
725IDD3P02=0.000000
726IDD3P1=0.000000
727IDD3P12=0.000000
728IDD4R=0.187000
729IDD4R2=0.000000
730IDD4W=0.165000
731IDD4W2=0.000000
732IDD5=0.220000
733IDD52=0.000000
734IDD6=0.000000
735IDD62=0.000000
736VDD=1.500000
737VDD2=0.000000
738activation_limit=4
739addr_mapping=RoRaBaCoCh
740bank_groups_per_rank=0
741banks_per_rank=8
742burst_length=8
743channels=1
744clk_domain=system.clk_domain
745conf_table_reported=true
746device_bus_width=8
747device_rowbuffer_size=1024
748device_size=536870912
749devices_per_rank=8
750dll=true
751eventq_index=0
752in_addr_map=true
753max_accesses_per_row=16
754mem_sched_policy=frfcfs
755min_writes_per_switch=16
756null=false
757page_policy=open_adaptive
758range=0:134217727
759ranks_per_channel=2
760read_buffer_size=32
761static_backend_latency=10000
762static_frontend_latency=10000
763tBURST=5000
764tCCD_L=0
765tCK=1250
766tCL=13750
767tCS=2500
768tRAS=35000
769tRCD=13750
770tREFI=7800000
771tRFC=260000
772tRP=13750
773tRRD=6000
774tRRD_L=0
775tRTP=7500
776tRTW=2500
777tWR=15000
778tWTR=7500
779tXAW=30000
780tXP=0
781tXPDLL=0
782tXS=0
783tXSDLL=0
784write_buffer_size=64
785write_high_thresh_perc=85
786write_low_thresh_perc=50
787port=system.membus.master[0]
788
789[system.voltage_domain]
790type=VoltageDomain
791eventq_index=0
792voltage=1.000000
793