1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 159 unchanged lines hidden (view full) ---

168localHistoryTableSize=2048
169localPredictorSize=2048
170numThreads=2
171useIndirect=true
172
173[system.cpu.dcache]
174type=Cache
175children=tags
176addr_ranges=0:18446744073709551615
177assoc=2
178clk_domain=system.cpu_clk_domain
179clusivity=mostly_incl
180default_p_state=UNDEFINED
181demand_mshr_reserve=1
182eventq_index=0
183hit_latency=2
184is_read_only=false

--- 341 unchanged lines hidden (view full) ---

526eventq_index=0
527opClass=IprAccess
528opLat=3
529pipelined=false
530
531[system.cpu.icache]
532type=Cache
533children=tags
534addr_ranges=0:18446744073709551615
535assoc=2
536clk_domain=system.cpu_clk_domain
537clusivity=mostly_incl
538default_p_state=UNDEFINED
539demand_mshr_reserve=1
540eventq_index=0
541hit_latency=2
542is_read_only=true

--- 52 unchanged lines hidden (view full) ---

595[system.cpu.itb]
596type=AlphaTLB
597eventq_index=0
598size=48
599
600[system.cpu.l2cache]
601type=Cache
602children=tags
603addr_ranges=0:18446744073709551615
604assoc=8
605clk_domain=system.cpu_clk_domain
606clusivity=mostly_incl
607default_p_state=UNDEFINED
608demand_mshr_reserve=1
609eventq_index=0
610hit_latency=20
611is_read_only=false

--- 123 unchanged lines hidden (view full) ---

735domains=
736enable=false
737eventq_index=0
738sys_clk_domain=system.clk_domain
739transition_latency=100000000
740
741[system.membus]
742type=CoherentXBar
743clk_domain=system.clk_domain
744default_p_state=UNDEFINED
745eventq_index=0
746forward_latency=4
747frontend_latency=3
748p_state_clk_gate_bins=20
749p_state_clk_gate_max=1000000000000
750p_state_clk_gate_min=1000
751point_of_coherency=true
752power_model=Null
753response_latency=2
754snoop_filter=Null
755snoop_response_latency=4
756system=system
757use_default_range=false
758width=16
759master=system.physmem.port
760slave=system.system_port system.cpu.l2cache.mem_side
761
762[system.physmem]
763type=DRAMCtrl
764IDD0=0.075000
765IDD02=0.000000
766IDD2N=0.050000
767IDD2N2=0.000000
768IDD2P0=0.000000
769IDD2P02=0.000000
770IDD2P1=0.000000
771IDD2P12=0.000000
772IDD3N=0.057000
773IDD3N2=0.000000
774IDD3P0=0.000000
775IDD3P02=0.000000
776IDD3P1=0.000000
777IDD3P12=0.000000
778IDD4R=0.187000
779IDD4R2=0.000000
780IDD4W=0.165000
781IDD4W2=0.000000
782IDD5=0.220000
783IDD52=0.000000
784IDD6=0.000000
785IDD62=0.000000
786VDD=1.500000
787VDD2=0.000000
788activation_limit=4
789addr_mapping=RoRaBaCoCh
790bank_groups_per_rank=0
791banks_per_rank=8
792burst_length=8
793channels=1
794clk_domain=system.clk_domain
795conf_table_reported=true
796default_p_state=UNDEFINED
797device_bus_width=8
798device_rowbuffer_size=1024
799device_size=536870912
800devices_per_rank=8
801dll=true
802eventq_index=0
803in_addr_map=true
804max_accesses_per_row=16
805mem_sched_policy=frfcfs
806min_writes_per_switch=16
807null=false
808p_state_clk_gate_bins=20
809p_state_clk_gate_max=1000000000000
810p_state_clk_gate_min=1000
811page_policy=open_adaptive
812power_model=Null
813range=0:134217727
814ranks_per_channel=2
815read_buffer_size=32
816static_backend_latency=10000
817static_frontend_latency=10000
818tBURST=5000
819tCCD_L=0
820tCK=1250
821tCL=13750

--- 5 unchanged lines hidden (view full) ---

827tRP=13750
828tRRD=6000
829tRRD_L=0
830tRTP=7500
831tRTW=2500
832tWR=15000
833tWTR=7500
834tXAW=30000
835tXP=0
836tXPDLL=0
837tXS=0
838tXSDLL=0
839write_buffer_size=64
840write_high_thresh_perc=85
841write_low_thresh_perc=50
842port=system.membus.master[0]
843
844[system.voltage_domain]
845type=VoltageDomain
846eventq_index=0
847voltage=1.000000
848