1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=System
13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17eventq_index=0
18exit_on_work_items=false
19init_param=0
20kernel=
21kernel_addr_check=true
22load_addr_mask=1099511627775
23load_offset=0
24mem_mode=timing
25mem_ranges=
26memories=system.physmem
27mmap_using_noreserve=false
28multi_thread=true
29num_work_ids=16
30readfile=
31symbolfile=
32thermal_components=
33thermal_model=Null
34work_begin_ckpt_count=0
35work_begin_cpu_id_exit=-1
36work_begin_exit_count=0
37work_cpus_ckpt_count=0
--- 29 unchanged lines hidden (view full) ---
67commitToFetchDelay=1
68commitToIEWDelay=1
69commitToRenameDelay=1
70commitWidth=8
71cpu_id=0
72decodeToFetchDelay=1
73decodeToRenameDelay=1
74decodeWidth=8
75dispatchWidth=8
76do_checkpoint_insts=true
77do_quiesce=true
78do_statistics_insts=true
79dtb=system.cpu.dtb
80eventq_index=0
81fetchBufferSize=64
82fetchQueueSize=32
--- 20 unchanged lines hidden (view full) ---
103needsTSO=false
104numIQEntries=64
105numPhysCCRegs=0
106numPhysFloatRegs=256
107numPhysIntRegs=256
108numROBEntries=192
109numRobs=1
110numThreads=2
111profile=0
112progress_interval=0
113renameToDecodeDelay=1
114renameToFetchDelay=1
115renameToIEWDelay=2
116renameToROBDelay=1
117renameWidth=8
118simpoint_start_insts=
--- 43 unchanged lines hidden (view full) ---
162
163[system.cpu.dcache]
164type=Cache
165children=tags
166addr_ranges=0:18446744073709551615
167assoc=2
168clk_domain=system.cpu_clk_domain
169clusivity=mostly_incl
170demand_mshr_reserve=1
171eventq_index=0
172hit_latency=2
173is_read_only=false
174max_miss_count=0
175mshrs=4
176prefetch_on_access=false
177prefetcher=Null
178response_latency=2
179sequential_access=false
180size=262144
181system=system
182tags=system.cpu.dcache.tags
183tgts_per_mshr=20
184write_buffers=8
185writeback_clean=false
186cpu_side=system.cpu.dcache_port
187mem_side=system.cpu.toL2Bus.slave[1]
188
189[system.cpu.dcache.tags]
190type=LRU
191assoc=2
192block_size=64
193clk_domain=system.cpu_clk_domain
194eventq_index=0
195hit_latency=2
196sequential_access=false
197size=262144
198
199[system.cpu.dtb]
200type=AlphaTLB
201eventq_index=0
202size=64
203
--- 306 unchanged lines hidden (view full) ---
510
511[system.cpu.icache]
512type=Cache
513children=tags
514addr_ranges=0:18446744073709551615
515assoc=2
516clk_domain=system.cpu_clk_domain
517clusivity=mostly_incl
518demand_mshr_reserve=1
519eventq_index=0
520hit_latency=2
521is_read_only=true
522max_miss_count=0
523mshrs=4
524prefetch_on_access=false
525prefetcher=Null
526response_latency=2
527sequential_access=false
528size=131072
529system=system
530tags=system.cpu.icache.tags
531tgts_per_mshr=20
532write_buffers=8
533writeback_clean=true
534cpu_side=system.cpu.icache_port
535mem_side=system.cpu.toL2Bus.slave[0]
536
537[system.cpu.icache.tags]
538type=LRU
539assoc=2
540block_size=64
541clk_domain=system.cpu_clk_domain
542eventq_index=0
543hit_latency=2
544sequential_access=false
545size=131072
546
547[system.cpu.interrupts0]
548type=AlphaInterrupts
549eventq_index=0
550
551[system.cpu.interrupts1]
--- 17 unchanged lines hidden (view full) ---
569
570[system.cpu.l2cache]
571type=Cache
572children=tags
573addr_ranges=0:18446744073709551615
574assoc=8
575clk_domain=system.cpu_clk_domain
576clusivity=mostly_incl
577demand_mshr_reserve=1
578eventq_index=0
579hit_latency=20
580is_read_only=false
581max_miss_count=0
582mshrs=20
583prefetch_on_access=false
584prefetcher=Null
585response_latency=20
586sequential_access=false
587size=2097152
588system=system
589tags=system.cpu.l2cache.tags
590tgts_per_mshr=12
591write_buffers=8
592writeback_clean=false
593cpu_side=system.cpu.toL2Bus.master[0]
594mem_side=system.membus.slave[1]
595
596[system.cpu.l2cache.tags]
597type=LRU
598assoc=8
599block_size=64
600clk_domain=system.cpu_clk_domain
601eventq_index=0
602hit_latency=20
603sequential_access=false
604size=2097152
605
606[system.cpu.toL2Bus]
607type=CoherentXBar
608children=snoop_filter
609clk_domain=system.cpu_clk_domain
610eventq_index=0
611forward_latency=0
612frontend_latency=1
613point_of_coherency=false
614response_latency=1
615snoop_filter=system.cpu.toL2Bus.snoop_filter
616snoop_response_latency=1
617system=system
618use_default_range=false
619width=32
620master=system.cpu.l2cache.cpu_side
621slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
--- 14 unchanged lines hidden (view full) ---
636cmd=hello
637cwd=
638drivers=
639egid=100
640env=
641errout=cerr
642euid=100
643eventq_index=0
644executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
645gid=100
646input=cin
647kvmInSE=false
648max_stack_size=67108864
649output=cout
650pid=100
651ppid=99
652simpoint=0
--- 6 unchanged lines hidden (view full) ---
659cmd=hello
660cwd=
661drivers=
662egid=100
663env=
664errout=cerr
665euid=100
666eventq_index=0
667executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
668gid=100
669input=cin
670kvmInSE=false
671max_stack_size=67108864
672output=cout
673pid=100
674ppid=99
675simpoint=0
--- 15 unchanged lines hidden (view full) ---
691enable=false
692eventq_index=0
693sys_clk_domain=system.clk_domain
694transition_latency=100000000
695
696[system.membus]
697type=CoherentXBar
698clk_domain=system.clk_domain
699eventq_index=0
700forward_latency=4
701frontend_latency=3
702point_of_coherency=true
703response_latency=2
704snoop_filter=Null
705snoop_response_latency=4
706system=system
707use_default_range=false
708width=16
709master=system.physmem.port
710slave=system.system_port system.cpu.l2cache.mem_side
--- 27 unchanged lines hidden (view full) ---
738activation_limit=4
739addr_mapping=RoRaBaCoCh
740bank_groups_per_rank=0
741banks_per_rank=8
742burst_length=8
743channels=1
744clk_domain=system.clk_domain
745conf_table_reported=true
746device_bus_width=8
747device_rowbuffer_size=1024
748device_size=536870912
749devices_per_rank=8
750dll=true
751eventq_index=0
752in_addr_map=true
753max_accesses_per_row=16
754mem_sched_policy=frfcfs
755min_writes_per_switch=16
756null=false
757page_policy=open_adaptive
758range=0:134217727
759ranks_per_channel=2
760read_buffer_size=32
761static_backend_latency=10000
762static_frontend_latency=10000
763tBURST=5000
764tCCD_L=0
765tCK=1250
--- 28 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=System
13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17eventq_index=0
18exit_on_work_items=false
19init_param=0
20kernel=
21kernel_addr_check=true
22load_addr_mask=1099511627775
23load_offset=0
24mem_mode=timing
25mem_ranges=
26memories=system.physmem
27mmap_using_noreserve=false
28multi_thread=true
29num_work_ids=16
30readfile=
31symbolfile=
32thermal_components=
33thermal_model=Null
34work_begin_ckpt_count=0
35work_begin_cpu_id_exit=-1
36work_begin_exit_count=0
37work_cpus_ckpt_count=0
--- 29 unchanged lines hidden (view full) ---
67commitToFetchDelay=1
68commitToIEWDelay=1
69commitToRenameDelay=1
70commitWidth=8
71cpu_id=0
72decodeToFetchDelay=1
73decodeToRenameDelay=1
74decodeWidth=8
75dispatchWidth=8
76do_checkpoint_insts=true
77do_quiesce=true
78do_statistics_insts=true
79dtb=system.cpu.dtb
80eventq_index=0
81fetchBufferSize=64
82fetchQueueSize=32
--- 20 unchanged lines hidden (view full) ---
103needsTSO=false
104numIQEntries=64
105numPhysCCRegs=0
106numPhysFloatRegs=256
107numPhysIntRegs=256
108numROBEntries=192
109numRobs=1
110numThreads=2
111profile=0
112progress_interval=0
113renameToDecodeDelay=1
114renameToFetchDelay=1
115renameToIEWDelay=2
116renameToROBDelay=1
117renameWidth=8
118simpoint_start_insts=
--- 43 unchanged lines hidden (view full) ---
162
163[system.cpu.dcache]
164type=Cache
165children=tags
166addr_ranges=0:18446744073709551615
167assoc=2
168clk_domain=system.cpu_clk_domain
169clusivity=mostly_incl
170demand_mshr_reserve=1
171eventq_index=0
172hit_latency=2
173is_read_only=false
174max_miss_count=0
175mshrs=4
176prefetch_on_access=false
177prefetcher=Null
178response_latency=2
179sequential_access=false
180size=262144
181system=system
182tags=system.cpu.dcache.tags
183tgts_per_mshr=20
184write_buffers=8
185writeback_clean=false
186cpu_side=system.cpu.dcache_port
187mem_side=system.cpu.toL2Bus.slave[1]
188
189[system.cpu.dcache.tags]
190type=LRU
191assoc=2
192block_size=64
193clk_domain=system.cpu_clk_domain
194eventq_index=0
195hit_latency=2
196sequential_access=false
197size=262144
198
199[system.cpu.dtb]
200type=AlphaTLB
201eventq_index=0
202size=64
203
--- 306 unchanged lines hidden (view full) ---
510
511[system.cpu.icache]
512type=Cache
513children=tags
514addr_ranges=0:18446744073709551615
515assoc=2
516clk_domain=system.cpu_clk_domain
517clusivity=mostly_incl
518demand_mshr_reserve=1
519eventq_index=0
520hit_latency=2
521is_read_only=true
522max_miss_count=0
523mshrs=4
524prefetch_on_access=false
525prefetcher=Null
526response_latency=2
527sequential_access=false
528size=131072
529system=system
530tags=system.cpu.icache.tags
531tgts_per_mshr=20
532write_buffers=8
533writeback_clean=true
534cpu_side=system.cpu.icache_port
535mem_side=system.cpu.toL2Bus.slave[0]
536
537[system.cpu.icache.tags]
538type=LRU
539assoc=2
540block_size=64
541clk_domain=system.cpu_clk_domain
542eventq_index=0
543hit_latency=2
544sequential_access=false
545size=131072
546
547[system.cpu.interrupts0]
548type=AlphaInterrupts
549eventq_index=0
550
551[system.cpu.interrupts1]
--- 17 unchanged lines hidden (view full) ---
569
570[system.cpu.l2cache]
571type=Cache
572children=tags
573addr_ranges=0:18446744073709551615
574assoc=8
575clk_domain=system.cpu_clk_domain
576clusivity=mostly_incl
577demand_mshr_reserve=1
578eventq_index=0
579hit_latency=20
580is_read_only=false
581max_miss_count=0
582mshrs=20
583prefetch_on_access=false
584prefetcher=Null
585response_latency=20
586sequential_access=false
587size=2097152
588system=system
589tags=system.cpu.l2cache.tags
590tgts_per_mshr=12
591write_buffers=8
592writeback_clean=false
593cpu_side=system.cpu.toL2Bus.master[0]
594mem_side=system.membus.slave[1]
595
596[system.cpu.l2cache.tags]
597type=LRU
598assoc=8
599block_size=64
600clk_domain=system.cpu_clk_domain
601eventq_index=0
602hit_latency=20
603sequential_access=false
604size=2097152
605
606[system.cpu.toL2Bus]
607type=CoherentXBar
608children=snoop_filter
609clk_domain=system.cpu_clk_domain
610eventq_index=0
611forward_latency=0
612frontend_latency=1
613point_of_coherency=false
614response_latency=1
615snoop_filter=system.cpu.toL2Bus.snoop_filter
616snoop_response_latency=1
617system=system
618use_default_range=false
619width=32
620master=system.cpu.l2cache.cpu_side
621slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
--- 14 unchanged lines hidden (view full) ---
636cmd=hello
637cwd=
638drivers=
639egid=100
640env=
641errout=cerr
642euid=100
643eventq_index=0
644executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
645gid=100
646input=cin
647kvmInSE=false
648max_stack_size=67108864
649output=cout
650pid=100
651ppid=99
652simpoint=0
--- 6 unchanged lines hidden (view full) ---
659cmd=hello
660cwd=
661drivers=
662egid=100
663env=
664errout=cerr
665euid=100
666eventq_index=0
667executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/alpha/linux/hello
668gid=100
669input=cin
670kvmInSE=false
671max_stack_size=67108864
672output=cout
673pid=100
674ppid=99
675simpoint=0
--- 15 unchanged lines hidden (view full) ---
691enable=false
692eventq_index=0
693sys_clk_domain=system.clk_domain
694transition_latency=100000000
695
696[system.membus]
697type=CoherentXBar
698clk_domain=system.clk_domain
699eventq_index=0
700forward_latency=4
701frontend_latency=3
702point_of_coherency=true
703response_latency=2
704snoop_filter=Null
705snoop_response_latency=4
706system=system
707use_default_range=false
708width=16
709master=system.physmem.port
710slave=system.system_port system.cpu.l2cache.mem_side
--- 27 unchanged lines hidden (view full) ---
738activation_limit=4
739addr_mapping=RoRaBaCoCh
740bank_groups_per_rank=0
741banks_per_rank=8
742burst_length=8
743channels=1
744clk_domain=system.clk_domain
745conf_table_reported=true
746device_bus_width=8
747device_rowbuffer_size=1024
748device_size=536870912
749devices_per_rank=8
750dll=true
751eventq_index=0
752in_addr_map=true
753max_accesses_per_row=16
754mem_sched_policy=frfcfs
755min_writes_per_switch=16
756null=false
757page_policy=open_adaptive
758range=0:134217727
759ranks_per_channel=2
760read_buffer_size=32
761static_backend_latency=10000
762static_frontend_latency=10000
763tBURST=5000
764tCCD_L=0
765tCK=1250
--- 28 unchanged lines hidden ---