1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 159 unchanged lines hidden (view full) ---

168localHistoryTableSize=2048
169localPredictorSize=2048
170numThreads=2
171useIndirect=true
172
173[system.cpu.dcache]
174type=Cache
175children=tags
176addr_ranges=0:18446744073709551615:0:0:0:0
177assoc=2
178clk_domain=system.cpu_clk_domain
179clusivity=mostly_incl
180default_p_state=UNDEFINED
181demand_mshr_reserve=1
182eventq_index=0
183hit_latency=2
184is_read_only=false

--- 341 unchanged lines hidden (view full) ---

526eventq_index=0
527opClass=IprAccess
528opLat=3
529pipelined=false
530
531[system.cpu.icache]
532type=Cache
533children=tags
534addr_ranges=0:18446744073709551615:0:0:0:0
535assoc=2
536clk_domain=system.cpu_clk_domain
537clusivity=mostly_incl
538default_p_state=UNDEFINED
539demand_mshr_reserve=1
540eventq_index=0
541hit_latency=2
542is_read_only=true

--- 52 unchanged lines hidden (view full) ---

595[system.cpu.itb]
596type=AlphaTLB
597eventq_index=0
598size=48
599
600[system.cpu.l2cache]
601type=Cache
602children=tags
603addr_ranges=0:18446744073709551615:0:0:0:0
604assoc=8
605clk_domain=system.cpu_clk_domain
606clusivity=mostly_incl
607default_p_state=UNDEFINED
608demand_mshr_reserve=1
609eventq_index=0
610hit_latency=20
611is_read_only=false

--- 123 unchanged lines hidden (view full) ---

735domains=
736enable=false
737eventq_index=0
738sys_clk_domain=system.clk_domain
739transition_latency=100000000
740
741[system.membus]
742type=CoherentXBar
743children=snoop_filter
744clk_domain=system.clk_domain
745default_p_state=UNDEFINED
746eventq_index=0
747forward_latency=4
748frontend_latency=3
749p_state_clk_gate_bins=20
750p_state_clk_gate_max=1000000000000
751p_state_clk_gate_min=1000
752point_of_coherency=true
753power_model=Null
754response_latency=2
755snoop_filter=system.membus.snoop_filter
756snoop_response_latency=4
757system=system
758use_default_range=false
759width=16
760master=system.physmem.port
761slave=system.system_port system.cpu.l2cache.mem_side
762
763[system.membus.snoop_filter]
764type=SnoopFilter
765eventq_index=0
766lookup_latency=1
767max_capacity=8388608
768system=system
769
770[system.physmem]
771type=DRAMCtrl
772IDD0=0.055000
773IDD02=0.000000
774IDD2N=0.032000
775IDD2N2=0.000000
776IDD2P0=0.000000
777IDD2P02=0.000000
778IDD2P1=0.032000
779IDD2P12=0.000000
780IDD3N=0.038000
781IDD3N2=0.000000
782IDD3P0=0.000000
783IDD3P02=0.000000
784IDD3P1=0.038000
785IDD3P12=0.000000
786IDD4R=0.157000
787IDD4R2=0.000000
788IDD4W=0.125000
789IDD4W2=0.000000
790IDD5=0.235000
791IDD52=0.000000
792IDD6=0.020000
793IDD62=0.000000
794VDD=1.500000
795VDD2=0.000000
796activation_limit=4
797addr_mapping=RoRaBaCoCh
798bank_groups_per_rank=0
799banks_per_rank=8
800burst_length=8
801channels=1
802clk_domain=system.clk_domain
803conf_table_reported=true
804default_p_state=UNDEFINED
805device_bus_width=8
806device_rowbuffer_size=1024
807device_size=536870912
808devices_per_rank=8
809dll=true
810eventq_index=0
811in_addr_map=true
812kvm_map=true
813max_accesses_per_row=16
814mem_sched_policy=frfcfs
815min_writes_per_switch=16
816null=false
817p_state_clk_gate_bins=20
818p_state_clk_gate_max=1000000000000
819p_state_clk_gate_min=1000
820page_policy=open_adaptive
821power_model=Null
822range=0:134217727:0:0:0:0
823ranks_per_channel=2
824read_buffer_size=32
825static_backend_latency=10000
826static_frontend_latency=10000
827tBURST=5000
828tCCD_L=0
829tCK=1250
830tCL=13750

--- 5 unchanged lines hidden (view full) ---

836tRP=13750
837tRRD=6000
838tRRD_L=0
839tRTP=7500
840tRTW=2500
841tWR=15000
842tWTR=7500
843tXAW=30000
844tXP=6000
845tXPDLL=0
846tXS=270000
847tXSDLL=0
848write_buffer_size=64
849write_high_thresh_perc=85
850write_low_thresh_perc=50
851port=system.membus.master[0]
852
853[system.voltage_domain]
854type=VoltageDomain
855eventq_index=0
856voltage=1.000000
857