| config.ini (9276:a5ede748a1d9) | config.ini (9348:44d31345e360) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a |
| 13clock=1 | 13clock=1000 |
| 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU | 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU |
| 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload | 33children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload |
| 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 --- 32 unchanged lines hidden (view full) --- 74globalHistoryBits=13 75globalPredictorSize=8192 76iewToCommitDelay=1 77iewToDecodeDelay=1 78iewToFetchDelay=1 79iewToRenameDelay=1 80instShiftAmt=2 81interrupts=system.cpu.interrupts | 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 --- 32 unchanged lines hidden (view full) --- 74globalHistoryBits=13 75globalPredictorSize=8192 76iewToCommitDelay=1 77iewToDecodeDelay=1 78iewToFetchDelay=1 79iewToRenameDelay=1 80instShiftAmt=2 81interrupts=system.cpu.interrupts |
| 82isa=system.cpu.isa |
|
| 82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 --- 35 unchanged lines hidden (view full) --- 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_ranges=0:18446744073709551615 131assoc=2 132block_size=64 | 83issueToExecuteDelay=1 84issueWidth=8 85itb=system.cpu.itb 86localCtrBits=2 87localHistoryBits=11 88localHistoryTableSize=2048 89localPredictorSize=2048 90max_insts_all_threads=0 --- 35 unchanged lines hidden (view full) --- 126dcache_port=system.cpu.dcache.cpu_side 127icache_port=system.cpu.icache.cpu_side 128 129[system.cpu.dcache] 130type=BaseCache 131addr_ranges=0:18446744073709551615 132assoc=2 133block_size=64 |
| 133clock=1 | 134clock=500 |
| 134forward_snoops=true 135hash_delay=1 | 135forward_snoops=true 136hash_delay=1 |
| 136hit_latency=1000 | 137hit_latency=2 |
| 137is_top_level=true 138max_miss_count=0 | 138is_top_level=true 139max_miss_count=0 |
| 139mshrs=10 | 140mshrs=4 |
| 140prefetch_on_access=false 141prefetcher=Null 142prioritizeRequests=false 143repl=Null | 141prefetch_on_access=false 142prefetcher=Null 143prioritizeRequests=false 144repl=Null |
| 144response_latency=1000 | 145response_latency=2 |
| 145size=262144 146subblock_size=0 147system=system 148tgts_per_mshr=20 149trace_addr=0 150two_queue=false 151write_buffers=8 152cpu_side=system.cpu.dcache_port --- 266 unchanged lines hidden (view full) --- 419opClass=IprAccess 420opLat=3 421 422[system.cpu.icache] 423type=BaseCache 424addr_ranges=0:18446744073709551615 425assoc=2 426block_size=64 | 146size=262144 147subblock_size=0 148system=system 149tgts_per_mshr=20 150trace_addr=0 151two_queue=false 152write_buffers=8 153cpu_side=system.cpu.dcache_port --- 266 unchanged lines hidden (view full) --- 420opClass=IprAccess 421opLat=3 422 423[system.cpu.icache] 424type=BaseCache 425addr_ranges=0:18446744073709551615 426assoc=2 427block_size=64 |
| 427clock=1 | 428clock=500 |
| 428forward_snoops=true 429hash_delay=1 | 429forward_snoops=true 430hash_delay=1 |
| 430hit_latency=1000 | 431hit_latency=2 |
| 431is_top_level=true 432max_miss_count=0 | 432is_top_level=true 433max_miss_count=0 |
| 433mshrs=10 | 434mshrs=4 |
| 434prefetch_on_access=false 435prefetcher=Null 436prioritizeRequests=false 437repl=Null | 435prefetch_on_access=false 436prefetcher=Null 437prioritizeRequests=false 438repl=Null |
| 438response_latency=1000 | 439response_latency=2 |
| 439size=131072 440subblock_size=0 441system=system 442tgts_per_mshr=20 443trace_addr=0 444two_queue=false 445write_buffers=8 446cpu_side=system.cpu.icache_port 447mem_side=system.cpu.toL2Bus.slave[0] 448 449[system.cpu.interrupts] 450type=PowerInterrupts 451 | 440size=131072 441subblock_size=0 442system=system 443tgts_per_mshr=20 444trace_addr=0 445two_queue=false 446write_buffers=8 447cpu_side=system.cpu.icache_port 448mem_side=system.cpu.toL2Bus.slave[0] 449 450[system.cpu.interrupts] 451type=PowerInterrupts 452 |
| 453[system.cpu.isa] 454type=PowerISA 455 |
|
| 452[system.cpu.itb] 453type=PowerTLB 454size=64 455 456[system.cpu.l2cache] 457type=BaseCache 458addr_ranges=0:18446744073709551615 | 456[system.cpu.itb] 457type=PowerTLB 458size=64 459 460[system.cpu.l2cache] 461type=BaseCache 462addr_ranges=0:18446744073709551615 |
| 459assoc=2 | 463assoc=8 |
| 460block_size=64 | 464block_size=64 |
| 461clock=1 | 465clock=500 |
| 462forward_snoops=true 463hash_delay=1 | 466forward_snoops=true 467hash_delay=1 |
| 464hit_latency=1000 | 468hit_latency=20 |
| 465is_top_level=false 466max_miss_count=0 | 469is_top_level=false 470max_miss_count=0 |
| 467mshrs=10 | 471mshrs=20 |
| 468prefetch_on_access=false 469prefetcher=Null 470prioritizeRequests=false 471repl=Null | 472prefetch_on_access=false 473prefetcher=Null 474prioritizeRequests=false 475repl=Null |
| 472response_latency=1000 | 476response_latency=20 |
| 473size=2097152 474subblock_size=0 475system=system | 477size=2097152 478subblock_size=0 479system=system |
| 476tgts_per_mshr=5 | 480tgts_per_mshr=12 |
| 477trace_addr=0 478two_queue=false 479write_buffers=8 480cpu_side=system.cpu.toL2Bus.master[0] 481mem_side=system.membus.slave[1] 482 483[system.cpu.toL2Bus] 484type=CoherentBus 485block_size=64 | 481trace_addr=0 482two_queue=false 483write_buffers=8 484cpu_side=system.cpu.toL2Bus.master[0] 485mem_side=system.membus.slave[1] 486 487[system.cpu.toL2Bus] 488type=CoherentBus 489block_size=64 |
| 486clock=1000 | 490clock=500 |
| 487header_cycles=1 488use_default_range=false | 491header_cycles=1 492use_default_range=false |
| 489width=8 | 493width=32 |
| 490master=system.cpu.l2cache.cpu_side 491slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 492 493[system.cpu.tracer] 494type=ExeTracer 495 496[system.cpu.workload] 497type=LiveProcess 498cmd=hello 499cwd= 500egid=100 501env= 502errout=cerr 503euid=100 | 494master=system.cpu.l2cache.cpu_side 495slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 496 497[system.cpu.tracer] 498type=ExeTracer 499 500[system.cpu.workload] 501type=LiveProcess 502cmd=hello 503cwd= 504egid=100 505env= 506errout=cerr 507euid=100 |
| 504executable=tests/test-progs/hello/bin/power/linux/hello | 508executable=/projects/pd/randd/dist/test-progs/hello/bin/power/linux/hello |
| 505gid=100 506input=cin 507max_stack_size=67108864 508output=cout 509pid=100 510ppid=99 511simpoint=0 512system=system --- 5 unchanged lines hidden (view full) --- 518clock=1000 519header_cycles=1 520use_default_range=false 521width=8 522master=system.physmem.port 523slave=system.system_port system.cpu.l2cache.mem_side 524 525[system.physmem] | 509gid=100 510input=cin 511max_stack_size=67108864 512output=cout 513pid=100 514ppid=99 515simpoint=0 516system=system --- 5 unchanged lines hidden (view full) --- 522clock=1000 523header_cycles=1 524use_default_range=false 525width=8 526master=system.physmem.port 527slave=system.system_port system.cpu.l2cache.mem_side 528 529[system.physmem] |
| 526type=SimpleMemory 527bandwidth=73.000000 528clock=1 | 530type=SimpleDRAM 531addr_mapping=openmap 532banks_per_rank=8 533clock=1000 |
| 529conf_table_reported=false 530in_addr_map=true | 534conf_table_reported=false 535in_addr_map=true |
| 531latency=30000 532latency_var=0 | 536lines_per_rowbuffer=64 537mem_sched_policy=fcfs |
| 533null=false | 538null=false |
| 539page_policy=open |
|
| 534range=0:134217727 | 540range=0:134217727 |
| 541ranks_per_channel=2 542read_buffer_size=32 543tBURST=4000 544tCL=14000 545tRCD=14000 546tREFI=7800000 547tRFC=300000 548tRP=14000 549tWTR=1000 550write_buffer_size=32 551write_thresh_perc=70 |
|
| 535zero=false 536port=system.membus.master[0] 537 | 552zero=false 553port=system.membus.master[0] 554 |