| config.ini (9150:a2370fa5c793) | config.ini (9276:a5ede748a1d9) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a |
| 13clock=1 |
|
| 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16 19readfile= 20symbolfile= --- 70 unchanged lines hidden (view full) --- 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 | 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= --- 70 unchanged lines hidden (view full) --- 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 |
| 99phase=0 | |
| 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 --- 17 unchanged lines hidden (view full) --- 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_ranges=0:18446744073709551615 131assoc=2 132block_size=64 | 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 --- 17 unchanged lines hidden (view full) --- 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_ranges=0:18446744073709551615 131assoc=2 132block_size=64 |
| 133clock=1 |
|
| 133forward_snoops=true 134hash_delay=1 | 134forward_snoops=true 135hash_delay=1 |
| 136hit_latency=1000 |
|
| 135is_top_level=true | 137is_top_level=true |
| 136latency=1000 | |
| 137max_miss_count=0 138mshrs=10 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null | 138max_miss_count=0 139mshrs=10 140prefetch_on_access=false 141prefetcher=Null 142prioritizeRequests=false 143repl=Null |
| 144response_latency=1000 |
|
| 143size=262144 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu.dcache_port --- 266 unchanged lines hidden (view full) --- 417opClass=IprAccess 418opLat=3 419 420[system.cpu.icache] 421type=BaseCache 422addr_ranges=0:18446744073709551615 423assoc=2 424block_size=64 | 145size=262144 146subblock_size=0 147system=system 148tgts_per_mshr=20 149trace_addr=0 150two_queue=false 151write_buffers=8 152cpu_side=system.cpu.dcache_port --- 266 unchanged lines hidden (view full) --- 419opClass=IprAccess 420opLat=3 421 422[system.cpu.icache] 423type=BaseCache 424addr_ranges=0:18446744073709551615 425assoc=2 426block_size=64 |
| 427clock=1 |
|
| 425forward_snoops=true 426hash_delay=1 | 428forward_snoops=true 429hash_delay=1 |
| 430hit_latency=1000 |
|
| 427is_top_level=true | 431is_top_level=true |
| 428latency=1000 | |
| 429max_miss_count=0 430mshrs=10 431prefetch_on_access=false 432prefetcher=Null 433prioritizeRequests=false 434repl=Null | 432max_miss_count=0 433mshrs=10 434prefetch_on_access=false 435prefetcher=Null 436prioritizeRequests=false 437repl=Null |
| 438response_latency=1000 |
|
| 435size=131072 436subblock_size=0 437system=system 438tgts_per_mshr=20 439trace_addr=0 440two_queue=false 441write_buffers=8 442cpu_side=system.cpu.icache_port --- 6 unchanged lines hidden (view full) --- 449type=PowerTLB 450size=64 451 452[system.cpu.l2cache] 453type=BaseCache 454addr_ranges=0:18446744073709551615 455assoc=2 456block_size=64 | 439size=131072 440subblock_size=0 441system=system 442tgts_per_mshr=20 443trace_addr=0 444two_queue=false 445write_buffers=8 446cpu_side=system.cpu.icache_port --- 6 unchanged lines hidden (view full) --- 453type=PowerTLB 454size=64 455 456[system.cpu.l2cache] 457type=BaseCache 458addr_ranges=0:18446744073709551615 459assoc=2 460block_size=64 |
| 461clock=1 |
|
| 457forward_snoops=true 458hash_delay=1 | 462forward_snoops=true 463hash_delay=1 |
| 464hit_latency=1000 |
|
| 459is_top_level=false | 465is_top_level=false |
| 460latency=1000 | |
| 461max_miss_count=0 462mshrs=10 463prefetch_on_access=false 464prefetcher=Null 465prioritizeRequests=false 466repl=Null | 466max_miss_count=0 467mshrs=10 468prefetch_on_access=false 469prefetcher=Null 470prioritizeRequests=false 471repl=Null |
| 472response_latency=1000 |
|
| 467size=2097152 468subblock_size=0 469system=system 470tgts_per_mshr=5 471trace_addr=0 472two_queue=false 473write_buffers=8 474cpu_side=system.cpu.toL2Bus.master[0] --- 15 unchanged lines hidden (view full) --- 490[system.cpu.workload] 491type=LiveProcess 492cmd=hello 493cwd= 494egid=100 495env= 496errout=cerr 497euid=100 | 473size=2097152 474subblock_size=0 475system=system 476tgts_per_mshr=5 477trace_addr=0 478two_queue=false 479write_buffers=8 480cpu_side=system.cpu.toL2Bus.master[0] --- 15 unchanged lines hidden (view full) --- 496[system.cpu.workload] 497type=LiveProcess 498cmd=hello 499cwd= 500egid=100 501env= 502errout=cerr 503euid=100 |
| 498executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello | 504executable=tests/test-progs/hello/bin/power/linux/hello |
| 499gid=100 500input=cin 501max_stack_size=67108864 502output=cout 503pid=100 504ppid=99 505simpoint=0 506system=system --- 6 unchanged lines hidden (view full) --- 513header_cycles=1 514use_default_range=false 515width=8 516master=system.physmem.port 517slave=system.system_port system.cpu.l2cache.mem_side 518 519[system.physmem] 520type=SimpleMemory | 505gid=100 506input=cin 507max_stack_size=67108864 508output=cout 509pid=100 510ppid=99 511simpoint=0 512system=system --- 6 unchanged lines hidden (view full) --- 519header_cycles=1 520use_default_range=false 521width=8 522master=system.physmem.port 523slave=system.system_port system.cpu.l2cache.mem_side 524 525[system.physmem] 526type=SimpleMemory |
| 527bandwidth=73.000000 528clock=1 |
|
| 521conf_table_reported=false | 529conf_table_reported=false |
| 522file= | |
| 523in_addr_map=true 524latency=30000 525latency_var=0 526null=false 527range=0:134217727 528zero=false 529port=system.membus.master[0] 530 | 530in_addr_map=true 531latency=30000 532latency_var=0 533null=false 534range=0:134217727 535zero=false 536port=system.membus.master[0] 537 |