| config.ini (8983:8800b05e1cb3) | config.ini (9055:38f1926fb599) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 461 unchanged lines hidden (view full) --- 470tgts_per_mshr=5 471trace_addr=0 472two_queue=false 473write_buffers=8 474cpu_side=system.cpu.toL2Bus.master[0] 475mem_side=system.membus.slave[1] 476 477[system.cpu.toL2Bus] | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 461 unchanged lines hidden (view full) --- 470tgts_per_mshr=5 471trace_addr=0 472two_queue=false 473write_buffers=8 474cpu_side=system.cpu.toL2Bus.master[0] 475mem_side=system.membus.slave[1] 476 477[system.cpu.toL2Bus] |
| 478type=Bus | 478type=CoherentBus |
| 479block_size=64 | 479block_size=64 |
| 480bus_id=0 | |
| 481clock=1000 482header_cycles=1 483use_default_range=false 484width=64 485master=system.cpu.l2cache.cpu_side 486slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 487 488[system.cpu.tracer] --- 14 unchanged lines hidden (view full) --- 503output=cout 504pid=100 505ppid=99 506simpoint=0 507system=system 508uid=100 509 510[system.membus] | 480clock=1000 481header_cycles=1 482use_default_range=false 483width=64 484master=system.cpu.l2cache.cpu_side 485slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 486 487[system.cpu.tracer] --- 14 unchanged lines hidden (view full) --- 502output=cout 503pid=100 504ppid=99 505simpoint=0 506system=system 507uid=100 508 509[system.membus] |
| 511type=Bus | 510type=CoherentBus |
| 512block_size=64 | 511block_size=64 |
| 513bus_id=0 | |
| 514clock=1000 515header_cycles=1 516use_default_range=false 517width=64 518master=system.physmem.port[0] 519slave=system.system_port system.cpu.l2cache.mem_side 520 521[system.physmem] 522type=SimpleMemory 523conf_table_reported=false 524file= 525in_addr_map=true 526latency=30000 527latency_var=0 528null=false 529range=0:134217727 530zero=false 531port=system.membus.master[0] 532 | 512clock=1000 513header_cycles=1 514use_default_range=false 515width=64 516master=system.physmem.port[0] 517slave=system.system_port system.cpu.l2cache.mem_side 518 519[system.physmem] 520type=SimpleMemory 521conf_table_reported=false 522file= 523in_addr_map=true 524latency=30000 525latency_var=0 526null=false 527range=0:134217727 528zero=false 529port=system.membus.master[0] 530 |