| config.ini (11680:b4d943429dc6) | config.ini (11731:c473ca7cc650) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 164 unchanged lines hidden (view full) --- 173 174[system.cpu.dcache] 175type=Cache 176children=tags 177addr_ranges=0:18446744073709551615:0:0:0:0 178assoc=2 179clk_domain=system.cpu_clk_domain 180clusivity=mostly_incl | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 164 unchanged lines hidden (view full) --- 173 174[system.cpu.dcache] 175type=Cache 176children=tags 177addr_ranges=0:18446744073709551615:0:0:0:0 178assoc=2 179clk_domain=system.cpu_clk_domain 180clusivity=mostly_incl |
| 181data_latency=2 |
|
| 181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 | 182default_p_state=UNDEFINED 183demand_mshr_reserve=1 184eventq_index=0 |
| 184hit_latency=2 | |
| 185is_read_only=false 186max_miss_count=0 187mshrs=4 188p_state_clk_gate_bins=20 189p_state_clk_gate_max=1000000000000 190p_state_clk_gate_min=1000 191power_model=Null 192prefetch_on_access=false 193prefetcher=Null 194response_latency=2 195sequential_access=false 196size=262144 197system=system | 185is_read_only=false 186max_miss_count=0 187mshrs=4 188p_state_clk_gate_bins=20 189p_state_clk_gate_max=1000000000000 190p_state_clk_gate_min=1000 191power_model=Null 192prefetch_on_access=false 193prefetcher=Null 194response_latency=2 195sequential_access=false 196size=262144 197system=system |
| 198tag_latency=2 |
|
| 198tags=system.cpu.dcache.tags 199tgts_per_mshr=20 200write_buffers=8 201writeback_clean=false 202cpu_side=system.cpu.dcache_port 203mem_side=system.cpu.toL2Bus.slave[1] 204 205[system.cpu.dcache.tags] 206type=LRU 207assoc=2 208block_size=64 209clk_domain=system.cpu_clk_domain | 199tags=system.cpu.dcache.tags 200tgts_per_mshr=20 201write_buffers=8 202writeback_clean=false 203cpu_side=system.cpu.dcache_port 204mem_side=system.cpu.toL2Bus.slave[1] 205 206[system.cpu.dcache.tags] 207type=LRU 208assoc=2 209block_size=64 210clk_domain=system.cpu_clk_domain |
| 211data_latency=2 |
|
| 210default_p_state=UNDEFINED 211eventq_index=0 | 212default_p_state=UNDEFINED 213eventq_index=0 |
| 212hit_latency=2 | |
| 213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=262144 | 214p_state_clk_gate_bins=20 215p_state_clk_gate_max=1000000000000 216p_state_clk_gate_min=1000 217power_model=Null 218sequential_access=false 219size=262144 |
| 220tag_latency=2 |
|
| 219 220[system.cpu.dtb] 221type=PowerTLB 222eventq_index=0 223size=64 224 225[system.cpu.fuPool] 226type=FUPool --- 61 unchanged lines hidden (view full) --- 288type=OpDesc 289eventq_index=0 290opClass=FloatCvt 291opLat=2 292pipelined=true 293 294[system.cpu.fuPool.FUList3] 295type=FUDesc | 221 222[system.cpu.dtb] 223type=PowerTLB 224eventq_index=0 225size=64 226 227[system.cpu.fuPool] 228type=FUPool --- 61 unchanged lines hidden (view full) --- 290type=OpDesc 291eventq_index=0 292opClass=FloatCvt 293opLat=2 294pipelined=true 295 296[system.cpu.fuPool.FUList3] 297type=FUDesc |
| 296children=opList0 opList1 opList2 | 298children=opList0 opList1 opList2 opList3 opList4 |
| 297count=2 298eventq_index=0 | 299count=2 300eventq_index=0 |
| 299opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 | 301opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 |
| 300 301[system.cpu.fuPool.FUList3.opList0] 302type=OpDesc 303eventq_index=0 304opClass=FloatMult 305opLat=4 306pipelined=true 307 308[system.cpu.fuPool.FUList3.opList1] 309type=OpDesc 310eventq_index=0 | 302 303[system.cpu.fuPool.FUList3.opList0] 304type=OpDesc 305eventq_index=0 306opClass=FloatMult 307opLat=4 308pipelined=true 309 310[system.cpu.fuPool.FUList3.opList1] 311type=OpDesc 312eventq_index=0 |
| 313opClass=FloatMultAcc 314opLat=5 315pipelined=true 316 317[system.cpu.fuPool.FUList3.opList2] 318type=OpDesc 319eventq_index=0 320opClass=FloatMisc 321opLat=3 322pipelined=true 323 324[system.cpu.fuPool.FUList3.opList3] 325type=OpDesc 326eventq_index=0 |
|
| 311opClass=FloatDiv 312opLat=12 313pipelined=false 314 | 327opClass=FloatDiv 328opLat=12 329pipelined=false 330 |
| 315[system.cpu.fuPool.FUList3.opList2] | 331[system.cpu.fuPool.FUList3.opList4] |
| 316type=OpDesc 317eventq_index=0 318opClass=FloatSqrt 319opLat=24 320pipelined=false 321 322[system.cpu.fuPool.FUList4] 323type=FUDesc | 332type=OpDesc 333eventq_index=0 334opClass=FloatSqrt 335opLat=24 336pipelined=false 337 338[system.cpu.fuPool.FUList4] 339type=FUDesc |
| 324children=opList | 340children=opList0 opList1 |
| 325count=0 326eventq_index=0 | 341count=0 342eventq_index=0 |
| 327opList=system.cpu.fuPool.FUList4.opList | 343opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 |
| 328 | 344 |
| 329[system.cpu.fuPool.FUList4.opList] | 345[system.cpu.fuPool.FUList4.opList0] |
| 330type=OpDesc 331eventq_index=0 332opClass=MemRead 333opLat=1 334pipelined=true 335 | 346type=OpDesc 347eventq_index=0 348opClass=MemRead 349opLat=1 350pipelined=true 351 |
| 352[system.cpu.fuPool.FUList4.opList1] 353type=OpDesc 354eventq_index=0 355opClass=FloatMemRead 356opLat=1 357pipelined=true 358 |
|
| 336[system.cpu.fuPool.FUList5] 337type=FUDesc 338children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 339count=4 340eventq_index=0 341opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 342 343[system.cpu.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 477type=OpDesc 478eventq_index=0 479opClass=SimdFloatSqrt 480opLat=1 481pipelined=true 482 483[system.cpu.fuPool.FUList6] 484type=FUDesc | 359[system.cpu.fuPool.FUList5] 360type=FUDesc 361children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 362count=4 363eventq_index=0 364opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 365 366[system.cpu.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 500type=OpDesc 501eventq_index=0 502opClass=SimdFloatSqrt 503opLat=1 504pipelined=true 505 506[system.cpu.fuPool.FUList6] 507type=FUDesc |
| 485children=opList | 508children=opList0 opList1 |
| 486count=0 487eventq_index=0 | 509count=0 510eventq_index=0 |
| 488opList=system.cpu.fuPool.FUList6.opList | 511opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 |
| 489 | 512 |
| 490[system.cpu.fuPool.FUList6.opList] | 513[system.cpu.fuPool.FUList6.opList0] |
| 491type=OpDesc 492eventq_index=0 493opClass=MemWrite 494opLat=1 495pipelined=true 496 | 514type=OpDesc 515eventq_index=0 516opClass=MemWrite 517opLat=1 518pipelined=true 519 |
| 520[system.cpu.fuPool.FUList6.opList1] 521type=OpDesc 522eventq_index=0 523opClass=FloatMemWrite 524opLat=1 525pipelined=true 526 |
|
| 497[system.cpu.fuPool.FUList7] 498type=FUDesc | 527[system.cpu.fuPool.FUList7] 528type=FUDesc |
| 499children=opList0 opList1 | 529children=opList0 opList1 opList2 opList3 |
| 500count=4 501eventq_index=0 | 530count=4 531eventq_index=0 |
| 502opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 | 532opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 |
| 503 504[system.cpu.fuPool.FUList7.opList0] 505type=OpDesc 506eventq_index=0 507opClass=MemRead 508opLat=1 509pipelined=true 510 511[system.cpu.fuPool.FUList7.opList1] 512type=OpDesc 513eventq_index=0 514opClass=MemWrite 515opLat=1 516pipelined=true 517 | 533 534[system.cpu.fuPool.FUList7.opList0] 535type=OpDesc 536eventq_index=0 537opClass=MemRead 538opLat=1 539pipelined=true 540 541[system.cpu.fuPool.FUList7.opList1] 542type=OpDesc 543eventq_index=0 544opClass=MemWrite 545opLat=1 546pipelined=true 547 |
| 548[system.cpu.fuPool.FUList7.opList2] 549type=OpDesc 550eventq_index=0 551opClass=FloatMemRead 552opLat=1 553pipelined=true 554 555[system.cpu.fuPool.FUList7.opList3] 556type=OpDesc 557eventq_index=0 558opClass=FloatMemWrite 559opLat=1 560pipelined=true 561 |
|
| 518[system.cpu.fuPool.FUList8] 519type=FUDesc 520children=opList 521count=1 522eventq_index=0 523opList=system.cpu.fuPool.FUList8.opList 524 525[system.cpu.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 531 532[system.cpu.icache] 533type=Cache 534children=tags 535addr_ranges=0:18446744073709551615:0:0:0:0 536assoc=2 537clk_domain=system.cpu_clk_domain 538clusivity=mostly_incl | 562[system.cpu.fuPool.FUList8] 563type=FUDesc 564children=opList 565count=1 566eventq_index=0 567opList=system.cpu.fuPool.FUList8.opList 568 569[system.cpu.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 575 576[system.cpu.icache] 577type=Cache 578children=tags 579addr_ranges=0:18446744073709551615:0:0:0:0 580assoc=2 581clk_domain=system.cpu_clk_domain 582clusivity=mostly_incl |
| 583data_latency=2 |
|
| 539default_p_state=UNDEFINED 540demand_mshr_reserve=1 541eventq_index=0 | 584default_p_state=UNDEFINED 585demand_mshr_reserve=1 586eventq_index=0 |
| 542hit_latency=2 | |
| 543is_read_only=true 544max_miss_count=0 545mshrs=4 546p_state_clk_gate_bins=20 547p_state_clk_gate_max=1000000000000 548p_state_clk_gate_min=1000 549power_model=Null 550prefetch_on_access=false 551prefetcher=Null 552response_latency=2 553sequential_access=false 554size=131072 555system=system | 587is_read_only=true 588max_miss_count=0 589mshrs=4 590p_state_clk_gate_bins=20 591p_state_clk_gate_max=1000000000000 592p_state_clk_gate_min=1000 593power_model=Null 594prefetch_on_access=false 595prefetcher=Null 596response_latency=2 597sequential_access=false 598size=131072 599system=system |
| 600tag_latency=2 |
|
| 556tags=system.cpu.icache.tags 557tgts_per_mshr=20 558write_buffers=8 559writeback_clean=true 560cpu_side=system.cpu.icache_port 561mem_side=system.cpu.toL2Bus.slave[0] 562 563[system.cpu.icache.tags] 564type=LRU 565assoc=2 566block_size=64 567clk_domain=system.cpu_clk_domain | 601tags=system.cpu.icache.tags 602tgts_per_mshr=20 603write_buffers=8 604writeback_clean=true 605cpu_side=system.cpu.icache_port 606mem_side=system.cpu.toL2Bus.slave[0] 607 608[system.cpu.icache.tags] 609type=LRU 610assoc=2 611block_size=64 612clk_domain=system.cpu_clk_domain |
| 613data_latency=2 |
|
| 568default_p_state=UNDEFINED 569eventq_index=0 | 614default_p_state=UNDEFINED 615eventq_index=0 |
| 570hit_latency=2 | |
| 571p_state_clk_gate_bins=20 572p_state_clk_gate_max=1000000000000 573p_state_clk_gate_min=1000 574power_model=Null 575sequential_access=false 576size=131072 | 616p_state_clk_gate_bins=20 617p_state_clk_gate_max=1000000000000 618p_state_clk_gate_min=1000 619power_model=Null 620sequential_access=false 621size=131072 |
| 622tag_latency=2 |
|
| 577 578[system.cpu.interrupts] 579type=PowerInterrupts 580eventq_index=0 581 582[system.cpu.isa] 583type=PowerISA 584eventq_index=0 --- 5 unchanged lines hidden (view full) --- 590 591[system.cpu.l2cache] 592type=Cache 593children=tags 594addr_ranges=0:18446744073709551615:0:0:0:0 595assoc=8 596clk_domain=system.cpu_clk_domain 597clusivity=mostly_incl | 623 624[system.cpu.interrupts] 625type=PowerInterrupts 626eventq_index=0 627 628[system.cpu.isa] 629type=PowerISA 630eventq_index=0 --- 5 unchanged lines hidden (view full) --- 636 637[system.cpu.l2cache] 638type=Cache 639children=tags 640addr_ranges=0:18446744073709551615:0:0:0:0 641assoc=8 642clk_domain=system.cpu_clk_domain 643clusivity=mostly_incl |
| 644data_latency=20 |
|
| 598default_p_state=UNDEFINED 599demand_mshr_reserve=1 600eventq_index=0 | 645default_p_state=UNDEFINED 646demand_mshr_reserve=1 647eventq_index=0 |
| 601hit_latency=20 | |
| 602is_read_only=false 603max_miss_count=0 604mshrs=20 605p_state_clk_gate_bins=20 606p_state_clk_gate_max=1000000000000 607p_state_clk_gate_min=1000 608power_model=Null 609prefetch_on_access=false 610prefetcher=Null 611response_latency=20 612sequential_access=false 613size=2097152 614system=system | 648is_read_only=false 649max_miss_count=0 650mshrs=20 651p_state_clk_gate_bins=20 652p_state_clk_gate_max=1000000000000 653p_state_clk_gate_min=1000 654power_model=Null 655prefetch_on_access=false 656prefetcher=Null 657response_latency=20 658sequential_access=false 659size=2097152 660system=system |
| 661tag_latency=20 |
|
| 615tags=system.cpu.l2cache.tags 616tgts_per_mshr=12 617write_buffers=8 618writeback_clean=false 619cpu_side=system.cpu.toL2Bus.master[0] 620mem_side=system.membus.slave[1] 621 622[system.cpu.l2cache.tags] 623type=LRU 624assoc=8 625block_size=64 626clk_domain=system.cpu_clk_domain | 662tags=system.cpu.l2cache.tags 663tgts_per_mshr=12 664write_buffers=8 665writeback_clean=false 666cpu_side=system.cpu.toL2Bus.master[0] 667mem_side=system.membus.slave[1] 668 669[system.cpu.l2cache.tags] 670type=LRU 671assoc=8 672block_size=64 673clk_domain=system.cpu_clk_domain |
| 674data_latency=20 |
|
| 627default_p_state=UNDEFINED 628eventq_index=0 | 675default_p_state=UNDEFINED 676eventq_index=0 |
| 629hit_latency=20 | |
| 630p_state_clk_gate_bins=20 631p_state_clk_gate_max=1000000000000 632p_state_clk_gate_min=1000 633power_model=Null 634sequential_access=false 635size=2097152 | 677p_state_clk_gate_bins=20 678p_state_clk_gate_max=1000000000000 679p_state_clk_gate_min=1000 680power_model=Null 681sequential_access=false 682size=2097152 |
| 683tag_latency=20 |
|
| 636 637[system.cpu.toL2Bus] 638type=CoherentXBar 639children=snoop_filter 640clk_domain=system.cpu_clk_domain 641default_p_state=UNDEFINED 642eventq_index=0 643forward_latency=0 --- 28 unchanged lines hidden (view full) --- 672cmd=hello 673cwd= 674drivers= 675egid=100 676env= 677errout=cerr 678euid=100 679eventq_index=0 | 684 685[system.cpu.toL2Bus] 686type=CoherentXBar 687children=snoop_filter 688clk_domain=system.cpu_clk_domain 689default_p_state=UNDEFINED 690eventq_index=0 691forward_latency=0 --- 28 unchanged lines hidden (view full) --- 720cmd=hello 721cwd= 722drivers= 723egid=100 724env= 725errout=cerr 726euid=100 727eventq_index=0 |
| 680executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello | 728executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello |
| 681gid=100 682input=cin 683kvmInSE=false 684max_stack_size=67108864 685output=cout 686pid=100 687ppid=99 688simpoint=0 --- 137 unchanged lines hidden --- | 729gid=100 730input=cin 731kvmInSE=false 732max_stack_size=67108864 733output=cout 734pid=100 735ppid=99 736simpoint=0 --- 137 unchanged lines hidden --- |