| config.ini (11570:4aac82f10951) | config.ini (11680:b4d943429dc6) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 160 unchanged lines hidden (view full) --- 169localHistoryTableSize=2048 170localPredictorSize=2048 171numThreads=1 172useIndirect=true 173 174[system.cpu.dcache] 175type=Cache 176children=tags | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 160 unchanged lines hidden (view full) --- 169localHistoryTableSize=2048 170localPredictorSize=2048 171numThreads=1 172useIndirect=true 173 174[system.cpu.dcache] 175type=Cache 176children=tags |
| 177addr_ranges=0:18446744073709551615 | 177addr_ranges=0:18446744073709551615:0:0:0:0 |
| 178assoc=2 179clk_domain=system.cpu_clk_domain 180clusivity=mostly_incl 181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 184hit_latency=2 185is_read_only=false --- 341 unchanged lines hidden (view full) --- 527eventq_index=0 528opClass=IprAccess 529opLat=3 530pipelined=false 531 532[system.cpu.icache] 533type=Cache 534children=tags | 178assoc=2 179clk_domain=system.cpu_clk_domain 180clusivity=mostly_incl 181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 184hit_latency=2 185is_read_only=false --- 341 unchanged lines hidden (view full) --- 527eventq_index=0 528opClass=IprAccess 529opLat=3 530pipelined=false 531 532[system.cpu.icache] 533type=Cache 534children=tags |
| 535addr_ranges=0:18446744073709551615 | 535addr_ranges=0:18446744073709551615:0:0:0:0 |
| 536assoc=2 537clk_domain=system.cpu_clk_domain 538clusivity=mostly_incl 539default_p_state=UNDEFINED 540demand_mshr_reserve=1 541eventq_index=0 542hit_latency=2 543is_read_only=true --- 42 unchanged lines hidden (view full) --- 586[system.cpu.itb] 587type=PowerTLB 588eventq_index=0 589size=64 590 591[system.cpu.l2cache] 592type=Cache 593children=tags | 536assoc=2 537clk_domain=system.cpu_clk_domain 538clusivity=mostly_incl 539default_p_state=UNDEFINED 540demand_mshr_reserve=1 541eventq_index=0 542hit_latency=2 543is_read_only=true --- 42 unchanged lines hidden (view full) --- 586[system.cpu.itb] 587type=PowerTLB 588eventq_index=0 589size=64 590 591[system.cpu.l2cache] 592type=Cache 593children=tags |
| 594addr_ranges=0:18446744073709551615 | 594addr_ranges=0:18446744073709551615:0:0:0:0 |
| 595assoc=8 596clk_domain=system.cpu_clk_domain 597clusivity=mostly_incl 598default_p_state=UNDEFINED 599demand_mshr_reserve=1 600eventq_index=0 601hit_latency=20 602is_read_only=false --- 100 unchanged lines hidden (view full) --- 703domains= 704enable=false 705eventq_index=0 706sys_clk_domain=system.clk_domain 707transition_latency=100000000 708 709[system.membus] 710type=CoherentXBar | 595assoc=8 596clk_domain=system.cpu_clk_domain 597clusivity=mostly_incl 598default_p_state=UNDEFINED 599demand_mshr_reserve=1 600eventq_index=0 601hit_latency=20 602is_read_only=false --- 100 unchanged lines hidden (view full) --- 703domains= 704enable=false 705eventq_index=0 706sys_clk_domain=system.clk_domain 707transition_latency=100000000 708 709[system.membus] 710type=CoherentXBar |
| 711children=snoop_filter |
|
| 711clk_domain=system.clk_domain 712default_p_state=UNDEFINED 713eventq_index=0 714forward_latency=4 715frontend_latency=3 716p_state_clk_gate_bins=20 717p_state_clk_gate_max=1000000000000 718p_state_clk_gate_min=1000 719point_of_coherency=true 720power_model=Null 721response_latency=2 | 712clk_domain=system.clk_domain 713default_p_state=UNDEFINED 714eventq_index=0 715forward_latency=4 716frontend_latency=3 717p_state_clk_gate_bins=20 718p_state_clk_gate_max=1000000000000 719p_state_clk_gate_min=1000 720point_of_coherency=true 721power_model=Null 722response_latency=2 |
| 722snoop_filter=Null | 723snoop_filter=system.membus.snoop_filter |
| 723snoop_response_latency=4 724system=system 725use_default_range=false 726width=16 727master=system.physmem.port 728slave=system.system_port system.cpu.l2cache.mem_side 729 | 724snoop_response_latency=4 725system=system 726use_default_range=false 727width=16 728master=system.physmem.port 729slave=system.system_port system.cpu.l2cache.mem_side 730 |
| 731[system.membus.snoop_filter] 732type=SnoopFilter 733eventq_index=0 734lookup_latency=1 735max_capacity=8388608 736system=system 737 |
|
| 730[system.physmem] 731type=DRAMCtrl | 738[system.physmem] 739type=DRAMCtrl |
| 732IDD0=0.075000 | 740IDD0=0.055000 |
| 733IDD02=0.000000 | 741IDD02=0.000000 |
| 734IDD2N=0.050000 | 742IDD2N=0.032000 |
| 735IDD2N2=0.000000 736IDD2P0=0.000000 737IDD2P02=0.000000 | 743IDD2N2=0.000000 744IDD2P0=0.000000 745IDD2P02=0.000000 |
| 738IDD2P1=0.000000 | 746IDD2P1=0.032000 |
| 739IDD2P12=0.000000 | 747IDD2P12=0.000000 |
| 740IDD3N=0.057000 | 748IDD3N=0.038000 |
| 741IDD3N2=0.000000 742IDD3P0=0.000000 743IDD3P02=0.000000 | 749IDD3N2=0.000000 750IDD3P0=0.000000 751IDD3P02=0.000000 |
| 744IDD3P1=0.000000 | 752IDD3P1=0.038000 |
| 745IDD3P12=0.000000 | 753IDD3P12=0.000000 |
| 746IDD4R=0.187000 | 754IDD4R=0.157000 |
| 747IDD4R2=0.000000 | 755IDD4R2=0.000000 |
| 748IDD4W=0.165000 | 756IDD4W=0.125000 |
| 749IDD4W2=0.000000 | 757IDD4W2=0.000000 |
| 750IDD5=0.220000 | 758IDD5=0.235000 |
| 751IDD52=0.000000 | 759IDD52=0.000000 |
| 752IDD6=0.000000 | 760IDD6=0.020000 |
| 753IDD62=0.000000 754VDD=1.500000 755VDD2=0.000000 756activation_limit=4 757addr_mapping=RoRaBaCoCh 758bank_groups_per_rank=0 759banks_per_rank=8 760burst_length=8 761channels=1 762clk_domain=system.clk_domain 763conf_table_reported=true 764default_p_state=UNDEFINED 765device_bus_width=8 766device_rowbuffer_size=1024 767device_size=536870912 768devices_per_rank=8 769dll=true 770eventq_index=0 771in_addr_map=true | 761IDD62=0.000000 762VDD=1.500000 763VDD2=0.000000 764activation_limit=4 765addr_mapping=RoRaBaCoCh 766bank_groups_per_rank=0 767banks_per_rank=8 768burst_length=8 769channels=1 770clk_domain=system.clk_domain 771conf_table_reported=true 772default_p_state=UNDEFINED 773device_bus_width=8 774device_rowbuffer_size=1024 775device_size=536870912 776devices_per_rank=8 777dll=true 778eventq_index=0 779in_addr_map=true |
| 780kvm_map=true |
|
| 772max_accesses_per_row=16 773mem_sched_policy=frfcfs 774min_writes_per_switch=16 775null=false 776p_state_clk_gate_bins=20 777p_state_clk_gate_max=1000000000000 778p_state_clk_gate_min=1000 779page_policy=open_adaptive 780power_model=Null | 781max_accesses_per_row=16 782mem_sched_policy=frfcfs 783min_writes_per_switch=16 784null=false 785p_state_clk_gate_bins=20 786p_state_clk_gate_max=1000000000000 787p_state_clk_gate_min=1000 788page_policy=open_adaptive 789power_model=Null |
| 781range=0:134217727 | 790range=0:134217727:0:0:0:0 |
| 782ranks_per_channel=2 783read_buffer_size=32 784static_backend_latency=10000 785static_frontend_latency=10000 786tBURST=5000 787tCCD_L=0 788tCK=1250 789tCL=13750 --- 5 unchanged lines hidden (view full) --- 795tRP=13750 796tRRD=6000 797tRRD_L=0 798tRTP=7500 799tRTW=2500 800tWR=15000 801tWTR=7500 802tXAW=30000 | 791ranks_per_channel=2 792read_buffer_size=32 793static_backend_latency=10000 794static_frontend_latency=10000 795tBURST=5000 796tCCD_L=0 797tCK=1250 798tCL=13750 --- 5 unchanged lines hidden (view full) --- 804tRP=13750 805tRRD=6000 806tRRD_L=0 807tRTP=7500 808tRTW=2500 809tWR=15000 810tWTR=7500 811tXAW=30000 |
| 803tXP=0 | 812tXP=6000 |
| 804tXPDLL=0 | 813tXPDLL=0 |
| 805tXS=0 | 814tXS=270000 |
| 806tXSDLL=0 807write_buffer_size=64 808write_high_thresh_perc=85 809write_low_thresh_perc=50 810port=system.membus.master[0] 811 812[system.voltage_domain] 813type=VoltageDomain 814eventq_index=0 815voltage=1.000000 816 | 815tXSDLL=0 816write_buffer_size=64 817write_high_thresh_perc=85 818write_low_thresh_perc=50 819port=system.membus.master[0] 820 821[system.voltage_domain] 822type=VoltageDomain 823eventq_index=0 824voltage=1.000000 825 |