config.ini (11312:3d7a85d71bd1) config.ini (11384:e3cbd2823210)
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 147 unchanged lines hidden (view full) ---

156type=Cache
157children=tags
158addr_ranges=0:18446744073709551615
159assoc=2
160clk_domain=system.cpu_clk_domain
161clusivity=mostly_incl
162demand_mshr_reserve=1
163eventq_index=0
1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 147 unchanged lines hidden (view full) ---

156type=Cache
157children=tags
158addr_ranges=0:18446744073709551615
159assoc=2
160clk_domain=system.cpu_clk_domain
161clusivity=mostly_incl
162demand_mshr_reserve=1
163eventq_index=0
164forward_snoops=true
165hit_latency=2
166is_read_only=false
167max_miss_count=0
168mshrs=4
169prefetch_on_access=false
170prefetcher=Null
171response_latency=2
172sequential_access=false

--- 332 unchanged lines hidden (view full) ---

505type=Cache
506children=tags
507addr_ranges=0:18446744073709551615
508assoc=2
509clk_domain=system.cpu_clk_domain
510clusivity=mostly_incl
511demand_mshr_reserve=1
512eventq_index=0
164hit_latency=2
165is_read_only=false
166max_miss_count=0
167mshrs=4
168prefetch_on_access=false
169prefetcher=Null
170response_latency=2
171sequential_access=false

--- 332 unchanged lines hidden (view full) ---

504type=Cache
505children=tags
506addr_ranges=0:18446744073709551615
507assoc=2
508clk_domain=system.cpu_clk_domain
509clusivity=mostly_incl
510demand_mshr_reserve=1
511eventq_index=0
513forward_snoops=true
514hit_latency=2
515is_read_only=true
516max_miss_count=0
517mshrs=4
518prefetch_on_access=false
519prefetcher=Null
520response_latency=2
521sequential_access=false

--- 33 unchanged lines hidden (view full) ---

555type=Cache
556children=tags
557addr_ranges=0:18446744073709551615
558assoc=8
559clk_domain=system.cpu_clk_domain
560clusivity=mostly_incl
561demand_mshr_reserve=1
562eventq_index=0
512hit_latency=2
513is_read_only=true
514max_miss_count=0
515mshrs=4
516prefetch_on_access=false
517prefetcher=Null
518response_latency=2
519sequential_access=false

--- 33 unchanged lines hidden (view full) ---

553type=Cache
554children=tags
555addr_ranges=0:18446744073709551615
556assoc=8
557clk_domain=system.cpu_clk_domain
558clusivity=mostly_incl
559demand_mshr_reserve=1
560eventq_index=0
563forward_snoops=true
564hit_latency=20
565is_read_only=false
566max_miss_count=0
567mshrs=20
568prefetch_on_access=false
569prefetcher=Null
570response_latency=20
571sequential_access=false

--- 18 unchanged lines hidden (view full) ---

590
591[system.cpu.toL2Bus]
592type=CoherentXBar
593children=snoop_filter
594clk_domain=system.cpu_clk_domain
595eventq_index=0
596forward_latency=0
597frontend_latency=1
561hit_latency=20
562is_read_only=false
563max_miss_count=0
564mshrs=20
565prefetch_on_access=false
566prefetcher=Null
567response_latency=20
568sequential_access=false

--- 18 unchanged lines hidden (view full) ---

587
588[system.cpu.toL2Bus]
589type=CoherentXBar
590children=snoop_filter
591clk_domain=system.cpu_clk_domain
592eventq_index=0
593forward_latency=0
594frontend_latency=1
595point_of_coherency=false
598response_latency=1
599snoop_filter=system.cpu.toL2Bus.snoop_filter
600snoop_response_latency=1
601system=system
602use_default_range=false
603width=32
604master=system.cpu.l2cache.cpu_side
605slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side

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620cmd=hello
621cwd=
622drivers=
623egid=100
624env=
625errout=cerr
626euid=100
627eventq_index=0
596response_latency=1
597snoop_filter=system.cpu.toL2Bus.snoop_filter
598snoop_response_latency=1
599system=system
600use_default_range=false
601width=32
602master=system.cpu.l2cache.cpu_side
603slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side

--- 14 unchanged lines hidden (view full) ---

618cmd=hello
619cwd=
620drivers=
621egid=100
622env=
623errout=cerr
624euid=100
625eventq_index=0
628executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
626executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/power/linux/hello
629gid=100
630input=cin
631kvmInSE=false
632max_stack_size=67108864
633output=cout
634pid=100
635ppid=99
636simpoint=0

--- 18 unchanged lines hidden (view full) ---

655transition_latency=100000000
656
657[system.membus]
658type=CoherentXBar
659clk_domain=system.clk_domain
660eventq_index=0
661forward_latency=4
662frontend_latency=3
627gid=100
628input=cin
629kvmInSE=false
630max_stack_size=67108864
631output=cout
632pid=100
633ppid=99
634simpoint=0

--- 18 unchanged lines hidden (view full) ---

653transition_latency=100000000
654
655[system.membus]
656type=CoherentXBar
657clk_domain=system.clk_domain
658eventq_index=0
659forward_latency=4
660frontend_latency=3
661point_of_coherency=true
663response_latency=2
664snoop_filter=Null
665snoop_response_latency=4
666system=system
667use_default_range=false
668width=16
669master=system.physmem.port
670slave=system.system_port system.cpu.l2cache.mem_side

--- 83 unchanged lines hidden ---
662response_latency=2
663snoop_filter=Null
664snoop_response_latency=4
665system=system
666use_default_range=false
667width=16
668master=system.physmem.port
669slave=system.system_port system.cpu.l2cache.mem_side

--- 83 unchanged lines hidden ---