1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
9time_sync_spin_threshold=100000000
10
11[system]
12type=System
13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17eventq_index=0
18init_param=0
19kernel=
20kernel_addr_check=true
21load_addr_mask=1099511627775
22load_offset=0
23mem_mode=timing
24mem_ranges=
25memories=system.physmem
26mmap_using_noreserve=false
27num_work_ids=16
28readfile=
29symbolfile=
30work_begin_ckpt_count=0
31work_begin_cpu_id_exit=-1
32work_begin_exit_count=0
33work_cpus_ckpt_count=0
34work_end_ckpt_count=0
35work_end_exit_count=0
36work_item_id=-1
37system_port=system.membus.slave[0]
38
39[system.clk_domain]
40type=SrcClockDomain
41clock=1000
42domain_id=-1
43eventq_index=0
44init_perf_level=0
45voltage_domain=system.voltage_domain
46
47[system.cpu]
48type=DerivO3CPU
49children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
50LFSTSize=1024
51LQEntries=32
52LSQCheckLoads=true
53LSQDepCheckShift=4
54SQEntries=32
55SSITSize=1024
56UnifiedTLB=true
57activity=0
58backComSize=5
59branchPred=system.cpu.branchPred
60cachePorts=200
61checker=Null
62clk_domain=system.cpu_clk_domain
63commitToDecodeDelay=1
64commitToFetchDelay=1
65commitToIEWDelay=1
66commitToRenameDelay=1
67commitWidth=8
68cpu_id=0
69decodeToFetchDelay=1
70decodeToRenameDelay=1
71decodeWidth=8
72dispatchWidth=8
73do_checkpoint_insts=true
74do_quiesce=true
75do_statistics_insts=true
76dtb=system.cpu.dtb
77eventq_index=0
78fetchBufferSize=64
79fetchQueueSize=32
80fetchToDecodeDelay=1
81fetchTrapLatency=1
82fetchWidth=8
83forwardComSize=5
84fuPool=system.cpu.fuPool
85function_trace=false
86function_trace_start=0
87iewToCommitDelay=1
88iewToDecodeDelay=1
89iewToFetchDelay=1
90iewToRenameDelay=1
91interrupts=system.cpu.interrupts
92isa=system.cpu.isa
93issueToExecuteDelay=1
94issueWidth=8
95itb=system.cpu.itb
96max_insts_all_threads=0
97max_insts_any_thread=0
98max_loads_all_threads=0
99max_loads_any_thread=0
100needsTSO=false
101numIQEntries=64
102numPhysCCRegs=0
103numPhysFloatRegs=256
104numPhysIntRegs=256
105numROBEntries=192
106numRobs=1
107numThreads=1
108profile=0
109progress_interval=0
110renameToDecodeDelay=1
111renameToFetchDelay=1
112renameToIEWDelay=2
113renameToROBDelay=1
114renameWidth=8
115simpoint_start_insts=
116smtCommitPolicy=RoundRobin
117smtFetchPolicy=SingleThread
118smtIQPolicy=Partitioned
119smtIQThreshold=100
120smtLSQPolicy=Partitioned
121smtLSQThreshold=100
122smtNumFetchingThreads=1
123smtROBPolicy=Partitioned
124smtROBThreshold=100
125socket_id=0
126squashWidth=8
127store_set_clear_period=250000
128switched_out=false
129system=system
130tracer=system.cpu.tracer
131trapLatency=13
132wbWidth=8
133workload=system.cpu.workload
134dcache_port=system.cpu.dcache.cpu_side
135icache_port=system.cpu.icache.cpu_side
136
137[system.cpu.branchPred]
138type=BranchPredictor
139BTBEntries=4096
140BTBTagSize=16
141RASSize=16
142choiceCtrBits=2
143choicePredictorSize=8192
144eventq_index=0
145globalCtrBits=2
146globalPredictorSize=8192
147instShiftAmt=2
148localCtrBits=2
149localHistoryTableSize=2048
150localPredictorSize=2048
151numThreads=1
152predType=tournament
153
154[system.cpu.dcache]
155type=BaseCache
156children=tags
157addr_ranges=0:18446744073709551615
158assoc=2
159clk_domain=system.cpu_clk_domain
160demand_mshr_reserve=1
161eventq_index=0
162forward_snoops=true
163hit_latency=2
164is_top_level=true
165max_miss_count=0
166mshrs=4
167prefetch_on_access=false
168prefetcher=Null
169response_latency=2
170sequential_access=false
171size=262144
172system=system
173tags=system.cpu.dcache.tags
174tgts_per_mshr=20
175two_queue=false
176write_buffers=8
177cpu_side=system.cpu.dcache_port
178mem_side=system.cpu.toL2Bus.slave[1]
179
180[system.cpu.dcache.tags]
181type=LRU
182assoc=2
183block_size=64
184clk_domain=system.cpu_clk_domain
185eventq_index=0
186hit_latency=2
187sequential_access=false
188size=262144
189
190[system.cpu.dtb]
191type=PowerTLB
192eventq_index=0
193size=64
194
195[system.cpu.fuPool]
196type=FUPool
197children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
198FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
199eventq_index=0
200
201[system.cpu.fuPool.FUList0]
202type=FUDesc
203children=opList
204count=6
205eventq_index=0
206opList=system.cpu.fuPool.FUList0.opList
207
208[system.cpu.fuPool.FUList0.opList]
209type=OpDesc
210eventq_index=0
211issueLat=1
212opClass=IntAlu
213opLat=1
214
215[system.cpu.fuPool.FUList1]
216type=FUDesc
217children=opList0 opList1
218count=2
219eventq_index=0
220opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
221
222[system.cpu.fuPool.FUList1.opList0]
223type=OpDesc
224eventq_index=0
225issueLat=1
226opClass=IntMult
227opLat=3
228
229[system.cpu.fuPool.FUList1.opList1]
230type=OpDesc
231eventq_index=0
232issueLat=19
233opClass=IntDiv
234opLat=20
235
236[system.cpu.fuPool.FUList2]
237type=FUDesc
238children=opList0 opList1 opList2
239count=4
240eventq_index=0
241opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
242
243[system.cpu.fuPool.FUList2.opList0]
244type=OpDesc
245eventq_index=0
246issueLat=1
247opClass=FloatAdd
248opLat=2
249
250[system.cpu.fuPool.FUList2.opList1]
251type=OpDesc
252eventq_index=0
253issueLat=1
254opClass=FloatCmp
255opLat=2
256
257[system.cpu.fuPool.FUList2.opList2]
258type=OpDesc
259eventq_index=0
260issueLat=1
261opClass=FloatCvt
262opLat=2
263
264[system.cpu.fuPool.FUList3]
265type=FUDesc
266children=opList0 opList1 opList2
267count=2
268eventq_index=0
269opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
270
271[system.cpu.fuPool.FUList3.opList0]
272type=OpDesc
273eventq_index=0
274issueLat=1
275opClass=FloatMult
276opLat=4
277
278[system.cpu.fuPool.FUList3.opList1]
279type=OpDesc
280eventq_index=0
281issueLat=12
282opClass=FloatDiv
283opLat=12
284
285[system.cpu.fuPool.FUList3.opList2]
286type=OpDesc
287eventq_index=0
288issueLat=24
289opClass=FloatSqrt
290opLat=24
291
292[system.cpu.fuPool.FUList4]
293type=FUDesc
294children=opList
295count=0
296eventq_index=0
297opList=system.cpu.fuPool.FUList4.opList
298
299[system.cpu.fuPool.FUList4.opList]
300type=OpDesc
301eventq_index=0
302issueLat=1
303opClass=MemRead
304opLat=1
305
306[system.cpu.fuPool.FUList5]
307type=FUDesc
308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
309count=4
310eventq_index=0
311opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
312
313[system.cpu.fuPool.FUList5.opList00]
314type=OpDesc
315eventq_index=0
316issueLat=1
317opClass=SimdAdd
318opLat=1
319
320[system.cpu.fuPool.FUList5.opList01]
321type=OpDesc
322eventq_index=0
323issueLat=1
324opClass=SimdAddAcc
325opLat=1
326
327[system.cpu.fuPool.FUList5.opList02]
328type=OpDesc
329eventq_index=0
330issueLat=1
331opClass=SimdAlu
332opLat=1
333
334[system.cpu.fuPool.FUList5.opList03]
335type=OpDesc
336eventq_index=0
337issueLat=1
338opClass=SimdCmp
339opLat=1
340
341[system.cpu.fuPool.FUList5.opList04]
342type=OpDesc
343eventq_index=0
344issueLat=1
345opClass=SimdCvt
346opLat=1
347
348[system.cpu.fuPool.FUList5.opList05]
349type=OpDesc
350eventq_index=0
351issueLat=1
352opClass=SimdMisc
353opLat=1
354
355[system.cpu.fuPool.FUList5.opList06]
356type=OpDesc
357eventq_index=0
358issueLat=1
359opClass=SimdMult
360opLat=1
361
362[system.cpu.fuPool.FUList5.opList07]
363type=OpDesc
364eventq_index=0
365issueLat=1
366opClass=SimdMultAcc
367opLat=1
368
369[system.cpu.fuPool.FUList5.opList08]
370type=OpDesc
371eventq_index=0
372issueLat=1
373opClass=SimdShift
374opLat=1
375
376[system.cpu.fuPool.FUList5.opList09]
377type=OpDesc
378eventq_index=0
379issueLat=1
380opClass=SimdShiftAcc
381opLat=1
382
383[system.cpu.fuPool.FUList5.opList10]
384type=OpDesc
385eventq_index=0
386issueLat=1
387opClass=SimdSqrt
388opLat=1
389
390[system.cpu.fuPool.FUList5.opList11]
391type=OpDesc
392eventq_index=0
393issueLat=1
394opClass=SimdFloatAdd
395opLat=1
396
397[system.cpu.fuPool.FUList5.opList12]
398type=OpDesc
399eventq_index=0
400issueLat=1
401opClass=SimdFloatAlu
402opLat=1
403
404[system.cpu.fuPool.FUList5.opList13]
405type=OpDesc
406eventq_index=0
407issueLat=1
408opClass=SimdFloatCmp
409opLat=1
410
411[system.cpu.fuPool.FUList5.opList14]
412type=OpDesc
413eventq_index=0
414issueLat=1
415opClass=SimdFloatCvt
416opLat=1
417
418[system.cpu.fuPool.FUList5.opList15]
419type=OpDesc
420eventq_index=0
421issueLat=1
422opClass=SimdFloatDiv
423opLat=1
424
425[system.cpu.fuPool.FUList5.opList16]
426type=OpDesc
427eventq_index=0
428issueLat=1
429opClass=SimdFloatMisc
430opLat=1
431
432[system.cpu.fuPool.FUList5.opList17]
433type=OpDesc
434eventq_index=0
435issueLat=1
436opClass=SimdFloatMult
437opLat=1
438
439[system.cpu.fuPool.FUList5.opList18]
440type=OpDesc
441eventq_index=0
442issueLat=1
443opClass=SimdFloatMultAcc
444opLat=1
445
446[system.cpu.fuPool.FUList5.opList19]
447type=OpDesc
448eventq_index=0
449issueLat=1
450opClass=SimdFloatSqrt
451opLat=1
452
453[system.cpu.fuPool.FUList6]
454type=FUDesc
455children=opList
456count=0
457eventq_index=0
458opList=system.cpu.fuPool.FUList6.opList
459
460[system.cpu.fuPool.FUList6.opList]
461type=OpDesc
462eventq_index=0
463issueLat=1
464opClass=MemWrite
465opLat=1
466
467[system.cpu.fuPool.FUList7]
468type=FUDesc
469children=opList0 opList1
470count=4
471eventq_index=0
472opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
473
474[system.cpu.fuPool.FUList7.opList0]
475type=OpDesc
476eventq_index=0
477issueLat=1
478opClass=MemRead
479opLat=1
480
481[system.cpu.fuPool.FUList7.opList1]
482type=OpDesc
483eventq_index=0
484issueLat=1
485opClass=MemWrite
486opLat=1
487
488[system.cpu.fuPool.FUList8]
489type=FUDesc
490children=opList
491count=1
492eventq_index=0
493opList=system.cpu.fuPool.FUList8.opList
494
495[system.cpu.fuPool.FUList8.opList]
496type=OpDesc
497eventq_index=0
498issueLat=3
499opClass=IprAccess
500opLat=3
501
502[system.cpu.icache]
503type=BaseCache
504children=tags
505addr_ranges=0:18446744073709551615
506assoc=2
507clk_domain=system.cpu_clk_domain
508demand_mshr_reserve=1
509eventq_index=0
510forward_snoops=true
511hit_latency=2
512is_top_level=true
513max_miss_count=0
514mshrs=4
515prefetch_on_access=false
516prefetcher=Null
517response_latency=2
518sequential_access=false
519size=131072
520system=system
521tags=system.cpu.icache.tags
522tgts_per_mshr=20
523two_queue=false
524write_buffers=8
525cpu_side=system.cpu.icache_port
526mem_side=system.cpu.toL2Bus.slave[0]
527
528[system.cpu.icache.tags]
529type=LRU
530assoc=2
531block_size=64
532clk_domain=system.cpu_clk_domain
533eventq_index=0
534hit_latency=2
535sequential_access=false
536size=131072
537
538[system.cpu.interrupts]
539type=PowerInterrupts
540eventq_index=0
541
542[system.cpu.isa]
543type=PowerISA
544eventq_index=0
545
546[system.cpu.itb]
547type=PowerTLB
548eventq_index=0
549size=64
550
551[system.cpu.l2cache]
552type=BaseCache
553children=tags
554addr_ranges=0:18446744073709551615
555assoc=8
556clk_domain=system.cpu_clk_domain
557demand_mshr_reserve=1
558eventq_index=0
559forward_snoops=true
560hit_latency=20
561is_top_level=false
562max_miss_count=0
563mshrs=20
564prefetch_on_access=false
565prefetcher=Null
566response_latency=20
567sequential_access=false
568size=2097152
569system=system
570tags=system.cpu.l2cache.tags
571tgts_per_mshr=12
572two_queue=false
573write_buffers=8
574cpu_side=system.cpu.toL2Bus.master[0]
575mem_side=system.membus.slave[1]
576
577[system.cpu.l2cache.tags]
578type=LRU
579assoc=8
580block_size=64
581clk_domain=system.cpu_clk_domain
582eventq_index=0
583hit_latency=20
584sequential_access=false
585size=2097152
586
587[system.cpu.toL2Bus]
588type=CoherentXBar
589clk_domain=system.cpu_clk_domain
590eventq_index=0
587header_cycles=1
591forward_latency=0
592frontend_latency=1
593response_latency=1
594snoop_filter=Null
595snoop_response_latency=1
596system=system
597use_default_range=false
598width=32
599master=system.cpu.l2cache.cpu_side
600slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
601
602[system.cpu.tracer]
603type=ExeTracer
604eventq_index=0
605
606[system.cpu.workload]
607type=LiveProcess
608cmd=hello
609cwd=
610drivers=
611egid=100
612env=
613errout=cerr
614euid=100
615eventq_index=0
616executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello
617gid=100
618input=cin
619kvmInSE=false
620max_stack_size=67108864
621output=cout
622pid=100
623ppid=99
624simpoint=0
625system=system
626uid=100
627useArchPT=false
628
629[system.cpu_clk_domain]
630type=SrcClockDomain
631clock=500
632domain_id=-1
633eventq_index=0
634init_perf_level=0
635voltage_domain=system.voltage_domain
636
637[system.dvfs_handler]
638type=DVFSHandler
639domains=
640enable=false
641eventq_index=0
642sys_clk_domain=system.clk_domain
643transition_latency=100000000
644
645[system.membus]
646type=CoherentXBar
647clk_domain=system.clk_domain
648eventq_index=0
640header_cycles=1
649forward_latency=4
650frontend_latency=3
651response_latency=2
652snoop_filter=Null
653snoop_response_latency=4
654system=system
655use_default_range=false
644width=8
656width=16
657master=system.physmem.port
658slave=system.system_port system.cpu.l2cache.mem_side
659
660[system.physmem]
661type=DRAMCtrl
662IDD0=0.075000
663IDD02=0.000000
664IDD2N=0.050000
665IDD2N2=0.000000
666IDD2P0=0.000000
667IDD2P02=0.000000
668IDD2P1=0.000000
669IDD2P12=0.000000
670IDD3N=0.057000
671IDD3N2=0.000000
672IDD3P0=0.000000
673IDD3P02=0.000000
674IDD3P1=0.000000
675IDD3P12=0.000000
676IDD4R=0.187000
677IDD4R2=0.000000
678IDD4W=0.165000
679IDD4W2=0.000000
680IDD5=0.220000
681IDD52=0.000000
682IDD6=0.000000
683IDD62=0.000000
684VDD=1.500000
685VDD2=0.000000
686activation_limit=4
675addr_mapping=RoRaBaChCo
687addr_mapping=RoRaBaCoCh
688bank_groups_per_rank=0
689banks_per_rank=8
690burst_length=8
691channels=1
692clk_domain=system.clk_domain
693conf_table_reported=true
694device_bus_width=8
695device_rowbuffer_size=1024
696device_size=536870912
697devices_per_rank=8
698dll=true
699eventq_index=0
700in_addr_map=true
701max_accesses_per_row=16
702mem_sched_policy=frfcfs
703min_writes_per_switch=16
704null=false
705page_policy=open_adaptive
706range=0:134217727
707ranks_per_channel=2
708read_buffer_size=32
709static_backend_latency=10000
710static_frontend_latency=10000
711tBURST=5000
712tCCD_L=0
713tCK=1250
714tCL=13750
715tCS=2500
716tRAS=35000
717tRCD=13750
718tREFI=7800000
719tRFC=260000
720tRP=13750
721tRRD=6000
722tRRD_L=0
723tRTP=7500
724tRTW=2500
725tWR=15000
726tWTR=7500
727tXAW=30000
728tXP=0
729tXPDLL=0
730tXS=0
731tXSDLL=0
732write_buffer_size=64
733write_high_thresh_perc=85
734write_low_thresh_perc=50
735port=system.membus.master[0]
736
737[system.voltage_domain]
738type=VoltageDomain
739eventq_index=0
740voltage=1.000000
741