19d18
< physmem=system.physmem
29c28
< system_port=system.membus.port[0]
---
> system_port=system.membus.slave[0]
131c130
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
152c151
< mem_side=system.cpu.toL2Bus.port[1]
---
> mem_side=system.cpu.toL2Bus.slave[1]
423c422
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
444c443
< mem_side=system.cpu.toL2Bus.port[0]
---
> mem_side=system.cpu.toL2Bus.slave[0]
455c454
< addr_range=0:18446744073709551615
---
> addr_ranges=0:18446744073709551615
475,476c474,475
< cpu_side=system.cpu.toL2Bus.port[2]
< mem_side=system.membus.port[2]
---
> cpu_side=system.cpu.toL2Bus.master[0]
> mem_side=system.membus.slave[1]
486c485,486
< port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
---
> master=system.cpu.l2cache.cpu_side
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
518c518,519
< port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
---
> master=system.physmem.port[0]
> slave=system.system_port system.cpu.l2cache.mem_side
521c522,523
< type=PhysicalMemory
---
> type=SimpleMemory
> conf_table_reported=false
522a525
> in_addr_map=true
528c531
< port=system.membus.port[1]
---
> port=system.membus.master[0]