Cross Reference: /gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini

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config.ini (9348:44d31345e360)	config.ini (9449:56610ab73040)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775
17mem_mode=atomic	17mem_mode=timing 18mem_ranges=
18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43UnifiedTLB=true 44activity=0 45backComSize=5 46cachePorts=200 47checker=Null 48choiceCtrBits=2 49choicePredictorSize=8192 50clock=500 51commitToDecodeDelay=1 52commitToFetchDelay=1 53commitToIEWDelay=1 54commitToRenameDelay=1 55commitWidth=8 56cpu_id=0 57decodeToFetchDelay=1 58decodeToRenameDelay=1 59decodeWidth=8	19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[0] 31 32[system.cpu] 33type=DerivO3CPU 34children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 35BTBEntries=4096 36BTBTagSize=16 37LFSTSize=1024 38LQEntries=32 39LSQCheckLoads=true 40LSQDepCheckShift=4 41RASSize=16 42SQEntries=32 43SSITSize=1024 44UnifiedTLB=true 45activity=0 46backComSize=5 47cachePorts=200 48checker=Null 49choiceCtrBits=2 50choicePredictorSize=8192 51clock=500 52commitToDecodeDelay=1 53commitToFetchDelay=1 54commitToIEWDelay=1 55commitToRenameDelay=1 56commitWidth=8 57cpu_id=0 58decodeToFetchDelay=1 59decodeToRenameDelay=1 60decodeWidth=8
60defer_registration=false
61dispatchWidth=8 62do_checkpoint_insts=true 63do_quiesce=true 64do_statistics_insts=true 65dtb=system.cpu.dtb 66fetchToDecodeDelay=1 67fetchTrapLatency=1 68fetchWidth=8 69forwardComSize=5 70fuPool=system.cpu.fuPool 71function_trace=false 72function_trace_start=0 73globalCtrBits=2 74globalHistoryBits=13 75globalPredictorSize=8192 76iewToCommitDelay=1 77iewToDecodeDelay=1 78iewToFetchDelay=1 79iewToRenameDelay=1 80instShiftAmt=2 81interrupts=system.cpu.interrupts 82isa=system.cpu.isa 83issueToExecuteDelay=1 84issueWidth=8 85itb=system.cpu.itb 86localCtrBits=2 87localHistoryBits=11 88localHistoryTableSize=2048 89localPredictorSize=2048 90max_insts_all_threads=0 91max_insts_any_thread=0 92max_loads_all_threads=0 93max_loads_any_thread=0 94needsTSO=false 95numIQEntries=64 96numPhysFloatRegs=256 97numPhysIntRegs=256 98numROBEntries=192 99numRobs=1 100numThreads=1 101predType=tournament 102profile=0 103progress_interval=0 104renameToDecodeDelay=1 105renameToFetchDelay=1 106renameToIEWDelay=2 107renameToROBDelay=1 108renameWidth=8 109smtCommitPolicy=RoundRobin 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100 118squashWidth=8 119store_set_clear_period=250000	61dispatchWidth=8 62do_checkpoint_insts=true 63do_quiesce=true 64do_statistics_insts=true 65dtb=system.cpu.dtb 66fetchToDecodeDelay=1 67fetchTrapLatency=1 68fetchWidth=8 69forwardComSize=5 70fuPool=system.cpu.fuPool 71function_trace=false 72function_trace_start=0 73globalCtrBits=2 74globalHistoryBits=13 75globalPredictorSize=8192 76iewToCommitDelay=1 77iewToDecodeDelay=1 78iewToFetchDelay=1 79iewToRenameDelay=1 80instShiftAmt=2 81interrupts=system.cpu.interrupts 82isa=system.cpu.isa 83issueToExecuteDelay=1 84issueWidth=8 85itb=system.cpu.itb 86localCtrBits=2 87localHistoryBits=11 88localHistoryTableSize=2048 89localPredictorSize=2048 90max_insts_all_threads=0 91max_insts_any_thread=0 92max_loads_all_threads=0 93max_loads_any_thread=0 94needsTSO=false 95numIQEntries=64 96numPhysFloatRegs=256 97numPhysIntRegs=256 98numROBEntries=192 99numRobs=1 100numThreads=1 101predType=tournament 102profile=0 103progress_interval=0 104renameToDecodeDelay=1 105renameToFetchDelay=1 106renameToIEWDelay=2 107renameToROBDelay=1 108renameWidth=8 109smtCommitPolicy=RoundRobin 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100 118squashWidth=8 119store_set_clear_period=250000
	120switched_out=false
120system=system 121tracer=system.cpu.tracer 122trapLatency=13 123wbDepth=1 124wbWidth=8 125workload=system.cpu.workload 126dcache_port=system.cpu.dcache.cpu_side 127icache_port=system.cpu.icache.cpu_side 128 129[system.cpu.dcache] 130type=BaseCache 131addr_ranges=0:18446744073709551615 132assoc=2 133block_size=64 134clock=500 135forward_snoops=true	121system=system 122tracer=system.cpu.tracer 123trapLatency=13 124wbDepth=1 125wbWidth=8 126workload=system.cpu.workload 127dcache_port=system.cpu.dcache.cpu_side 128icache_port=system.cpu.icache.cpu_side 129 130[system.cpu.dcache] 131type=BaseCache 132addr_ranges=0:18446744073709551615 133assoc=2 134block_size=64 135clock=500 136forward_snoops=true
136hash_delay=1
137hit_latency=2 138is_top_level=true 139max_miss_count=0 140mshrs=4 141prefetch_on_access=false 142prefetcher=Null	137hit_latency=2 138is_top_level=true 139max_miss_count=0 140mshrs=4 141prefetch_on_access=false 142prefetcher=Null
143prioritizeRequests=false 144repl=Null
145response_latency=2 146size=262144	143response_latency=2 144size=262144
147subblock_size=0
148system=system 149tgts_per_mshr=20	145system=system 146tgts_per_mshr=20
150trace_addr=0
151two_queue=false 152write_buffers=8 153cpu_side=system.cpu.dcache_port 154mem_side=system.cpu.toL2Bus.slave[1] 155 156[system.cpu.dtb] 157type=PowerTLB 158size=64 159 160[system.cpu.fuPool] 161type=FUPool 162children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 163FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 164 165[system.cpu.fuPool.FUList0] 166type=FUDesc 167children=opList 168count=6 169opList=system.cpu.fuPool.FUList0.opList 170 171[system.cpu.fuPool.FUList0.opList] 172type=OpDesc 173issueLat=1 174opClass=IntAlu 175opLat=1 176 177[system.cpu.fuPool.FUList1] 178type=FUDesc 179children=opList0 opList1 180count=2 181opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 182 183[system.cpu.fuPool.FUList1.opList0] 184type=OpDesc 185issueLat=1 186opClass=IntMult 187opLat=3 188 189[system.cpu.fuPool.FUList1.opList1] 190type=OpDesc 191issueLat=19 192opClass=IntDiv 193opLat=20 194 195[system.cpu.fuPool.FUList2] 196type=FUDesc 197children=opList0 opList1 opList2 198count=4 199opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 200 201[system.cpu.fuPool.FUList2.opList0] 202type=OpDesc 203issueLat=1 204opClass=FloatAdd 205opLat=2 206 207[system.cpu.fuPool.FUList2.opList1] 208type=OpDesc 209issueLat=1 210opClass=FloatCmp 211opLat=2 212 213[system.cpu.fuPool.FUList2.opList2] 214type=OpDesc 215issueLat=1 216opClass=FloatCvt 217opLat=2 218 219[system.cpu.fuPool.FUList3] 220type=FUDesc 221children=opList0 opList1 opList2 222count=2 223opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 224 225[system.cpu.fuPool.FUList3.opList0] 226type=OpDesc 227issueLat=1 228opClass=FloatMult 229opLat=4 230 231[system.cpu.fuPool.FUList3.opList1] 232type=OpDesc 233issueLat=12 234opClass=FloatDiv 235opLat=12 236 237[system.cpu.fuPool.FUList3.opList2] 238type=OpDesc 239issueLat=24 240opClass=FloatSqrt 241opLat=24 242 243[system.cpu.fuPool.FUList4] 244type=FUDesc 245children=opList 246count=0 247opList=system.cpu.fuPool.FUList4.opList 248 249[system.cpu.fuPool.FUList4.opList] 250type=OpDesc 251issueLat=1 252opClass=MemRead 253opLat=1 254 255[system.cpu.fuPool.FUList5] 256type=FUDesc 257children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 258count=4 259opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 260 261[system.cpu.fuPool.FUList5.opList00] 262type=OpDesc 263issueLat=1 264opClass=SimdAdd 265opLat=1 266 267[system.cpu.fuPool.FUList5.opList01] 268type=OpDesc 269issueLat=1 270opClass=SimdAddAcc 271opLat=1 272 273[system.cpu.fuPool.FUList5.opList02] 274type=OpDesc 275issueLat=1 276opClass=SimdAlu 277opLat=1 278 279[system.cpu.fuPool.FUList5.opList03] 280type=OpDesc 281issueLat=1 282opClass=SimdCmp 283opLat=1 284 285[system.cpu.fuPool.FUList5.opList04] 286type=OpDesc 287issueLat=1 288opClass=SimdCvt 289opLat=1 290 291[system.cpu.fuPool.FUList5.opList05] 292type=OpDesc 293issueLat=1 294opClass=SimdMisc 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList06] 298type=OpDesc 299issueLat=1 300opClass=SimdMult 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList07] 304type=OpDesc 305issueLat=1 306opClass=SimdMultAcc 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList08] 310type=OpDesc 311issueLat=1 312opClass=SimdShift 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList09] 316type=OpDesc 317issueLat=1 318opClass=SimdShiftAcc 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList10] 322type=OpDesc 323issueLat=1 324opClass=SimdSqrt 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList11] 328type=OpDesc 329issueLat=1 330opClass=SimdFloatAdd 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList12] 334type=OpDesc 335issueLat=1 336opClass=SimdFloatAlu 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList13] 340type=OpDesc 341issueLat=1 342opClass=SimdFloatCmp 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList14] 346type=OpDesc 347issueLat=1 348opClass=SimdFloatCvt 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList15] 352type=OpDesc 353issueLat=1 354opClass=SimdFloatDiv 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList16] 358type=OpDesc 359issueLat=1 360opClass=SimdFloatMisc 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList17] 364type=OpDesc 365issueLat=1 366opClass=SimdFloatMult 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList18] 370type=OpDesc 371issueLat=1 372opClass=SimdFloatMultAcc 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList19] 376type=OpDesc 377issueLat=1 378opClass=SimdFloatSqrt 379opLat=1 380 381[system.cpu.fuPool.FUList6] 382type=FUDesc 383children=opList 384count=0 385opList=system.cpu.fuPool.FUList6.opList 386 387[system.cpu.fuPool.FUList6.opList] 388type=OpDesc 389issueLat=1 390opClass=MemWrite 391opLat=1 392 393[system.cpu.fuPool.FUList7] 394type=FUDesc 395children=opList0 opList1 396count=4 397opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 398 399[system.cpu.fuPool.FUList7.opList0] 400type=OpDesc 401issueLat=1 402opClass=MemRead 403opLat=1 404 405[system.cpu.fuPool.FUList7.opList1] 406type=OpDesc 407issueLat=1 408opClass=MemWrite 409opLat=1 410 411[system.cpu.fuPool.FUList8] 412type=FUDesc 413children=opList 414count=1 415opList=system.cpu.fuPool.FUList8.opList 416 417[system.cpu.fuPool.FUList8.opList] 418type=OpDesc 419issueLat=3 420opClass=IprAccess 421opLat=3 422 423[system.cpu.icache] 424type=BaseCache 425addr_ranges=0:18446744073709551615 426assoc=2 427block_size=64 428clock=500 429forward_snoops=true	147two_queue=false 148write_buffers=8 149cpu_side=system.cpu.dcache_port 150mem_side=system.cpu.toL2Bus.slave[1] 151 152[system.cpu.dtb] 153type=PowerTLB 154size=64 155 156[system.cpu.fuPool] 157type=FUPool 158children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 159FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 160 161[system.cpu.fuPool.FUList0] 162type=FUDesc 163children=opList 164count=6 165opList=system.cpu.fuPool.FUList0.opList 166 167[system.cpu.fuPool.FUList0.opList] 168type=OpDesc 169issueLat=1 170opClass=IntAlu 171opLat=1 172 173[system.cpu.fuPool.FUList1] 174type=FUDesc 175children=opList0 opList1 176count=2 177opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 178 179[system.cpu.fuPool.FUList1.opList0] 180type=OpDesc 181issueLat=1 182opClass=IntMult 183opLat=3 184 185[system.cpu.fuPool.FUList1.opList1] 186type=OpDesc 187issueLat=19 188opClass=IntDiv 189opLat=20 190 191[system.cpu.fuPool.FUList2] 192type=FUDesc 193children=opList0 opList1 opList2 194count=4 195opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 196 197[system.cpu.fuPool.FUList2.opList0] 198type=OpDesc 199issueLat=1 200opClass=FloatAdd 201opLat=2 202 203[system.cpu.fuPool.FUList2.opList1] 204type=OpDesc 205issueLat=1 206opClass=FloatCmp 207opLat=2 208 209[system.cpu.fuPool.FUList2.opList2] 210type=OpDesc 211issueLat=1 212opClass=FloatCvt 213opLat=2 214 215[system.cpu.fuPool.FUList3] 216type=FUDesc 217children=opList0 opList1 opList2 218count=2 219opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 220 221[system.cpu.fuPool.FUList3.opList0] 222type=OpDesc 223issueLat=1 224opClass=FloatMult 225opLat=4 226 227[system.cpu.fuPool.FUList3.opList1] 228type=OpDesc 229issueLat=12 230opClass=FloatDiv 231opLat=12 232 233[system.cpu.fuPool.FUList3.opList2] 234type=OpDesc 235issueLat=24 236opClass=FloatSqrt 237opLat=24 238 239[system.cpu.fuPool.FUList4] 240type=FUDesc 241children=opList 242count=0 243opList=system.cpu.fuPool.FUList4.opList 244 245[system.cpu.fuPool.FUList4.opList] 246type=OpDesc 247issueLat=1 248opClass=MemRead 249opLat=1 250 251[system.cpu.fuPool.FUList5] 252type=FUDesc 253children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 254count=4 255opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 256 257[system.cpu.fuPool.FUList5.opList00] 258type=OpDesc 259issueLat=1 260opClass=SimdAdd 261opLat=1 262 263[system.cpu.fuPool.FUList5.opList01] 264type=OpDesc 265issueLat=1 266opClass=SimdAddAcc 267opLat=1 268 269[system.cpu.fuPool.FUList5.opList02] 270type=OpDesc 271issueLat=1 272opClass=SimdAlu 273opLat=1 274 275[system.cpu.fuPool.FUList5.opList03] 276type=OpDesc 277issueLat=1 278opClass=SimdCmp 279opLat=1 280 281[system.cpu.fuPool.FUList5.opList04] 282type=OpDesc 283issueLat=1 284opClass=SimdCvt 285opLat=1 286 287[system.cpu.fuPool.FUList5.opList05] 288type=OpDesc 289issueLat=1 290opClass=SimdMisc 291opLat=1 292 293[system.cpu.fuPool.FUList5.opList06] 294type=OpDesc 295issueLat=1 296opClass=SimdMult 297opLat=1 298 299[system.cpu.fuPool.FUList5.opList07] 300type=OpDesc 301issueLat=1 302opClass=SimdMultAcc 303opLat=1 304 305[system.cpu.fuPool.FUList5.opList08] 306type=OpDesc 307issueLat=1 308opClass=SimdShift 309opLat=1 310 311[system.cpu.fuPool.FUList5.opList09] 312type=OpDesc 313issueLat=1 314opClass=SimdShiftAcc 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList10] 318type=OpDesc 319issueLat=1 320opClass=SimdSqrt 321opLat=1 322 323[system.cpu.fuPool.FUList5.opList11] 324type=OpDesc 325issueLat=1 326opClass=SimdFloatAdd 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList12] 330type=OpDesc 331issueLat=1 332opClass=SimdFloatAlu 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList13] 336type=OpDesc 337issueLat=1 338opClass=SimdFloatCmp 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList14] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatCvt 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList15] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatDiv 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList16] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatMisc 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList17] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatMult 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList18] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatMultAcc 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList19] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatSqrt 375opLat=1 376 377[system.cpu.fuPool.FUList6] 378type=FUDesc 379children=opList 380count=0 381opList=system.cpu.fuPool.FUList6.opList 382 383[system.cpu.fuPool.FUList6.opList] 384type=OpDesc 385issueLat=1 386opClass=MemWrite 387opLat=1 388 389[system.cpu.fuPool.FUList7] 390type=FUDesc 391children=opList0 opList1 392count=4 393opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 394 395[system.cpu.fuPool.FUList7.opList0] 396type=OpDesc 397issueLat=1 398opClass=MemRead 399opLat=1 400 401[system.cpu.fuPool.FUList7.opList1] 402type=OpDesc 403issueLat=1 404opClass=MemWrite 405opLat=1 406 407[system.cpu.fuPool.FUList8] 408type=FUDesc 409children=opList 410count=1 411opList=system.cpu.fuPool.FUList8.opList 412 413[system.cpu.fuPool.FUList8.opList] 414type=OpDesc 415issueLat=3 416opClass=IprAccess 417opLat=3 418 419[system.cpu.icache] 420type=BaseCache 421addr_ranges=0:18446744073709551615 422assoc=2 423block_size=64 424clock=500 425forward_snoops=true
430hash_delay=1
431hit_latency=2 432is_top_level=true 433max_miss_count=0 434mshrs=4 435prefetch_on_access=false 436prefetcher=Null	426hit_latency=2 427is_top_level=true 428max_miss_count=0 429mshrs=4 430prefetch_on_access=false 431prefetcher=Null
437prioritizeRequests=false 438repl=Null
439response_latency=2 440size=131072	432response_latency=2 433size=131072
441subblock_size=0
442system=system 443tgts_per_mshr=20	434system=system 435tgts_per_mshr=20
444trace_addr=0
445two_queue=false 446write_buffers=8 447cpu_side=system.cpu.icache_port 448mem_side=system.cpu.toL2Bus.slave[0] 449 450[system.cpu.interrupts] 451type=PowerInterrupts 452 453[system.cpu.isa] 454type=PowerISA 455 456[system.cpu.itb] 457type=PowerTLB 458size=64 459 460[system.cpu.l2cache] 461type=BaseCache 462addr_ranges=0:18446744073709551615 463assoc=8 464block_size=64 465clock=500 466forward_snoops=true	436two_queue=false 437write_buffers=8 438cpu_side=system.cpu.icache_port 439mem_side=system.cpu.toL2Bus.slave[0] 440 441[system.cpu.interrupts] 442type=PowerInterrupts 443 444[system.cpu.isa] 445type=PowerISA 446 447[system.cpu.itb] 448type=PowerTLB 449size=64 450 451[system.cpu.l2cache] 452type=BaseCache 453addr_ranges=0:18446744073709551615 454assoc=8 455block_size=64 456clock=500 457forward_snoops=true
467hash_delay=1
468hit_latency=20 469is_top_level=false 470max_miss_count=0 471mshrs=20 472prefetch_on_access=false 473prefetcher=Null	458hit_latency=20 459is_top_level=false 460max_miss_count=0 461mshrs=20 462prefetch_on_access=false 463prefetcher=Null
474prioritizeRequests=false 475repl=Null
476response_latency=20 477size=2097152	464response_latency=20 465size=2097152
478subblock_size=0
479system=system 480tgts_per_mshr=12	466system=system 467tgts_per_mshr=12
481trace_addr=0
482two_queue=false 483write_buffers=8 484cpu_side=system.cpu.toL2Bus.master[0] 485mem_side=system.membus.slave[1] 486 487[system.cpu.toL2Bus] 488type=CoherentBus 489block_size=64 490clock=500 491header_cycles=1 492use_default_range=false 493width=32 494master=system.cpu.l2cache.cpu_side 495slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 496 497[system.cpu.tracer] 498type=ExeTracer 499 500[system.cpu.workload] 501type=LiveProcess 502cmd=hello 503cwd= 504egid=100 505env= 506errout=cerr 507euid=100	468two_queue=false 469write_buffers=8 470cpu_side=system.cpu.toL2Bus.master[0] 471mem_side=system.membus.slave[1] 472 473[system.cpu.toL2Bus] 474type=CoherentBus 475block_size=64 476clock=500 477header_cycles=1 478use_default_range=false 479width=32 480master=system.cpu.l2cache.cpu_side 481slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 482 483[system.cpu.tracer] 484type=ExeTracer 485 486[system.cpu.workload] 487type=LiveProcess 488cmd=hello 489cwd= 490egid=100 491env= 492errout=cerr 493euid=100
508executable=/projects/pd/randd/dist/test-progs/hello/bin/power/linux/hello	494executable=/gem5/dist/test-progs/hello/bin/power/linux/hello
509gid=100 510input=cin 511max_stack_size=67108864 512output=cout 513pid=100 514ppid=99 515simpoint=0 516system=system 517uid=100 518 519[system.membus] 520type=CoherentBus 521block_size=64 522clock=1000 523header_cycles=1 524use_default_range=false 525width=8 526master=system.physmem.port 527slave=system.system_port system.cpu.l2cache.mem_side 528 529[system.physmem] 530type=SimpleDRAM 531addr_mapping=openmap 532banks_per_rank=8 533clock=1000 534conf_table_reported=false 535in_addr_map=true 536lines_per_rowbuffer=64 537mem_sched_policy=fcfs 538null=false 539page_policy=open 540range=0:134217727 541ranks_per_channel=2 542read_buffer_size=32 543tBURST=4000 544tCL=14000 545tRCD=14000 546tREFI=7800000 547tRFC=300000 548tRP=14000 549tWTR=1000 550write_buffer_size=32 551write_thresh_perc=70 552zero=false 553port=system.membus.master[0] 554	495gid=100 496input=cin 497max_stack_size=67108864 498output=cout 499pid=100 500ppid=99 501simpoint=0 502system=system 503uid=100 504 505[system.membus] 506type=CoherentBus 507block_size=64 508clock=1000 509header_cycles=1 510use_default_range=false 511width=8 512master=system.physmem.port 513slave=system.system_port system.cpu.l2cache.mem_side 514 515[system.physmem] 516type=SimpleDRAM 517addr_mapping=openmap 518banks_per_rank=8 519clock=1000 520conf_table_reported=false 521in_addr_map=true 522lines_per_rowbuffer=64 523mem_sched_policy=fcfs 524null=false 525page_policy=open 526range=0:134217727 527ranks_per_channel=2 528read_buffer_size=32 529tBURST=4000 530tCL=14000 531tRCD=14000 532tREFI=7800000 533tRFC=300000 534tRP=14000 535tWTR=1000 536write_buffer_size=32 537write_thresh_perc=70 538zero=false 539port=system.membus.master[0] 540