Cross Reference: /gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini

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config.ini (8835:7c68f84d7c4e)	config.ini (8983:8800b05e1cb3)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16
19physmem=system.physmem
20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1	19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1
29system_port=system.membus.port[0]	28system_port=system.membus.slave[0]
30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43UnifiedTLB=true 44activity=0 45backComSize=5 46cachePorts=200 47checker=Null 48choiceCtrBits=2 49choicePredictorSize=8192 50clock=500 51commitToDecodeDelay=1 52commitToFetchDelay=1 53commitToIEWDelay=1 54commitToRenameDelay=1 55commitWidth=8 56cpu_id=0 57decodeToFetchDelay=1 58decodeToRenameDelay=1 59decodeWidth=8 60defer_registration=false 61dispatchWidth=8 62do_checkpoint_insts=true 63do_quiesce=true 64do_statistics_insts=true 65dtb=system.cpu.dtb 66fetchToDecodeDelay=1 67fetchTrapLatency=1 68fetchWidth=8 69forwardComSize=5 70fuPool=system.cpu.fuPool 71function_trace=false 72function_trace_start=0 73globalCtrBits=2 74globalHistoryBits=13 75globalPredictorSize=8192 76iewToCommitDelay=1 77iewToDecodeDelay=1 78iewToFetchDelay=1 79iewToRenameDelay=1 80instShiftAmt=2 81interrupts=system.cpu.interrupts 82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100phase=0 101predType=tournament 102profile=0 103progress_interval=0 104renameToDecodeDelay=1 105renameToFetchDelay=1 106renameToIEWDelay=2 107renameToROBDelay=1 108renameWidth=8 109smtCommitPolicy=RoundRobin 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100 118squashWidth=8 119store_set_clear_period=250000 120system=system 121tracer=system.cpu.tracer 122trapLatency=13 123wbDepth=1 124wbWidth=8 125workload=system.cpu.workload 126dcache_port=system.cpu.dcache.cpu_side 127icache_port=system.cpu.icache.cpu_side 128 129[system.cpu.dcache] 130type=BaseCache	29 30[system.cpu] 31type=DerivO3CPU 32children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 33BTBEntries=4096 34BTBTagSize=16 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39RASSize=16 40SQEntries=32 41SSITSize=1024 42UnifiedTLB=true 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99phase=0 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache
131addr_range=0:18446744073709551615	130addr_ranges=0:18446744073709551615
132assoc=2 133block_size=64 134forward_snoops=true 135hash_delay=1 136is_top_level=true 137latency=1000 138max_miss_count=0 139mshrs=10 140prefetch_on_access=false 141prefetcher=Null 142prioritizeRequests=false 143repl=Null 144size=262144 145subblock_size=0 146system=system 147tgts_per_mshr=20 148trace_addr=0 149two_queue=false 150write_buffers=8 151cpu_side=system.cpu.dcache_port	131assoc=2 132block_size=64 133forward_snoops=true 134hash_delay=1 135is_top_level=true 136latency=1000 137max_miss_count=0 138mshrs=10 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null 143size=262144 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu.dcache_port
152mem_side=system.cpu.toL2Bus.port[1]	151mem_side=system.cpu.toL2Bus.slave[1]
153 154[system.cpu.dtb] 155type=PowerTLB 156size=64 157 158[system.cpu.fuPool] 159type=FUPool 160children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 161FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 162 163[system.cpu.fuPool.FUList0] 164type=FUDesc 165children=opList 166count=6 167opList=system.cpu.fuPool.FUList0.opList 168 169[system.cpu.fuPool.FUList0.opList] 170type=OpDesc 171issueLat=1 172opClass=IntAlu 173opLat=1 174 175[system.cpu.fuPool.FUList1] 176type=FUDesc 177children=opList0 opList1 178count=2 179opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 180 181[system.cpu.fuPool.FUList1.opList0] 182type=OpDesc 183issueLat=1 184opClass=IntMult 185opLat=3 186 187[system.cpu.fuPool.FUList1.opList1] 188type=OpDesc 189issueLat=19 190opClass=IntDiv 191opLat=20 192 193[system.cpu.fuPool.FUList2] 194type=FUDesc 195children=opList0 opList1 opList2 196count=4 197opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 198 199[system.cpu.fuPool.FUList2.opList0] 200type=OpDesc 201issueLat=1 202opClass=FloatAdd 203opLat=2 204 205[system.cpu.fuPool.FUList2.opList1] 206type=OpDesc 207issueLat=1 208opClass=FloatCmp 209opLat=2 210 211[system.cpu.fuPool.FUList2.opList2] 212type=OpDesc 213issueLat=1 214opClass=FloatCvt 215opLat=2 216 217[system.cpu.fuPool.FUList3] 218type=FUDesc 219children=opList0 opList1 opList2 220count=2 221opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 222 223[system.cpu.fuPool.FUList3.opList0] 224type=OpDesc 225issueLat=1 226opClass=FloatMult 227opLat=4 228 229[system.cpu.fuPool.FUList3.opList1] 230type=OpDesc 231issueLat=12 232opClass=FloatDiv 233opLat=12 234 235[system.cpu.fuPool.FUList3.opList2] 236type=OpDesc 237issueLat=24 238opClass=FloatSqrt 239opLat=24 240 241[system.cpu.fuPool.FUList4] 242type=FUDesc 243children=opList 244count=0 245opList=system.cpu.fuPool.FUList4.opList 246 247[system.cpu.fuPool.FUList4.opList] 248type=OpDesc 249issueLat=1 250opClass=MemRead 251opLat=1 252 253[system.cpu.fuPool.FUList5] 254type=FUDesc 255children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 256count=4 257opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 258 259[system.cpu.fuPool.FUList5.opList00] 260type=OpDesc 261issueLat=1 262opClass=SimdAdd 263opLat=1 264 265[system.cpu.fuPool.FUList5.opList01] 266type=OpDesc 267issueLat=1 268opClass=SimdAddAcc 269opLat=1 270 271[system.cpu.fuPool.FUList5.opList02] 272type=OpDesc 273issueLat=1 274opClass=SimdAlu 275opLat=1 276 277[system.cpu.fuPool.FUList5.opList03] 278type=OpDesc 279issueLat=1 280opClass=SimdCmp 281opLat=1 282 283[system.cpu.fuPool.FUList5.opList04] 284type=OpDesc 285issueLat=1 286opClass=SimdCvt 287opLat=1 288 289[system.cpu.fuPool.FUList5.opList05] 290type=OpDesc 291issueLat=1 292opClass=SimdMisc 293opLat=1 294 295[system.cpu.fuPool.FUList5.opList06] 296type=OpDesc 297issueLat=1 298opClass=SimdMult 299opLat=1 300 301[system.cpu.fuPool.FUList5.opList07] 302type=OpDesc 303issueLat=1 304opClass=SimdMultAcc 305opLat=1 306 307[system.cpu.fuPool.FUList5.opList08] 308type=OpDesc 309issueLat=1 310opClass=SimdShift 311opLat=1 312 313[system.cpu.fuPool.FUList5.opList09] 314type=OpDesc 315issueLat=1 316opClass=SimdShiftAcc 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList10] 320type=OpDesc 321issueLat=1 322opClass=SimdSqrt 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList11] 326type=OpDesc 327issueLat=1 328opClass=SimdFloatAdd 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList12] 332type=OpDesc 333issueLat=1 334opClass=SimdFloatAlu 335opLat=1 336 337[system.cpu.fuPool.FUList5.opList13] 338type=OpDesc 339issueLat=1 340opClass=SimdFloatCmp 341opLat=1 342 343[system.cpu.fuPool.FUList5.opList14] 344type=OpDesc 345issueLat=1 346opClass=SimdFloatCvt 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList15] 350type=OpDesc 351issueLat=1 352opClass=SimdFloatDiv 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList16] 356type=OpDesc 357issueLat=1 358opClass=SimdFloatMisc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList17] 362type=OpDesc 363issueLat=1 364opClass=SimdFloatMult 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList18] 368type=OpDesc 369issueLat=1 370opClass=SimdFloatMultAcc 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList19] 374type=OpDesc 375issueLat=1 376opClass=SimdFloatSqrt 377opLat=1 378 379[system.cpu.fuPool.FUList6] 380type=FUDesc 381children=opList 382count=0 383opList=system.cpu.fuPool.FUList6.opList 384 385[system.cpu.fuPool.FUList6.opList] 386type=OpDesc 387issueLat=1 388opClass=MemWrite 389opLat=1 390 391[system.cpu.fuPool.FUList7] 392type=FUDesc 393children=opList0 opList1 394count=4 395opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 396 397[system.cpu.fuPool.FUList7.opList0] 398type=OpDesc 399issueLat=1 400opClass=MemRead 401opLat=1 402 403[system.cpu.fuPool.FUList7.opList1] 404type=OpDesc 405issueLat=1 406opClass=MemWrite 407opLat=1 408 409[system.cpu.fuPool.FUList8] 410type=FUDesc 411children=opList 412count=1 413opList=system.cpu.fuPool.FUList8.opList 414 415[system.cpu.fuPool.FUList8.opList] 416type=OpDesc 417issueLat=3 418opClass=IprAccess 419opLat=3 420 421[system.cpu.icache] 422type=BaseCache	152 153[system.cpu.dtb] 154type=PowerTLB 155size=64 156 157[system.cpu.fuPool] 158type=FUPool 159children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 160FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 161 162[system.cpu.fuPool.FUList0] 163type=FUDesc 164children=opList 165count=6 166opList=system.cpu.fuPool.FUList0.opList 167 168[system.cpu.fuPool.FUList0.opList] 169type=OpDesc 170issueLat=1 171opClass=IntAlu 172opLat=1 173 174[system.cpu.fuPool.FUList1] 175type=FUDesc 176children=opList0 opList1 177count=2 178opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 179 180[system.cpu.fuPool.FUList1.opList0] 181type=OpDesc 182issueLat=1 183opClass=IntMult 184opLat=3 185 186[system.cpu.fuPool.FUList1.opList1] 187type=OpDesc 188issueLat=19 189opClass=IntDiv 190opLat=20 191 192[system.cpu.fuPool.FUList2] 193type=FUDesc 194children=opList0 opList1 opList2 195count=4 196opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 197 198[system.cpu.fuPool.FUList2.opList0] 199type=OpDesc 200issueLat=1 201opClass=FloatAdd 202opLat=2 203 204[system.cpu.fuPool.FUList2.opList1] 205type=OpDesc 206issueLat=1 207opClass=FloatCmp 208opLat=2 209 210[system.cpu.fuPool.FUList2.opList2] 211type=OpDesc 212issueLat=1 213opClass=FloatCvt 214opLat=2 215 216[system.cpu.fuPool.FUList3] 217type=FUDesc 218children=opList0 opList1 opList2 219count=2 220opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 221 222[system.cpu.fuPool.FUList3.opList0] 223type=OpDesc 224issueLat=1 225opClass=FloatMult 226opLat=4 227 228[system.cpu.fuPool.FUList3.opList1] 229type=OpDesc 230issueLat=12 231opClass=FloatDiv 232opLat=12 233 234[system.cpu.fuPool.FUList3.opList2] 235type=OpDesc 236issueLat=24 237opClass=FloatSqrt 238opLat=24 239 240[system.cpu.fuPool.FUList4] 241type=FUDesc 242children=opList 243count=0 244opList=system.cpu.fuPool.FUList4.opList 245 246[system.cpu.fuPool.FUList4.opList] 247type=OpDesc 248issueLat=1 249opClass=MemRead 250opLat=1 251 252[system.cpu.fuPool.FUList5] 253type=FUDesc 254children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 255count=4 256opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 257 258[system.cpu.fuPool.FUList5.opList00] 259type=OpDesc 260issueLat=1 261opClass=SimdAdd 262opLat=1 263 264[system.cpu.fuPool.FUList5.opList01] 265type=OpDesc 266issueLat=1 267opClass=SimdAddAcc 268opLat=1 269 270[system.cpu.fuPool.FUList5.opList02] 271type=OpDesc 272issueLat=1 273opClass=SimdAlu 274opLat=1 275 276[system.cpu.fuPool.FUList5.opList03] 277type=OpDesc 278issueLat=1 279opClass=SimdCmp 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList04] 283type=OpDesc 284issueLat=1 285opClass=SimdCvt 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList05] 289type=OpDesc 290issueLat=1 291opClass=SimdMisc 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList06] 295type=OpDesc 296issueLat=1 297opClass=SimdMult 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList07] 301type=OpDesc 302issueLat=1 303opClass=SimdMultAcc 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList08] 307type=OpDesc 308issueLat=1 309opClass=SimdShift 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList09] 313type=OpDesc 314issueLat=1 315opClass=SimdShiftAcc 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList10] 319type=OpDesc 320issueLat=1 321opClass=SimdSqrt 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList11] 325type=OpDesc 326issueLat=1 327opClass=SimdFloatAdd 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList12] 331type=OpDesc 332issueLat=1 333opClass=SimdFloatAlu 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList13] 337type=OpDesc 338issueLat=1 339opClass=SimdFloatCmp 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList14] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatCvt 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList15] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatDiv 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList16] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatMisc 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList17] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatMult 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList18] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatMultAcc 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList19] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatSqrt 376opLat=1 377 378[system.cpu.fuPool.FUList6] 379type=FUDesc 380children=opList 381count=0 382opList=system.cpu.fuPool.FUList6.opList 383 384[system.cpu.fuPool.FUList6.opList] 385type=OpDesc 386issueLat=1 387opClass=MemWrite 388opLat=1 389 390[system.cpu.fuPool.FUList7] 391type=FUDesc 392children=opList0 opList1 393count=4 394opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 395 396[system.cpu.fuPool.FUList7.opList0] 397type=OpDesc 398issueLat=1 399opClass=MemRead 400opLat=1 401 402[system.cpu.fuPool.FUList7.opList1] 403type=OpDesc 404issueLat=1 405opClass=MemWrite 406opLat=1 407 408[system.cpu.fuPool.FUList8] 409type=FUDesc 410children=opList 411count=1 412opList=system.cpu.fuPool.FUList8.opList 413 414[system.cpu.fuPool.FUList8.opList] 415type=OpDesc 416issueLat=3 417opClass=IprAccess 418opLat=3 419 420[system.cpu.icache] 421type=BaseCache
423addr_range=0:18446744073709551615	422addr_ranges=0:18446744073709551615
424assoc=2 425block_size=64 426forward_snoops=true 427hash_delay=1 428is_top_level=true 429latency=1000 430max_miss_count=0 431mshrs=10 432prefetch_on_access=false 433prefetcher=Null 434prioritizeRequests=false 435repl=Null 436size=131072 437subblock_size=0 438system=system 439tgts_per_mshr=20 440trace_addr=0 441two_queue=false 442write_buffers=8 443cpu_side=system.cpu.icache_port	423assoc=2 424block_size=64 425forward_snoops=true 426hash_delay=1 427is_top_level=true 428latency=1000 429max_miss_count=0 430mshrs=10 431prefetch_on_access=false 432prefetcher=Null 433prioritizeRequests=false 434repl=Null 435size=131072 436subblock_size=0 437system=system 438tgts_per_mshr=20 439trace_addr=0 440two_queue=false 441write_buffers=8 442cpu_side=system.cpu.icache_port
444mem_side=system.cpu.toL2Bus.port[0]	443mem_side=system.cpu.toL2Bus.slave[0]
445 446[system.cpu.interrupts] 447type=PowerInterrupts 448 449[system.cpu.itb] 450type=PowerTLB 451size=64 452 453[system.cpu.l2cache] 454type=BaseCache	444 445[system.cpu.interrupts] 446type=PowerInterrupts 447 448[system.cpu.itb] 449type=PowerTLB 450size=64 451 452[system.cpu.l2cache] 453type=BaseCache
455addr_range=0:18446744073709551615	454addr_ranges=0:18446744073709551615
456assoc=2 457block_size=64 458forward_snoops=true 459hash_delay=1 460is_top_level=false 461latency=1000 462max_miss_count=0 463mshrs=10 464prefetch_on_access=false 465prefetcher=Null 466prioritizeRequests=false 467repl=Null 468size=2097152 469subblock_size=0 470system=system 471tgts_per_mshr=5 472trace_addr=0 473two_queue=false 474write_buffers=8	455assoc=2 456block_size=64 457forward_snoops=true 458hash_delay=1 459is_top_level=false 460latency=1000 461max_miss_count=0 462mshrs=10 463prefetch_on_access=false 464prefetcher=Null 465prioritizeRequests=false 466repl=Null 467size=2097152 468subblock_size=0 469system=system 470tgts_per_mshr=5 471trace_addr=0 472two_queue=false 473write_buffers=8
475cpu_side=system.cpu.toL2Bus.port[2] 476mem_side=system.membus.port[2]	474cpu_side=system.cpu.toL2Bus.master[0] 475mem_side=system.membus.slave[1]
477 478[system.cpu.toL2Bus] 479type=Bus 480block_size=64 481bus_id=0 482clock=1000 483header_cycles=1 484use_default_range=false 485width=64	476 477[system.cpu.toL2Bus] 478type=Bus 479block_size=64 480bus_id=0 481clock=1000 482header_cycles=1 483use_default_range=false 484width=64
486port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side	485master=system.cpu.l2cache.cpu_side 486slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
487 488[system.cpu.tracer] 489type=ExeTracer 490 491[system.cpu.workload] 492type=LiveProcess 493cmd=hello 494cwd= 495egid=100 496env= 497errout=cerr 498euid=100 499executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello 500gid=100 501input=cin 502max_stack_size=67108864 503output=cout 504pid=100 505ppid=99 506simpoint=0 507system=system 508uid=100 509 510[system.membus] 511type=Bus 512block_size=64 513bus_id=0 514clock=1000 515header_cycles=1 516use_default_range=false 517width=64	487 488[system.cpu.tracer] 489type=ExeTracer 490 491[system.cpu.workload] 492type=LiveProcess 493cmd=hello 494cwd= 495egid=100 496env= 497errout=cerr 498euid=100 499executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello 500gid=100 501input=cin 502max_stack_size=67108864 503output=cout 504pid=100 505ppid=99 506simpoint=0 507system=system 508uid=100 509 510[system.membus] 511type=Bus 512block_size=64 513bus_id=0 514clock=1000 515header_cycles=1 516use_default_range=false 517width=64
518port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side	518master=system.physmem.port[0] 519slave=system.system_port system.cpu.l2cache.mem_side
519 520[system.physmem]	520 521[system.physmem]
521type=PhysicalMemory	522type=SimpleMemory 523conf_table_reported=false
522file=	524file=
	525in_addr_map=true
523latency=30000 524latency_var=0 525null=false 526range=0:134217727 527zero=false	526latency=30000 527latency_var=0 528null=false 529range=0:134217727 530zero=false
528port=system.membus.port[1]	531port=system.membus.master[0]
529	532