Cross Reference: /gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini

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config.ini (10451:3a87241adfb8)	config.ini (10736:4433fb00fa7d)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem
	26mmap_using_noreserve=false
26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55UnifiedTLB=true 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchQueueSize=32 79fetchToDecodeDelay=1 80fetchTrapLatency=1 81fetchWidth=8 82forwardComSize=5 83fuPool=system.cpu.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu.interrupts 91isa=system.cpu.isa 92issueToExecuteDelay=1 93issueWidth=8 94itb=system.cpu.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99needsTSO=false 100numIQEntries=64 101numPhysCCRegs=0 102numPhysFloatRegs=256 103numPhysIntRegs=256 104numROBEntries=192 105numRobs=1 106numThreads=1 107profile=0 108progress_interval=0 109renameToDecodeDelay=1 110renameToFetchDelay=1 111renameToIEWDelay=2 112renameToROBDelay=1 113renameWidth=8 114simpoint_start_insts= 115smtCommitPolicy=RoundRobin 116smtFetchPolicy=SingleThread 117smtIQPolicy=Partitioned 118smtIQThreshold=100 119smtLSQPolicy=Partitioned 120smtLSQThreshold=100 121smtNumFetchingThreads=1 122smtROBPolicy=Partitioned 123smtROBThreshold=100 124socket_id=0 125squashWidth=8 126store_set_clear_period=250000 127switched_out=false 128system=system 129tracer=system.cpu.tracer 130trapLatency=13 131wbWidth=8 132workload=system.cpu.workload 133dcache_port=system.cpu.dcache.cpu_side 134icache_port=system.cpu.icache.cpu_side 135 136[system.cpu.branchPred] 137type=BranchPredictor 138BTBEntries=4096 139BTBTagSize=16 140RASSize=16 141choiceCtrBits=2 142choicePredictorSize=8192 143eventq_index=0 144globalCtrBits=2 145globalPredictorSize=8192 146instShiftAmt=2 147localCtrBits=2 148localHistoryTableSize=2048 149localPredictorSize=2048 150numThreads=1 151predType=tournament 152 153[system.cpu.dcache] 154type=BaseCache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain	27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56UnifiedTLB=true 57activity=0 58backComSize=5 59branchPred=system.cpu.branchPred 60cachePorts=200 61checker=Null 62clk_domain=system.cpu_clk_domain 63commitToDecodeDelay=1 64commitToFetchDelay=1 65commitToIEWDelay=1 66commitToRenameDelay=1 67commitWidth=8 68cpu_id=0 69decodeToFetchDelay=1 70decodeToRenameDelay=1 71decodeWidth=8 72dispatchWidth=8 73do_checkpoint_insts=true 74do_quiesce=true 75do_statistics_insts=true 76dtb=system.cpu.dtb 77eventq_index=0 78fetchBufferSize=64 79fetchQueueSize=32 80fetchToDecodeDelay=1 81fetchTrapLatency=1 82fetchWidth=8 83forwardComSize=5 84fuPool=system.cpu.fuPool 85function_trace=false 86function_trace_start=0 87iewToCommitDelay=1 88iewToDecodeDelay=1 89iewToFetchDelay=1 90iewToRenameDelay=1 91interrupts=system.cpu.interrupts 92isa=system.cpu.isa 93issueToExecuteDelay=1 94issueWidth=8 95itb=system.cpu.itb 96max_insts_all_threads=0 97max_insts_any_thread=0 98max_loads_all_threads=0 99max_loads_any_thread=0 100needsTSO=false 101numIQEntries=64 102numPhysCCRegs=0 103numPhysFloatRegs=256 104numPhysIntRegs=256 105numROBEntries=192 106numRobs=1 107numThreads=1 108profile=0 109progress_interval=0 110renameToDecodeDelay=1 111renameToFetchDelay=1 112renameToIEWDelay=2 113renameToROBDelay=1 114renameWidth=8 115simpoint_start_insts= 116smtCommitPolicy=RoundRobin 117smtFetchPolicy=SingleThread 118smtIQPolicy=Partitioned 119smtIQThreshold=100 120smtLSQPolicy=Partitioned 121smtLSQThreshold=100 122smtNumFetchingThreads=1 123smtROBPolicy=Partitioned 124smtROBThreshold=100 125socket_id=0 126squashWidth=8 127store_set_clear_period=250000 128switched_out=false 129system=system 130tracer=system.cpu.tracer 131trapLatency=13 132wbWidth=8 133workload=system.cpu.workload 134dcache_port=system.cpu.dcache.cpu_side 135icache_port=system.cpu.icache.cpu_side 136 137[system.cpu.branchPred] 138type=BranchPredictor 139BTBEntries=4096 140BTBTagSize=16 141RASSize=16 142choiceCtrBits=2 143choicePredictorSize=8192 144eventq_index=0 145globalCtrBits=2 146globalPredictorSize=8192 147instShiftAmt=2 148localCtrBits=2 149localHistoryTableSize=2048 150localPredictorSize=2048 151numThreads=1 152predType=tournament 153 154[system.cpu.dcache] 155type=BaseCache 156children=tags 157addr_ranges=0:18446744073709551615 158assoc=2 159clk_domain=system.cpu_clk_domain
	160demand_mshr_reserve=1
159eventq_index=0 160forward_snoops=true 161hit_latency=2 162is_top_level=true 163max_miss_count=0 164mshrs=4 165prefetch_on_access=false 166prefetcher=Null 167response_latency=2 168sequential_access=false 169size=262144 170system=system 171tags=system.cpu.dcache.tags 172tgts_per_mshr=20 173two_queue=false 174write_buffers=8 175cpu_side=system.cpu.dcache_port 176mem_side=system.cpu.toL2Bus.slave[1] 177 178[system.cpu.dcache.tags] 179type=LRU 180assoc=2 181block_size=64 182clk_domain=system.cpu_clk_domain 183eventq_index=0 184hit_latency=2 185sequential_access=false 186size=262144 187 188[system.cpu.dtb] 189type=PowerTLB 190eventq_index=0 191size=64 192 193[system.cpu.fuPool] 194type=FUPool 195children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 196FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 197eventq_index=0 198 199[system.cpu.fuPool.FUList0] 200type=FUDesc 201children=opList 202count=6 203eventq_index=0 204opList=system.cpu.fuPool.FUList0.opList 205 206[system.cpu.fuPool.FUList0.opList] 207type=OpDesc 208eventq_index=0 209issueLat=1 210opClass=IntAlu 211opLat=1 212 213[system.cpu.fuPool.FUList1] 214type=FUDesc 215children=opList0 opList1 216count=2 217eventq_index=0 218opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 219 220[system.cpu.fuPool.FUList1.opList0] 221type=OpDesc 222eventq_index=0 223issueLat=1 224opClass=IntMult 225opLat=3 226 227[system.cpu.fuPool.FUList1.opList1] 228type=OpDesc 229eventq_index=0 230issueLat=19 231opClass=IntDiv 232opLat=20 233 234[system.cpu.fuPool.FUList2] 235type=FUDesc 236children=opList0 opList1 opList2 237count=4 238eventq_index=0 239opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 240 241[system.cpu.fuPool.FUList2.opList0] 242type=OpDesc 243eventq_index=0 244issueLat=1 245opClass=FloatAdd 246opLat=2 247 248[system.cpu.fuPool.FUList2.opList1] 249type=OpDesc 250eventq_index=0 251issueLat=1 252opClass=FloatCmp 253opLat=2 254 255[system.cpu.fuPool.FUList2.opList2] 256type=OpDesc 257eventq_index=0 258issueLat=1 259opClass=FloatCvt 260opLat=2 261 262[system.cpu.fuPool.FUList3] 263type=FUDesc 264children=opList0 opList1 opList2 265count=2 266eventq_index=0 267opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 268 269[system.cpu.fuPool.FUList3.opList0] 270type=OpDesc 271eventq_index=0 272issueLat=1 273opClass=FloatMult 274opLat=4 275 276[system.cpu.fuPool.FUList3.opList1] 277type=OpDesc 278eventq_index=0 279issueLat=12 280opClass=FloatDiv 281opLat=12 282 283[system.cpu.fuPool.FUList3.opList2] 284type=OpDesc 285eventq_index=0 286issueLat=24 287opClass=FloatSqrt 288opLat=24 289 290[system.cpu.fuPool.FUList4] 291type=FUDesc 292children=opList 293count=0 294eventq_index=0 295opList=system.cpu.fuPool.FUList4.opList 296 297[system.cpu.fuPool.FUList4.opList] 298type=OpDesc 299eventq_index=0 300issueLat=1 301opClass=MemRead 302opLat=1 303 304[system.cpu.fuPool.FUList5] 305type=FUDesc 306children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 307count=4 308eventq_index=0 309opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 310 311[system.cpu.fuPool.FUList5.opList00] 312type=OpDesc 313eventq_index=0 314issueLat=1 315opClass=SimdAdd 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList01] 319type=OpDesc 320eventq_index=0 321issueLat=1 322opClass=SimdAddAcc 323opLat=1 324 325[system.cpu.fuPool.FUList5.opList02] 326type=OpDesc 327eventq_index=0 328issueLat=1 329opClass=SimdAlu 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList03] 333type=OpDesc 334eventq_index=0 335issueLat=1 336opClass=SimdCmp 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList04] 340type=OpDesc 341eventq_index=0 342issueLat=1 343opClass=SimdCvt 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList05] 347type=OpDesc 348eventq_index=0 349issueLat=1 350opClass=SimdMisc 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList06] 354type=OpDesc 355eventq_index=0 356issueLat=1 357opClass=SimdMult 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList07] 361type=OpDesc 362eventq_index=0 363issueLat=1 364opClass=SimdMultAcc 365opLat=1 366 367[system.cpu.fuPool.FUList5.opList08] 368type=OpDesc 369eventq_index=0 370issueLat=1 371opClass=SimdShift 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList09] 375type=OpDesc 376eventq_index=0 377issueLat=1 378opClass=SimdShiftAcc 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList10] 382type=OpDesc 383eventq_index=0 384issueLat=1 385opClass=SimdSqrt 386opLat=1 387 388[system.cpu.fuPool.FUList5.opList11] 389type=OpDesc 390eventq_index=0 391issueLat=1 392opClass=SimdFloatAdd 393opLat=1 394 395[system.cpu.fuPool.FUList5.opList12] 396type=OpDesc 397eventq_index=0 398issueLat=1 399opClass=SimdFloatAlu 400opLat=1 401 402[system.cpu.fuPool.FUList5.opList13] 403type=OpDesc 404eventq_index=0 405issueLat=1 406opClass=SimdFloatCmp 407opLat=1 408 409[system.cpu.fuPool.FUList5.opList14] 410type=OpDesc 411eventq_index=0 412issueLat=1 413opClass=SimdFloatCvt 414opLat=1 415 416[system.cpu.fuPool.FUList5.opList15] 417type=OpDesc 418eventq_index=0 419issueLat=1 420opClass=SimdFloatDiv 421opLat=1 422 423[system.cpu.fuPool.FUList5.opList16] 424type=OpDesc 425eventq_index=0 426issueLat=1 427opClass=SimdFloatMisc 428opLat=1 429 430[system.cpu.fuPool.FUList5.opList17] 431type=OpDesc 432eventq_index=0 433issueLat=1 434opClass=SimdFloatMult 435opLat=1 436 437[system.cpu.fuPool.FUList5.opList18] 438type=OpDesc 439eventq_index=0 440issueLat=1 441opClass=SimdFloatMultAcc 442opLat=1 443 444[system.cpu.fuPool.FUList5.opList19] 445type=OpDesc 446eventq_index=0 447issueLat=1 448opClass=SimdFloatSqrt 449opLat=1 450 451[system.cpu.fuPool.FUList6] 452type=FUDesc 453children=opList 454count=0 455eventq_index=0 456opList=system.cpu.fuPool.FUList6.opList 457 458[system.cpu.fuPool.FUList6.opList] 459type=OpDesc 460eventq_index=0 461issueLat=1 462opClass=MemWrite 463opLat=1 464 465[system.cpu.fuPool.FUList7] 466type=FUDesc 467children=opList0 opList1 468count=4 469eventq_index=0 470opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 471 472[system.cpu.fuPool.FUList7.opList0] 473type=OpDesc 474eventq_index=0 475issueLat=1 476opClass=MemRead 477opLat=1 478 479[system.cpu.fuPool.FUList7.opList1] 480type=OpDesc 481eventq_index=0 482issueLat=1 483opClass=MemWrite 484opLat=1 485 486[system.cpu.fuPool.FUList8] 487type=FUDesc 488children=opList 489count=1 490eventq_index=0 491opList=system.cpu.fuPool.FUList8.opList 492 493[system.cpu.fuPool.FUList8.opList] 494type=OpDesc 495eventq_index=0 496issueLat=3 497opClass=IprAccess 498opLat=3 499 500[system.cpu.icache] 501type=BaseCache 502children=tags 503addr_ranges=0:18446744073709551615 504assoc=2 505clk_domain=system.cpu_clk_domain	161eventq_index=0 162forward_snoops=true 163hit_latency=2 164is_top_level=true 165max_miss_count=0 166mshrs=4 167prefetch_on_access=false 168prefetcher=Null 169response_latency=2 170sequential_access=false 171size=262144 172system=system 173tags=system.cpu.dcache.tags 174tgts_per_mshr=20 175two_queue=false 176write_buffers=8 177cpu_side=system.cpu.dcache_port 178mem_side=system.cpu.toL2Bus.slave[1] 179 180[system.cpu.dcache.tags] 181type=LRU 182assoc=2 183block_size=64 184clk_domain=system.cpu_clk_domain 185eventq_index=0 186hit_latency=2 187sequential_access=false 188size=262144 189 190[system.cpu.dtb] 191type=PowerTLB 192eventq_index=0 193size=64 194 195[system.cpu.fuPool] 196type=FUPool 197children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 198FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 199eventq_index=0 200 201[system.cpu.fuPool.FUList0] 202type=FUDesc 203children=opList 204count=6 205eventq_index=0 206opList=system.cpu.fuPool.FUList0.opList 207 208[system.cpu.fuPool.FUList0.opList] 209type=OpDesc 210eventq_index=0 211issueLat=1 212opClass=IntAlu 213opLat=1 214 215[system.cpu.fuPool.FUList1] 216type=FUDesc 217children=opList0 opList1 218count=2 219eventq_index=0 220opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 221 222[system.cpu.fuPool.FUList1.opList0] 223type=OpDesc 224eventq_index=0 225issueLat=1 226opClass=IntMult 227opLat=3 228 229[system.cpu.fuPool.FUList1.opList1] 230type=OpDesc 231eventq_index=0 232issueLat=19 233opClass=IntDiv 234opLat=20 235 236[system.cpu.fuPool.FUList2] 237type=FUDesc 238children=opList0 opList1 opList2 239count=4 240eventq_index=0 241opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 242 243[system.cpu.fuPool.FUList2.opList0] 244type=OpDesc 245eventq_index=0 246issueLat=1 247opClass=FloatAdd 248opLat=2 249 250[system.cpu.fuPool.FUList2.opList1] 251type=OpDesc 252eventq_index=0 253issueLat=1 254opClass=FloatCmp 255opLat=2 256 257[system.cpu.fuPool.FUList2.opList2] 258type=OpDesc 259eventq_index=0 260issueLat=1 261opClass=FloatCvt 262opLat=2 263 264[system.cpu.fuPool.FUList3] 265type=FUDesc 266children=opList0 opList1 opList2 267count=2 268eventq_index=0 269opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 270 271[system.cpu.fuPool.FUList3.opList0] 272type=OpDesc 273eventq_index=0 274issueLat=1 275opClass=FloatMult 276opLat=4 277 278[system.cpu.fuPool.FUList3.opList1] 279type=OpDesc 280eventq_index=0 281issueLat=12 282opClass=FloatDiv 283opLat=12 284 285[system.cpu.fuPool.FUList3.opList2] 286type=OpDesc 287eventq_index=0 288issueLat=24 289opClass=FloatSqrt 290opLat=24 291 292[system.cpu.fuPool.FUList4] 293type=FUDesc 294children=opList 295count=0 296eventq_index=0 297opList=system.cpu.fuPool.FUList4.opList 298 299[system.cpu.fuPool.FUList4.opList] 300type=OpDesc 301eventq_index=0 302issueLat=1 303opClass=MemRead 304opLat=1 305 306[system.cpu.fuPool.FUList5] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 309count=4 310eventq_index=0 311opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 312 313[system.cpu.fuPool.FUList5.opList00] 314type=OpDesc 315eventq_index=0 316issueLat=1 317opClass=SimdAdd 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList01] 321type=OpDesc 322eventq_index=0 323issueLat=1 324opClass=SimdAddAcc 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList02] 328type=OpDesc 329eventq_index=0 330issueLat=1 331opClass=SimdAlu 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList03] 335type=OpDesc 336eventq_index=0 337issueLat=1 338opClass=SimdCmp 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList04] 342type=OpDesc 343eventq_index=0 344issueLat=1 345opClass=SimdCvt 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList05] 349type=OpDesc 350eventq_index=0 351issueLat=1 352opClass=SimdMisc 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList06] 356type=OpDesc 357eventq_index=0 358issueLat=1 359opClass=SimdMult 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList07] 363type=OpDesc 364eventq_index=0 365issueLat=1 366opClass=SimdMultAcc 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList08] 370type=OpDesc 371eventq_index=0 372issueLat=1 373opClass=SimdShift 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList09] 377type=OpDesc 378eventq_index=0 379issueLat=1 380opClass=SimdShiftAcc 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList10] 384type=OpDesc 385eventq_index=0 386issueLat=1 387opClass=SimdSqrt 388opLat=1 389 390[system.cpu.fuPool.FUList5.opList11] 391type=OpDesc 392eventq_index=0 393issueLat=1 394opClass=SimdFloatAdd 395opLat=1 396 397[system.cpu.fuPool.FUList5.opList12] 398type=OpDesc 399eventq_index=0 400issueLat=1 401opClass=SimdFloatAlu 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList13] 405type=OpDesc 406eventq_index=0 407issueLat=1 408opClass=SimdFloatCmp 409opLat=1 410 411[system.cpu.fuPool.FUList5.opList14] 412type=OpDesc 413eventq_index=0 414issueLat=1 415opClass=SimdFloatCvt 416opLat=1 417 418[system.cpu.fuPool.FUList5.opList15] 419type=OpDesc 420eventq_index=0 421issueLat=1 422opClass=SimdFloatDiv 423opLat=1 424 425[system.cpu.fuPool.FUList5.opList16] 426type=OpDesc 427eventq_index=0 428issueLat=1 429opClass=SimdFloatMisc 430opLat=1 431 432[system.cpu.fuPool.FUList5.opList17] 433type=OpDesc 434eventq_index=0 435issueLat=1 436opClass=SimdFloatMult 437opLat=1 438 439[system.cpu.fuPool.FUList5.opList18] 440type=OpDesc 441eventq_index=0 442issueLat=1 443opClass=SimdFloatMultAcc 444opLat=1 445 446[system.cpu.fuPool.FUList5.opList19] 447type=OpDesc 448eventq_index=0 449issueLat=1 450opClass=SimdFloatSqrt 451opLat=1 452 453[system.cpu.fuPool.FUList6] 454type=FUDesc 455children=opList 456count=0 457eventq_index=0 458opList=system.cpu.fuPool.FUList6.opList 459 460[system.cpu.fuPool.FUList6.opList] 461type=OpDesc 462eventq_index=0 463issueLat=1 464opClass=MemWrite 465opLat=1 466 467[system.cpu.fuPool.FUList7] 468type=FUDesc 469children=opList0 opList1 470count=4 471eventq_index=0 472opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 473 474[system.cpu.fuPool.FUList7.opList0] 475type=OpDesc 476eventq_index=0 477issueLat=1 478opClass=MemRead 479opLat=1 480 481[system.cpu.fuPool.FUList7.opList1] 482type=OpDesc 483eventq_index=0 484issueLat=1 485opClass=MemWrite 486opLat=1 487 488[system.cpu.fuPool.FUList8] 489type=FUDesc 490children=opList 491count=1 492eventq_index=0 493opList=system.cpu.fuPool.FUList8.opList 494 495[system.cpu.fuPool.FUList8.opList] 496type=OpDesc 497eventq_index=0 498issueLat=3 499opClass=IprAccess 500opLat=3 501 502[system.cpu.icache] 503type=BaseCache 504children=tags 505addr_ranges=0:18446744073709551615 506assoc=2 507clk_domain=system.cpu_clk_domain
	508demand_mshr_reserve=1
506eventq_index=0 507forward_snoops=true 508hit_latency=2 509is_top_level=true 510max_miss_count=0 511mshrs=4 512prefetch_on_access=false 513prefetcher=Null 514response_latency=2 515sequential_access=false 516size=131072 517system=system 518tags=system.cpu.icache.tags 519tgts_per_mshr=20 520two_queue=false 521write_buffers=8 522cpu_side=system.cpu.icache_port 523mem_side=system.cpu.toL2Bus.slave[0] 524 525[system.cpu.icache.tags] 526type=LRU 527assoc=2 528block_size=64 529clk_domain=system.cpu_clk_domain 530eventq_index=0 531hit_latency=2 532sequential_access=false 533size=131072 534 535[system.cpu.interrupts] 536type=PowerInterrupts 537eventq_index=0 538 539[system.cpu.isa] 540type=PowerISA 541eventq_index=0 542 543[system.cpu.itb] 544type=PowerTLB 545eventq_index=0 546size=64 547 548[system.cpu.l2cache] 549type=BaseCache 550children=tags 551addr_ranges=0:18446744073709551615 552assoc=8 553clk_domain=system.cpu_clk_domain	509eventq_index=0 510forward_snoops=true 511hit_latency=2 512is_top_level=true 513max_miss_count=0 514mshrs=4 515prefetch_on_access=false 516prefetcher=Null 517response_latency=2 518sequential_access=false 519size=131072 520system=system 521tags=system.cpu.icache.tags 522tgts_per_mshr=20 523two_queue=false 524write_buffers=8 525cpu_side=system.cpu.icache_port 526mem_side=system.cpu.toL2Bus.slave[0] 527 528[system.cpu.icache.tags] 529type=LRU 530assoc=2 531block_size=64 532clk_domain=system.cpu_clk_domain 533eventq_index=0 534hit_latency=2 535sequential_access=false 536size=131072 537 538[system.cpu.interrupts] 539type=PowerInterrupts 540eventq_index=0 541 542[system.cpu.isa] 543type=PowerISA 544eventq_index=0 545 546[system.cpu.itb] 547type=PowerTLB 548eventq_index=0 549size=64 550 551[system.cpu.l2cache] 552type=BaseCache 553children=tags 554addr_ranges=0:18446744073709551615 555assoc=8 556clk_domain=system.cpu_clk_domain
	557demand_mshr_reserve=1
554eventq_index=0 555forward_snoops=true 556hit_latency=20 557is_top_level=false 558max_miss_count=0 559mshrs=20 560prefetch_on_access=false 561prefetcher=Null 562response_latency=20 563sequential_access=false 564size=2097152 565system=system 566tags=system.cpu.l2cache.tags 567tgts_per_mshr=12 568two_queue=false 569write_buffers=8 570cpu_side=system.cpu.toL2Bus.master[0] 571mem_side=system.membus.slave[1] 572 573[system.cpu.l2cache.tags] 574type=LRU 575assoc=8 576block_size=64 577clk_domain=system.cpu_clk_domain 578eventq_index=0 579hit_latency=20 580sequential_access=false 581size=2097152 582 583[system.cpu.toL2Bus] 584type=CoherentXBar 585clk_domain=system.cpu_clk_domain 586eventq_index=0	558eventq_index=0 559forward_snoops=true 560hit_latency=20 561is_top_level=false 562max_miss_count=0 563mshrs=20 564prefetch_on_access=false 565prefetcher=Null 566response_latency=20 567sequential_access=false 568size=2097152 569system=system 570tags=system.cpu.l2cache.tags 571tgts_per_mshr=12 572two_queue=false 573write_buffers=8 574cpu_side=system.cpu.toL2Bus.master[0] 575mem_side=system.membus.slave[1] 576 577[system.cpu.l2cache.tags] 578type=LRU 579assoc=8 580block_size=64 581clk_domain=system.cpu_clk_domain 582eventq_index=0 583hit_latency=20 584sequential_access=false 585size=2097152 586 587[system.cpu.toL2Bus] 588type=CoherentXBar 589clk_domain=system.cpu_clk_domain 590eventq_index=0
587header_cycles=1	591forward_latency=0 592frontend_latency=1 593response_latency=1
588snoop_filter=Null	594snoop_filter=Null
	595snoop_response_latency=1
589system=system 590use_default_range=false 591width=32 592master=system.cpu.l2cache.cpu_side 593slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 594 595[system.cpu.tracer] 596type=ExeTracer 597eventq_index=0 598 599[system.cpu.workload] 600type=LiveProcess 601cmd=hello 602cwd=	596system=system 597use_default_range=false 598width=32 599master=system.cpu.l2cache.cpu_side 600slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 601 602[system.cpu.tracer] 603type=ExeTracer 604eventq_index=0 605 606[system.cpu.workload] 607type=LiveProcess 608cmd=hello 609cwd=
	610drivers=
603egid=100 604env= 605errout=cerr 606euid=100 607eventq_index=0 608executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello 609gid=100 610input=cin	611egid=100 612env= 613errout=cerr 614euid=100 615eventq_index=0 616executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/power/linux/hello 617gid=100 618input=cin
	619kvmInSE=false
611max_stack_size=67108864 612output=cout 613pid=100 614ppid=99 615simpoint=0 616system=system 617uid=100 618useArchPT=false 619 620[system.cpu_clk_domain] 621type=SrcClockDomain 622clock=500 623domain_id=-1 624eventq_index=0 625init_perf_level=0 626voltage_domain=system.voltage_domain 627 628[system.dvfs_handler] 629type=DVFSHandler 630domains= 631enable=false 632eventq_index=0 633sys_clk_domain=system.clk_domain 634transition_latency=100000000 635 636[system.membus] 637type=CoherentXBar 638clk_domain=system.clk_domain 639eventq_index=0	620max_stack_size=67108864 621output=cout 622pid=100 623ppid=99 624simpoint=0 625system=system 626uid=100 627useArchPT=false 628 629[system.cpu_clk_domain] 630type=SrcClockDomain 631clock=500 632domain_id=-1 633eventq_index=0 634init_perf_level=0 635voltage_domain=system.voltage_domain 636 637[system.dvfs_handler] 638type=DVFSHandler 639domains= 640enable=false 641eventq_index=0 642sys_clk_domain=system.clk_domain 643transition_latency=100000000 644 645[system.membus] 646type=CoherentXBar 647clk_domain=system.clk_domain 648eventq_index=0
640header_cycles=1	649forward_latency=4 650frontend_latency=3 651response_latency=2
641snoop_filter=Null	652snoop_filter=Null
	653snoop_response_latency=4
642system=system 643use_default_range=false	654system=system 655use_default_range=false
644width=8	656width=16
645master=system.physmem.port 646slave=system.system_port system.cpu.l2cache.mem_side 647 648[system.physmem] 649type=DRAMCtrl 650IDD0=0.075000 651IDD02=0.000000 652IDD2N=0.050000 653IDD2N2=0.000000 654IDD2P0=0.000000 655IDD2P02=0.000000 656IDD2P1=0.000000 657IDD2P12=0.000000 658IDD3N=0.057000 659IDD3N2=0.000000 660IDD3P0=0.000000 661IDD3P02=0.000000 662IDD3P1=0.000000 663IDD3P12=0.000000 664IDD4R=0.187000 665IDD4R2=0.000000 666IDD4W=0.165000 667IDD4W2=0.000000 668IDD5=0.220000 669IDD52=0.000000 670IDD6=0.000000 671IDD62=0.000000 672VDD=1.500000 673VDD2=0.000000 674activation_limit=4	657master=system.physmem.port 658slave=system.system_port system.cpu.l2cache.mem_side 659 660[system.physmem] 661type=DRAMCtrl 662IDD0=0.075000 663IDD02=0.000000 664IDD2N=0.050000 665IDD2N2=0.000000 666IDD2P0=0.000000 667IDD2P02=0.000000 668IDD2P1=0.000000 669IDD2P12=0.000000 670IDD3N=0.057000 671IDD3N2=0.000000 672IDD3P0=0.000000 673IDD3P02=0.000000 674IDD3P1=0.000000 675IDD3P12=0.000000 676IDD4R=0.187000 677IDD4R2=0.000000 678IDD4W=0.165000 679IDD4W2=0.000000 680IDD5=0.220000 681IDD52=0.000000 682IDD6=0.000000 683IDD62=0.000000 684VDD=1.500000 685VDD2=0.000000 686activation_limit=4
675addr_mapping=RoRaBaChCo	687addr_mapping=RoRaBaCoCh
676bank_groups_per_rank=0 677banks_per_rank=8 678burst_length=8 679channels=1 680clk_domain=system.clk_domain 681conf_table_reported=true 682device_bus_width=8 683device_rowbuffer_size=1024	688bank_groups_per_rank=0 689banks_per_rank=8 690burst_length=8 691channels=1 692clk_domain=system.clk_domain 693conf_table_reported=true 694device_bus_width=8 695device_rowbuffer_size=1024
	696device_size=536870912
684devices_per_rank=8 685dll=true 686eventq_index=0 687in_addr_map=true 688max_accesses_per_row=16 689mem_sched_policy=frfcfs 690min_writes_per_switch=16 691null=false 692page_policy=open_adaptive 693range=0:134217727 694ranks_per_channel=2 695read_buffer_size=32 696static_backend_latency=10000 697static_frontend_latency=10000 698tBURST=5000 699tCCD_L=0 700tCK=1250 701tCL=13750 702tCS=2500 703tRAS=35000 704tRCD=13750 705tREFI=7800000 706tRFC=260000 707tRP=13750 708tRRD=6000 709tRRD_L=0 710tRTP=7500 711tRTW=2500 712tWR=15000 713tWTR=7500 714tXAW=30000 715tXP=0 716tXPDLL=0 717tXS=0 718tXSDLL=0 719write_buffer_size=64 720write_high_thresh_perc=85 721write_low_thresh_perc=50 722port=system.membus.master[0] 723 724[system.voltage_domain] 725type=VoltageDomain 726eventq_index=0 727voltage=1.000000 728	697devices_per_rank=8 698dll=true 699eventq_index=0 700in_addr_map=true 701max_accesses_per_row=16 702mem_sched_policy=frfcfs 703min_writes_per_switch=16 704null=false 705page_policy=open_adaptive 706range=0:134217727 707ranks_per_channel=2 708read_buffer_size=32 709static_backend_latency=10000 710static_frontend_latency=10000 711tBURST=5000 712tCCD_L=0 713tCK=1250 714tCL=13750 715tCS=2500 716tRAS=35000 717tRCD=13750 718tREFI=7800000 719tRFC=260000 720tRP=13750 721tRRD=6000 722tRRD_L=0 723tRTP=7500 724tRTW=2500 725tWR=15000 726tWTR=7500 727tXAW=30000 728tXP=0 729tXPDLL=0 730tXS=0 731tXSDLL=0 732write_buffer_size=64 733write_high_thresh_perc=85 734write_low_thresh_perc=50 735port=system.membus.master[0] 736 737[system.voltage_domain] 738type=VoltageDomain 739eventq_index=0 740voltage=1.000000 741