1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 164 unchanged lines hidden (view full) ---
173
174[system.cpu.dcache]
175type=Cache
176children=tags
177addr_ranges=0:18446744073709551615:0:0:0:0
178assoc=2
179clk_domain=system.cpu_clk_domain
180clusivity=mostly_incl
181default_p_state=UNDEFINED
182demand_mshr_reserve=1
183eventq_index=0
184hit_latency=2
185is_read_only=false
186max_miss_count=0
187mshrs=4
188p_state_clk_gate_bins=20
189p_state_clk_gate_max=1000000000000
190p_state_clk_gate_min=1000
191power_model=Null
192prefetch_on_access=false
193prefetcher=Null
194response_latency=2
195sequential_access=false
196size=262144
197system=system
198tags=system.cpu.dcache.tags
199tgts_per_mshr=20
200write_buffers=8
201writeback_clean=false
202cpu_side=system.cpu.dcache_port
203mem_side=system.cpu.toL2Bus.slave[1]
204
205[system.cpu.dcache.tags]
206type=LRU
207assoc=2
208block_size=64
209clk_domain=system.cpu_clk_domain
210default_p_state=UNDEFINED
211eventq_index=0
212hit_latency=2
213p_state_clk_gate_bins=20
214p_state_clk_gate_max=1000000000000
215p_state_clk_gate_min=1000
216power_model=Null
217sequential_access=false
218size=262144
219
220[system.cpu.dtb]
221type=PowerTLB
222eventq_index=0
223size=64
224
225[system.cpu.fuPool]
226type=FUPool
--- 61 unchanged lines hidden (view full) ---
288type=OpDesc
289eventq_index=0
290opClass=FloatCvt
291opLat=2
292pipelined=true
293
294[system.cpu.fuPool.FUList3]
295type=FUDesc
296children=opList0 opList1 opList2
297count=2
298eventq_index=0
299opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
300
301[system.cpu.fuPool.FUList3.opList0]
302type=OpDesc
303eventq_index=0
304opClass=FloatMult
305opLat=4
306pipelined=true
307
308[system.cpu.fuPool.FUList3.opList1]
309type=OpDesc
310eventq_index=0
311opClass=FloatDiv
312opLat=12
313pipelined=false
314
315[system.cpu.fuPool.FUList3.opList2]
316type=OpDesc
317eventq_index=0
318opClass=FloatSqrt
319opLat=24
320pipelined=false
321
322[system.cpu.fuPool.FUList4]
323type=FUDesc
324children=opList
325count=0
326eventq_index=0
327opList=system.cpu.fuPool.FUList4.opList
328
329[system.cpu.fuPool.FUList4.opList]
330type=OpDesc
331eventq_index=0
332opClass=MemRead
333opLat=1
334pipelined=true
335
336[system.cpu.fuPool.FUList5]
337type=FUDesc
338children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
339count=4
340eventq_index=0
341opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
342
343[system.cpu.fuPool.FUList5.opList00]
--- 133 unchanged lines hidden (view full) ---
477type=OpDesc
478eventq_index=0
479opClass=SimdFloatSqrt
480opLat=1
481pipelined=true
482
483[system.cpu.fuPool.FUList6]
484type=FUDesc
485children=opList
486count=0
487eventq_index=0
488opList=system.cpu.fuPool.FUList6.opList
489
490[system.cpu.fuPool.FUList6.opList]
491type=OpDesc
492eventq_index=0
493opClass=MemWrite
494opLat=1
495pipelined=true
496
497[system.cpu.fuPool.FUList7]
498type=FUDesc
499children=opList0 opList1
500count=4
501eventq_index=0
502opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
503
504[system.cpu.fuPool.FUList7.opList0]
505type=OpDesc
506eventq_index=0
507opClass=MemRead
508opLat=1
509pipelined=true
510
511[system.cpu.fuPool.FUList7.opList1]
512type=OpDesc
513eventq_index=0
514opClass=MemWrite
515opLat=1
516pipelined=true
517
518[system.cpu.fuPool.FUList8]
519type=FUDesc
520children=opList
521count=1
522eventq_index=0
523opList=system.cpu.fuPool.FUList8.opList
524
525[system.cpu.fuPool.FUList8.opList]
--- 5 unchanged lines hidden (view full) ---
531
532[system.cpu.icache]
533type=Cache
534children=tags
535addr_ranges=0:18446744073709551615:0:0:0:0
536assoc=2
537clk_domain=system.cpu_clk_domain
538clusivity=mostly_incl
539default_p_state=UNDEFINED
540demand_mshr_reserve=1
541eventq_index=0
542hit_latency=2
543is_read_only=true
544max_miss_count=0
545mshrs=4
546p_state_clk_gate_bins=20
547p_state_clk_gate_max=1000000000000
548p_state_clk_gate_min=1000
549power_model=Null
550prefetch_on_access=false
551prefetcher=Null
552response_latency=2
553sequential_access=false
554size=131072
555system=system
556tags=system.cpu.icache.tags
557tgts_per_mshr=20
558write_buffers=8
559writeback_clean=true
560cpu_side=system.cpu.icache_port
561mem_side=system.cpu.toL2Bus.slave[0]
562
563[system.cpu.icache.tags]
564type=LRU
565assoc=2
566block_size=64
567clk_domain=system.cpu_clk_domain
568default_p_state=UNDEFINED
569eventq_index=0
570hit_latency=2
571p_state_clk_gate_bins=20
572p_state_clk_gate_max=1000000000000
573p_state_clk_gate_min=1000
574power_model=Null
575sequential_access=false
576size=131072
577
578[system.cpu.interrupts]
579type=PowerInterrupts
580eventq_index=0
581
582[system.cpu.isa]
583type=PowerISA
584eventq_index=0
--- 5 unchanged lines hidden (view full) ---
590
591[system.cpu.l2cache]
592type=Cache
593children=tags
594addr_ranges=0:18446744073709551615:0:0:0:0
595assoc=8
596clk_domain=system.cpu_clk_domain
597clusivity=mostly_incl
598default_p_state=UNDEFINED
599demand_mshr_reserve=1
600eventq_index=0
601hit_latency=20
602is_read_only=false
603max_miss_count=0
604mshrs=20
605p_state_clk_gate_bins=20
606p_state_clk_gate_max=1000000000000
607p_state_clk_gate_min=1000
608power_model=Null
609prefetch_on_access=false
610prefetcher=Null
611response_latency=20
612sequential_access=false
613size=2097152
614system=system
615tags=system.cpu.l2cache.tags
616tgts_per_mshr=12
617write_buffers=8
618writeback_clean=false
619cpu_side=system.cpu.toL2Bus.master[0]
620mem_side=system.membus.slave[1]
621
622[system.cpu.l2cache.tags]
623type=LRU
624assoc=8
625block_size=64
626clk_domain=system.cpu_clk_domain
627default_p_state=UNDEFINED
628eventq_index=0
629hit_latency=20
630p_state_clk_gate_bins=20
631p_state_clk_gate_max=1000000000000
632p_state_clk_gate_min=1000
633power_model=Null
634sequential_access=false
635size=2097152
636
637[system.cpu.toL2Bus]
638type=CoherentXBar
639children=snoop_filter
640clk_domain=system.cpu_clk_domain
641default_p_state=UNDEFINED
642eventq_index=0
643forward_latency=0
--- 28 unchanged lines hidden (view full) ---
672cmd=hello
673cwd=
674drivers=
675egid=100
676env=
677errout=cerr
678euid=100
679eventq_index=0
680executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello
681gid=100
682input=cin
683kvmInSE=false
684max_stack_size=67108864
685output=cout
686pid=100
687ppid=99
688simpoint=0
--- 137 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 164 unchanged lines hidden (view full) ---
173
174[system.cpu.dcache]
175type=Cache
176children=tags
177addr_ranges=0:18446744073709551615:0:0:0:0
178assoc=2
179clk_domain=system.cpu_clk_domain
180clusivity=mostly_incl
181default_p_state=UNDEFINED
182demand_mshr_reserve=1
183eventq_index=0
184hit_latency=2
185is_read_only=false
186max_miss_count=0
187mshrs=4
188p_state_clk_gate_bins=20
189p_state_clk_gate_max=1000000000000
190p_state_clk_gate_min=1000
191power_model=Null
192prefetch_on_access=false
193prefetcher=Null
194response_latency=2
195sequential_access=false
196size=262144
197system=system
198tags=system.cpu.dcache.tags
199tgts_per_mshr=20
200write_buffers=8
201writeback_clean=false
202cpu_side=system.cpu.dcache_port
203mem_side=system.cpu.toL2Bus.slave[1]
204
205[system.cpu.dcache.tags]
206type=LRU
207assoc=2
208block_size=64
209clk_domain=system.cpu_clk_domain
210default_p_state=UNDEFINED
211eventq_index=0
212hit_latency=2
213p_state_clk_gate_bins=20
214p_state_clk_gate_max=1000000000000
215p_state_clk_gate_min=1000
216power_model=Null
217sequential_access=false
218size=262144
219
220[system.cpu.dtb]
221type=PowerTLB
222eventq_index=0
223size=64
224
225[system.cpu.fuPool]
226type=FUPool
--- 61 unchanged lines hidden (view full) ---
288type=OpDesc
289eventq_index=0
290opClass=FloatCvt
291opLat=2
292pipelined=true
293
294[system.cpu.fuPool.FUList3]
295type=FUDesc
296children=opList0 opList1 opList2
297count=2
298eventq_index=0
299opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
300
301[system.cpu.fuPool.FUList3.opList0]
302type=OpDesc
303eventq_index=0
304opClass=FloatMult
305opLat=4
306pipelined=true
307
308[system.cpu.fuPool.FUList3.opList1]
309type=OpDesc
310eventq_index=0
311opClass=FloatDiv
312opLat=12
313pipelined=false
314
315[system.cpu.fuPool.FUList3.opList2]
316type=OpDesc
317eventq_index=0
318opClass=FloatSqrt
319opLat=24
320pipelined=false
321
322[system.cpu.fuPool.FUList4]
323type=FUDesc
324children=opList
325count=0
326eventq_index=0
327opList=system.cpu.fuPool.FUList4.opList
328
329[system.cpu.fuPool.FUList4.opList]
330type=OpDesc
331eventq_index=0
332opClass=MemRead
333opLat=1
334pipelined=true
335
336[system.cpu.fuPool.FUList5]
337type=FUDesc
338children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
339count=4
340eventq_index=0
341opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
342
343[system.cpu.fuPool.FUList5.opList00]
--- 133 unchanged lines hidden (view full) ---
477type=OpDesc
478eventq_index=0
479opClass=SimdFloatSqrt
480opLat=1
481pipelined=true
482
483[system.cpu.fuPool.FUList6]
484type=FUDesc
485children=opList
486count=0
487eventq_index=0
488opList=system.cpu.fuPool.FUList6.opList
489
490[system.cpu.fuPool.FUList6.opList]
491type=OpDesc
492eventq_index=0
493opClass=MemWrite
494opLat=1
495pipelined=true
496
497[system.cpu.fuPool.FUList7]
498type=FUDesc
499children=opList0 opList1
500count=4
501eventq_index=0
502opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
503
504[system.cpu.fuPool.FUList7.opList0]
505type=OpDesc
506eventq_index=0
507opClass=MemRead
508opLat=1
509pipelined=true
510
511[system.cpu.fuPool.FUList7.opList1]
512type=OpDesc
513eventq_index=0
514opClass=MemWrite
515opLat=1
516pipelined=true
517
518[system.cpu.fuPool.FUList8]
519type=FUDesc
520children=opList
521count=1
522eventq_index=0
523opList=system.cpu.fuPool.FUList8.opList
524
525[system.cpu.fuPool.FUList8.opList]
--- 5 unchanged lines hidden (view full) ---
531
532[system.cpu.icache]
533type=Cache
534children=tags
535addr_ranges=0:18446744073709551615:0:0:0:0
536assoc=2
537clk_domain=system.cpu_clk_domain
538clusivity=mostly_incl
539default_p_state=UNDEFINED
540demand_mshr_reserve=1
541eventq_index=0
542hit_latency=2
543is_read_only=true
544max_miss_count=0
545mshrs=4
546p_state_clk_gate_bins=20
547p_state_clk_gate_max=1000000000000
548p_state_clk_gate_min=1000
549power_model=Null
550prefetch_on_access=false
551prefetcher=Null
552response_latency=2
553sequential_access=false
554size=131072
555system=system
556tags=system.cpu.icache.tags
557tgts_per_mshr=20
558write_buffers=8
559writeback_clean=true
560cpu_side=system.cpu.icache_port
561mem_side=system.cpu.toL2Bus.slave[0]
562
563[system.cpu.icache.tags]
564type=LRU
565assoc=2
566block_size=64
567clk_domain=system.cpu_clk_domain
568default_p_state=UNDEFINED
569eventq_index=0
570hit_latency=2
571p_state_clk_gate_bins=20
572p_state_clk_gate_max=1000000000000
573p_state_clk_gate_min=1000
574power_model=Null
575sequential_access=false
576size=131072
577
578[system.cpu.interrupts]
579type=PowerInterrupts
580eventq_index=0
581
582[system.cpu.isa]
583type=PowerISA
584eventq_index=0
--- 5 unchanged lines hidden (view full) ---
590
591[system.cpu.l2cache]
592type=Cache
593children=tags
594addr_ranges=0:18446744073709551615:0:0:0:0
595assoc=8
596clk_domain=system.cpu_clk_domain
597clusivity=mostly_incl
598default_p_state=UNDEFINED
599demand_mshr_reserve=1
600eventq_index=0
601hit_latency=20
602is_read_only=false
603max_miss_count=0
604mshrs=20
605p_state_clk_gate_bins=20
606p_state_clk_gate_max=1000000000000
607p_state_clk_gate_min=1000
608power_model=Null
609prefetch_on_access=false
610prefetcher=Null
611response_latency=20
612sequential_access=false
613size=2097152
614system=system
615tags=system.cpu.l2cache.tags
616tgts_per_mshr=12
617write_buffers=8
618writeback_clean=false
619cpu_side=system.cpu.toL2Bus.master[0]
620mem_side=system.membus.slave[1]
621
622[system.cpu.l2cache.tags]
623type=LRU
624assoc=8
625block_size=64
626clk_domain=system.cpu_clk_domain
627default_p_state=UNDEFINED
628eventq_index=0
629hit_latency=20
630p_state_clk_gate_bins=20
631p_state_clk_gate_max=1000000000000
632p_state_clk_gate_min=1000
633power_model=Null
634sequential_access=false
635size=2097152
636
637[system.cpu.toL2Bus]
638type=CoherentXBar
639children=snoop_filter
640clk_domain=system.cpu_clk_domain
641default_p_state=UNDEFINED
642eventq_index=0
643forward_latency=0
--- 28 unchanged lines hidden (view full) ---
672cmd=hello
673cwd=
674drivers=
675egid=100
676env=
677errout=cerr
678euid=100
679eventq_index=0
680executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/power/linux/hello
681gid=100
682input=cin
683kvmInSE=false
684max_stack_size=67108864
685output=cout
686pid=100
687ppid=99
688simpoint=0
--- 137 unchanged lines hidden ---