| config.ini (8983:8800b05e1cb3) | config.ini (9055:38f1926fb599) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 129 unchanged lines hidden (view full) --- 138tgts_per_mshr=5 139trace_addr=0 140two_queue=false 141write_buffers=8 142cpu_side=system.cpu.toL2Bus.master[0] 143mem_side=system.membus.slave[1] 144 145[system.cpu.toL2Bus] | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 129 unchanged lines hidden (view full) --- 138tgts_per_mshr=5 139trace_addr=0 140two_queue=false 141write_buffers=8 142cpu_side=system.cpu.toL2Bus.master[0] 143mem_side=system.membus.slave[1] 144 145[system.cpu.toL2Bus] |
| 146type=Bus | 146type=CoherentBus |
| 147block_size=64 | 147block_size=64 |
| 148bus_id=0 | |
| 149clock=1000 150header_cycles=1 151use_default_range=false 152width=64 153master=system.cpu.l2cache.cpu_side 154slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 155 156[system.cpu.tracer] --- 14 unchanged lines hidden (view full) --- 171output=cout 172pid=100 173ppid=99 174simpoint=0 175system=system 176uid=100 177 178[system.membus] | 148clock=1000 149header_cycles=1 150use_default_range=false 151width=64 152master=system.cpu.l2cache.cpu_side 153slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 154 155[system.cpu.tracer] --- 14 unchanged lines hidden (view full) --- 170output=cout 171pid=100 172ppid=99 173simpoint=0 174system=system 175uid=100 176 177[system.membus] |
| 179type=Bus | 178type=CoherentBus |
| 180block_size=64 | 179block_size=64 |
| 181bus_id=0 | |
| 182clock=1000 183header_cycles=1 184use_default_range=false 185width=64 186master=system.physmem.port[0] 187slave=system.system_port system.cpu.l2cache.mem_side 188 189[system.physmem] 190type=SimpleMemory 191conf_table_reported=false 192file= 193in_addr_map=true 194latency=30000 195latency_var=0 196null=false 197range=0:134217727 198zero=false 199port=system.membus.master[0] 200 | 180clock=1000 181header_cycles=1 182use_default_range=false 183width=64 184master=system.physmem.port[0] 185slave=system.system_port system.cpu.l2cache.mem_side 186 187[system.physmem] 188type=SimpleMemory 189conf_table_reported=false 190file= 191in_addr_map=true 192latency=30000 193latency_var=0 194null=false 195range=0:134217727 196zero=false 197port=system.membus.master[0] 198 |