| config.ini (11440:76b5639162af) | config.ini (11570:4aac82f10951) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17default_p_state=UNDEFINED |
|
| 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 | 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 |
| 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null |
|
| 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 --- 12 unchanged lines hidden (view full) --- 50 51[system.cpu] 52type=TimingSimpleCPU 53children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 54branchPred=Null 55checker=Null 56clk_domain=system.cpu_clk_domain 57cpu_id=0 | 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 --- 12 unchanged lines hidden (view full) --- 55 56[system.cpu] 57type=TimingSimpleCPU 58children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload 59branchPred=Null 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 |
| 63default_p_state=UNDEFINED |
|
| 58do_checkpoint_insts=true 59do_quiesce=true 60do_statistics_insts=true 61dtb=system.cpu.dtb 62eventq_index=0 63function_trace=false 64function_trace_start=0 65interrupts=system.cpu.interrupts 66isa=system.cpu.isa 67itb=system.cpu.itb 68max_insts_all_threads=0 69max_insts_any_thread=0 70max_loads_all_threads=0 71max_loads_any_thread=0 72numThreads=1 | 64do_checkpoint_insts=true 65do_quiesce=true 66do_statistics_insts=true 67dtb=system.cpu.dtb 68eventq_index=0 69function_trace=false 70function_trace_start=0 71interrupts=system.cpu.interrupts 72isa=system.cpu.isa 73itb=system.cpu.itb 74max_insts_all_threads=0 75max_insts_any_thread=0 76max_loads_all_threads=0 77max_loads_any_thread=0 78numThreads=1 |
| 79p_state_clk_gate_bins=20 80p_state_clk_gate_max=1000000000000 81p_state_clk_gate_min=1000 82power_model=Null |
|
| 73profile=0 74progress_interval=0 75simpoint_start_insts= 76socket_id=0 77switched_out=false 78system=system 79tracer=system.cpu.tracer 80workload=system.cpu.workload 81dcache_port=system.cpu.dcache.cpu_side 82icache_port=system.cpu.icache.cpu_side 83 84[system.cpu.dcache] 85type=Cache 86children=tags 87addr_ranges=0:18446744073709551615 88assoc=2 89clk_domain=system.cpu_clk_domain 90clusivity=mostly_incl | 83profile=0 84progress_interval=0 85simpoint_start_insts= 86socket_id=0 87switched_out=false 88system=system 89tracer=system.cpu.tracer 90workload=system.cpu.workload 91dcache_port=system.cpu.dcache.cpu_side 92icache_port=system.cpu.icache.cpu_side 93 94[system.cpu.dcache] 95type=Cache 96children=tags 97addr_ranges=0:18446744073709551615 98assoc=2 99clk_domain=system.cpu_clk_domain 100clusivity=mostly_incl |
| 101default_p_state=UNDEFINED |
|
| 91demand_mshr_reserve=1 92eventq_index=0 93hit_latency=2 94is_read_only=false 95max_miss_count=0 96mshrs=4 | 102demand_mshr_reserve=1 103eventq_index=0 104hit_latency=2 105is_read_only=false 106max_miss_count=0 107mshrs=4 |
| 108p_state_clk_gate_bins=20 109p_state_clk_gate_max=1000000000000 110p_state_clk_gate_min=1000 111power_model=Null |
|
| 97prefetch_on_access=false 98prefetcher=Null 99response_latency=2 100sequential_access=false 101size=262144 102system=system 103tags=system.cpu.dcache.tags 104tgts_per_mshr=20 105write_buffers=8 106writeback_clean=false 107cpu_side=system.cpu.dcache_port 108mem_side=system.cpu.toL2Bus.slave[1] 109 110[system.cpu.dcache.tags] 111type=LRU 112assoc=2 113block_size=64 114clk_domain=system.cpu_clk_domain | 112prefetch_on_access=false 113prefetcher=Null 114response_latency=2 115sequential_access=false 116size=262144 117system=system 118tags=system.cpu.dcache.tags 119tgts_per_mshr=20 120write_buffers=8 121writeback_clean=false 122cpu_side=system.cpu.dcache_port 123mem_side=system.cpu.toL2Bus.slave[1] 124 125[system.cpu.dcache.tags] 126type=LRU 127assoc=2 128block_size=64 129clk_domain=system.cpu_clk_domain |
| 130default_p_state=UNDEFINED |
|
| 115eventq_index=0 116hit_latency=2 | 131eventq_index=0 132hit_latency=2 |
| 133p_state_clk_gate_bins=20 134p_state_clk_gate_max=1000000000000 135p_state_clk_gate_min=1000 136power_model=Null |
|
| 117sequential_access=false 118size=262144 119 120[system.cpu.dtb] 121type=MipsTLB 122eventq_index=0 123size=64 124 125[system.cpu.icache] 126type=Cache 127children=tags 128addr_ranges=0:18446744073709551615 129assoc=2 130clk_domain=system.cpu_clk_domain 131clusivity=mostly_incl | 137sequential_access=false 138size=262144 139 140[system.cpu.dtb] 141type=MipsTLB 142eventq_index=0 143size=64 144 145[system.cpu.icache] 146type=Cache 147children=tags 148addr_ranges=0:18446744073709551615 149assoc=2 150clk_domain=system.cpu_clk_domain 151clusivity=mostly_incl |
| 152default_p_state=UNDEFINED |
|
| 132demand_mshr_reserve=1 133eventq_index=0 134hit_latency=2 135is_read_only=true 136max_miss_count=0 137mshrs=4 | 153demand_mshr_reserve=1 154eventq_index=0 155hit_latency=2 156is_read_only=true 157max_miss_count=0 158mshrs=4 |
| 159p_state_clk_gate_bins=20 160p_state_clk_gate_max=1000000000000 161p_state_clk_gate_min=1000 162power_model=Null |
|
| 138prefetch_on_access=false 139prefetcher=Null 140response_latency=2 141sequential_access=false 142size=131072 143system=system 144tags=system.cpu.icache.tags 145tgts_per_mshr=20 146write_buffers=8 147writeback_clean=true 148cpu_side=system.cpu.icache_port 149mem_side=system.cpu.toL2Bus.slave[0] 150 151[system.cpu.icache.tags] 152type=LRU 153assoc=2 154block_size=64 155clk_domain=system.cpu_clk_domain | 163prefetch_on_access=false 164prefetcher=Null 165response_latency=2 166sequential_access=false 167size=131072 168system=system 169tags=system.cpu.icache.tags 170tgts_per_mshr=20 171write_buffers=8 172writeback_clean=true 173cpu_side=system.cpu.icache_port 174mem_side=system.cpu.toL2Bus.slave[0] 175 176[system.cpu.icache.tags] 177type=LRU 178assoc=2 179block_size=64 180clk_domain=system.cpu_clk_domain |
| 181default_p_state=UNDEFINED |
|
| 156eventq_index=0 157hit_latency=2 | 182eventq_index=0 183hit_latency=2 |
| 184p_state_clk_gate_bins=20 185p_state_clk_gate_max=1000000000000 186p_state_clk_gate_min=1000 187power_model=Null |
|
| 158sequential_access=false 159size=131072 160 161[system.cpu.interrupts] 162type=MipsInterrupts 163eventq_index=0 164 165[system.cpu.isa] --- 10 unchanged lines hidden (view full) --- 176 177[system.cpu.l2cache] 178type=Cache 179children=tags 180addr_ranges=0:18446744073709551615 181assoc=8 182clk_domain=system.cpu_clk_domain 183clusivity=mostly_incl | 188sequential_access=false 189size=131072 190 191[system.cpu.interrupts] 192type=MipsInterrupts 193eventq_index=0 194 195[system.cpu.isa] --- 10 unchanged lines hidden (view full) --- 206 207[system.cpu.l2cache] 208type=Cache 209children=tags 210addr_ranges=0:18446744073709551615 211assoc=8 212clk_domain=system.cpu_clk_domain 213clusivity=mostly_incl |
| 214default_p_state=UNDEFINED |
|
| 184demand_mshr_reserve=1 185eventq_index=0 186hit_latency=20 187is_read_only=false 188max_miss_count=0 189mshrs=20 | 215demand_mshr_reserve=1 216eventq_index=0 217hit_latency=20 218is_read_only=false 219max_miss_count=0 220mshrs=20 |
| 221p_state_clk_gate_bins=20 222p_state_clk_gate_max=1000000000000 223p_state_clk_gate_min=1000 224power_model=Null |
|
| 190prefetch_on_access=false 191prefetcher=Null 192response_latency=20 193sequential_access=false 194size=2097152 195system=system 196tags=system.cpu.l2cache.tags 197tgts_per_mshr=12 198write_buffers=8 199writeback_clean=false 200cpu_side=system.cpu.toL2Bus.master[0] 201mem_side=system.membus.slave[1] 202 203[system.cpu.l2cache.tags] 204type=LRU 205assoc=8 206block_size=64 207clk_domain=system.cpu_clk_domain | 225prefetch_on_access=false 226prefetcher=Null 227response_latency=20 228sequential_access=false 229size=2097152 230system=system 231tags=system.cpu.l2cache.tags 232tgts_per_mshr=12 233write_buffers=8 234writeback_clean=false 235cpu_side=system.cpu.toL2Bus.master[0] 236mem_side=system.membus.slave[1] 237 238[system.cpu.l2cache.tags] 239type=LRU 240assoc=8 241block_size=64 242clk_domain=system.cpu_clk_domain |
| 243default_p_state=UNDEFINED |
|
| 208eventq_index=0 209hit_latency=20 | 244eventq_index=0 245hit_latency=20 |
| 246p_state_clk_gate_bins=20 247p_state_clk_gate_max=1000000000000 248p_state_clk_gate_min=1000 249power_model=Null |
|
| 210sequential_access=false 211size=2097152 212 213[system.cpu.toL2Bus] 214type=CoherentXBar 215children=snoop_filter 216clk_domain=system.cpu_clk_domain | 250sequential_access=false 251size=2097152 252 253[system.cpu.toL2Bus] 254type=CoherentXBar 255children=snoop_filter 256clk_domain=system.cpu_clk_domain |
| 257default_p_state=UNDEFINED |
|
| 217eventq_index=0 218forward_latency=0 219frontend_latency=1 | 258eventq_index=0 259forward_latency=0 260frontend_latency=1 |
| 261p_state_clk_gate_bins=20 262p_state_clk_gate_max=1000000000000 263p_state_clk_gate_min=1000 |
|
| 220point_of_coherency=false | 264point_of_coherency=false |
| 265power_model=Null |
|
| 221response_latency=1 222snoop_filter=system.cpu.toL2Bus.snoop_filter 223snoop_response_latency=1 224system=system 225use_default_range=false 226width=32 227master=system.cpu.l2cache.cpu_side 228slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 14 unchanged lines hidden (view full) --- 243cmd=hello 244cwd= 245drivers= 246egid=100 247env= 248errout=cerr 249euid=100 250eventq_index=0 | 266response_latency=1 267snoop_filter=system.cpu.toL2Bus.snoop_filter 268snoop_response_latency=1 269system=system 270use_default_range=false 271width=32 272master=system.cpu.l2cache.cpu_side 273slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side --- 14 unchanged lines hidden (view full) --- 288cmd=hello 289cwd= 290drivers= 291egid=100 292env= 293errout=cerr 294euid=100 295eventq_index=0 |
| 251executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello | 296executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/mips/linux/hello |
| 252gid=100 253input=cin 254kvmInSE=false 255max_stack_size=67108864 256output=cout 257pid=100 258ppid=99 259simpoint=0 --- 15 unchanged lines hidden (view full) --- 275enable=false 276eventq_index=0 277sys_clk_domain=system.clk_domain 278transition_latency=100000000 279 280[system.membus] 281type=CoherentXBar 282clk_domain=system.clk_domain | 297gid=100 298input=cin 299kvmInSE=false 300max_stack_size=67108864 301output=cout 302pid=100 303ppid=99 304simpoint=0 --- 15 unchanged lines hidden (view full) --- 320enable=false 321eventq_index=0 322sys_clk_domain=system.clk_domain 323transition_latency=100000000 324 325[system.membus] 326type=CoherentXBar 327clk_domain=system.clk_domain |
| 328default_p_state=UNDEFINED |
|
| 283eventq_index=0 284forward_latency=4 285frontend_latency=3 | 329eventq_index=0 330forward_latency=4 331frontend_latency=3 |
| 332p_state_clk_gate_bins=20 333p_state_clk_gate_max=1000000000000 334p_state_clk_gate_min=1000 |
|
| 286point_of_coherency=true | 335point_of_coherency=true |
| 336power_model=Null |
|
| 287response_latency=2 288snoop_filter=Null 289snoop_response_latency=4 290system=system 291use_default_range=false 292width=16 293master=system.physmem.port 294slave=system.system_port system.cpu.l2cache.mem_side 295 296[system.physmem] 297type=SimpleMemory 298bandwidth=73.000000 299clk_domain=system.clk_domain 300conf_table_reported=true | 337response_latency=2 338snoop_filter=Null 339snoop_response_latency=4 340system=system 341use_default_range=false 342width=16 343master=system.physmem.port 344slave=system.system_port system.cpu.l2cache.mem_side 345 346[system.physmem] 347type=SimpleMemory 348bandwidth=73.000000 349clk_domain=system.clk_domain 350conf_table_reported=true |
| 351default_p_state=UNDEFINED |
|
| 301eventq_index=0 302in_addr_map=true 303latency=30000 304latency_var=0 305null=false | 352eventq_index=0 353in_addr_map=true 354latency=30000 355latency_var=0 356null=false |
| 357p_state_clk_gate_bins=20 358p_state_clk_gate_max=1000000000000 359p_state_clk_gate_min=1000 360power_model=Null |
|
| 306range=0:134217727 307port=system.membus.master[0] 308 309[system.voltage_domain] 310type=VoltageDomain 311eventq_index=0 312voltage=1.000000 313 | 361range=0:134217727 362port=system.membus.master[0] 363 364[system.voltage_domain] 365type=VoltageDomain 366eventq_index=0 367voltage=1.000000 368 |