1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 9 unchanged lines hidden (view full) ---

18init_param=0
19kernel=
20kernel_addr_check=true
21load_addr_mask=1099511627775
22load_offset=0
23mem_mode=atomic
24mem_ranges=
25memories=system.physmem
26num_work_ids=16
27readfile=
28symbolfile=
29work_begin_ckpt_count=0
30work_begin_cpu_id_exit=-1
31work_begin_exit_count=0
32work_cpus_ckpt_count=0
33work_end_ckpt_count=0

--- 83 unchanged lines hidden (view full) ---

117warnOnlyOnLoadError=true
118workload=system.cpu.workload
119
120[system.cpu.checker.dstage2_mmu]
121type=ArmStage2MMU
122children=stage2_tlb
123eventq_index=0
124stage2_tlb=system.cpu.checker.dstage2_mmu.stage2_tlb
125tlb=system.cpu.checker.dtb
126
127[system.cpu.checker.dstage2_mmu.stage2_tlb]
128type=ArmTLB
129children=walker
130eventq_index=0
131is_stage2=true
132size=32

--- 45 unchanged lines hidden (view full) ---

178id_isar5=0
179id_mmfr0=270536963
180id_mmfr1=0
181id_mmfr2=19070976
182id_mmfr3=34611729
183id_pfr0=49
184id_pfr1=4113
185midr=1091551472
186system=system
187
188[system.cpu.checker.istage2_mmu]
189type=ArmStage2MMU
190children=stage2_tlb
191eventq_index=0
192stage2_tlb=system.cpu.checker.istage2_mmu.stage2_tlb
193tlb=system.cpu.checker.itb
194
195[system.cpu.checker.istage2_mmu.stage2_tlb]
196type=ArmTLB
197children=walker
198eventq_index=0
199is_stage2=true
200size=32

--- 27 unchanged lines hidden (view full) ---

228type=ExeTracer
229eventq_index=0
230
231[system.cpu.dstage2_mmu]
232type=ArmStage2MMU
233children=stage2_tlb
234eventq_index=0
235stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
236tlb=system.cpu.dtb
237
238[system.cpu.dstage2_mmu.stage2_tlb]
239type=ArmTLB
240children=walker
241eventq_index=0
242is_stage2=true
243size=32
244walker=system.cpu.dstage2_mmu.stage2_tlb.walker
245
246[system.cpu.dstage2_mmu.stage2_tlb.walker]
247type=ArmTableWalker
248clk_domain=system.cpu_clk_domain
249eventq_index=0
250is_stage2=true
251num_squash_per_cycle=2
252sys=system
253port=system.membus.slave[6]
254
255[system.cpu.dtb]
256type=ArmTLB
257children=walker
258eventq_index=0
259is_stage2=false
260size=64
261walker=system.cpu.dtb.walker

--- 33 unchanged lines hidden (view full) ---

295id_isar5=0
296id_mmfr0=270536963
297id_mmfr1=0
298id_mmfr2=19070976
299id_mmfr3=34611729
300id_pfr0=49
301id_pfr1=4113
302midr=1091551472
303system=system
304
305[system.cpu.istage2_mmu]
306type=ArmStage2MMU
307children=stage2_tlb
308eventq_index=0
309stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
310tlb=system.cpu.itb
311
312[system.cpu.istage2_mmu.stage2_tlb]
313type=ArmTLB
314children=walker
315eventq_index=0
316is_stage2=true
317size=32
318walker=system.cpu.istage2_mmu.stage2_tlb.walker
319
320[system.cpu.istage2_mmu.stage2_tlb.walker]
321type=ArmTableWalker
322clk_domain=system.cpu_clk_domain
323eventq_index=0
324is_stage2=true
325num_squash_per_cycle=2
326sys=system
327port=system.membus.slave[5]
328
329[system.cpu.itb]
330type=ArmTLB
331children=walker
332eventq_index=0
333is_stage2=false
334size=64
335walker=system.cpu.itb.walker

--- 10 unchanged lines hidden (view full) ---

346[system.cpu.tracer]
347type=ExeTracer
348eventq_index=0
349
350[system.cpu.workload]
351type=LiveProcess
352cmd=hello
353cwd=
354egid=100
355env=
356errout=cerr
357euid=100
358eventq_index=0
359executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
360gid=100
361input=cin
362max_stack_size=67108864
363output=cout
364pid=100
365ppid=99
366simpoint=0
367system=system
368uid=100
369useArchPT=false

--- 13 unchanged lines hidden (view full) ---

383eventq_index=0
384sys_clk_domain=system.clk_domain
385transition_latency=100000000
386
387[system.membus]
388type=CoherentXBar
389clk_domain=system.clk_domain
390eventq_index=0
391header_cycles=1
392snoop_filter=Null
393system=system
394use_default_range=false
395width=8
396master=system.physmem.port
397slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
398
399[system.physmem]
400type=SimpleMemory
401bandwidth=73.000000
402clk_domain=system.clk_domain
403conf_table_reported=true
404eventq_index=0
405in_addr_map=true
406latency=30000
407latency_var=0
408null=false
409range=0:134217727
410port=system.membus.master[0]
411
412[system.voltage_domain]
413type=VoltageDomain
414eventq_index=0
415voltage=1.000000
416