| config.ini (11440:76b5639162af) | config.ini (11570:4aac82f10951) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17default_p_state=UNDEFINED |
|
| 17eventq_index=0 18exit_on_work_items=false 19init_param=0 20kernel= 21kernel_addr_check=true 22load_addr_mask=1099511627775 23load_offset=0 24mem_mode=timing 25mem_ranges= 26memories=system.physmem 27mmap_using_noreserve=false 28multi_thread=false 29num_work_ids=16 | 18eventq_index=0 19exit_on_work_items=false 20init_param=0 21kernel= 22kernel_addr_check=true 23load_addr_mask=1099511627775 24load_offset=0 25mem_mode=timing 26mem_ranges= 27memories=system.physmem 28mmap_using_noreserve=false 29multi_thread=false 30num_work_ids=16 |
| 31p_state_clk_gate_bins=20 32p_state_clk_gate_max=1000000000000 33p_state_clk_gate_min=1000 34power_model=Null |
|
| 30readfile= 31symbolfile= 32thermal_components= 33thermal_model=Null 34work_begin_ckpt_count=0 35work_begin_cpu_id_exit=-1 36work_begin_exit_count=0 37work_cpus_ckpt_count=0 --- 16 unchanged lines hidden (view full) --- 54branchPred=system.cpu.branchPred 55checker=Null 56clk_domain=system.cpu_clk_domain 57cpu_id=0 58decodeCycleInput=true 59decodeInputBufferSize=3 60decodeInputWidth=2 61decodeToExecuteForwardDelay=1 | 35readfile= 36symbolfile= 37thermal_components= 38thermal_model=Null 39work_begin_ckpt_count=0 40work_begin_cpu_id_exit=-1 41work_begin_exit_count=0 42work_cpus_ckpt_count=0 --- 16 unchanged lines hidden (view full) --- 59branchPred=system.cpu.branchPred 60checker=Null 61clk_domain=system.cpu_clk_domain 62cpu_id=0 63decodeCycleInput=true 64decodeInputBufferSize=3 65decodeInputWidth=2 66decodeToExecuteForwardDelay=1 |
| 67default_p_state=UNDEFINED |
|
| 62do_checkpoint_insts=true 63do_quiesce=true 64do_statistics_insts=true 65dstage2_mmu=system.cpu.dstage2_mmu 66dtb=system.cpu.dtb 67enableIdling=true 68eventq_index=0 69executeAllowEarlyMemoryIssue=true --- 28 unchanged lines hidden (view full) --- 98isa=system.cpu.isa 99istage2_mmu=system.cpu.istage2_mmu 100itb=system.cpu.itb 101max_insts_all_threads=0 102max_insts_any_thread=0 103max_loads_all_threads=0 104max_loads_any_thread=0 105numThreads=1 | 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dstage2_mmu=system.cpu.dstage2_mmu 72dtb=system.cpu.dtb 73enableIdling=true 74eventq_index=0 75executeAllowEarlyMemoryIssue=true --- 28 unchanged lines hidden (view full) --- 104isa=system.cpu.isa 105istage2_mmu=system.cpu.istage2_mmu 106itb=system.cpu.itb 107max_insts_all_threads=0 108max_insts_any_thread=0 109max_loads_all_threads=0 110max_loads_any_thread=0 111numThreads=1 |
| 112p_state_clk_gate_bins=20 113p_state_clk_gate_max=1000000000000 114p_state_clk_gate_min=1000 115power_model=Null |
|
| 106profile=0 107progress_interval=0 108simpoint_start_insts= 109socket_id=0 110switched_out=false 111system=system | 116profile=0 117progress_interval=0 118simpoint_start_insts= 119socket_id=0 120switched_out=false 121system=system |
| 122threadPolicy=RoundRobin |
|
| 112tracer=system.cpu.tracer 113workload=system.cpu.workload 114dcache_port=system.cpu.dcache.cpu_side 115icache_port=system.cpu.icache.cpu_side 116 117[system.cpu.branchPred] 118type=TournamentBP 119BTBEntries=4096 --- 19 unchanged lines hidden (view full) --- 139 140[system.cpu.dcache] 141type=Cache 142children=tags 143addr_ranges=0:18446744073709551615 144assoc=2 145clk_domain=system.cpu_clk_domain 146clusivity=mostly_incl | 123tracer=system.cpu.tracer 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.branchPred] 129type=TournamentBP 130BTBEntries=4096 --- 19 unchanged lines hidden (view full) --- 150 151[system.cpu.dcache] 152type=Cache 153children=tags 154addr_ranges=0:18446744073709551615 155assoc=2 156clk_domain=system.cpu_clk_domain 157clusivity=mostly_incl |
| 158default_p_state=UNDEFINED |
|
| 147demand_mshr_reserve=1 148eventq_index=0 149hit_latency=2 150is_read_only=false 151max_miss_count=0 152mshrs=4 | 159demand_mshr_reserve=1 160eventq_index=0 161hit_latency=2 162is_read_only=false 163max_miss_count=0 164mshrs=4 |
| 165p_state_clk_gate_bins=20 166p_state_clk_gate_max=1000000000000 167p_state_clk_gate_min=1000 168power_model=Null |
|
| 153prefetch_on_access=false 154prefetcher=Null 155response_latency=2 156sequential_access=false 157size=262144 158system=system 159tags=system.cpu.dcache.tags 160tgts_per_mshr=20 161write_buffers=8 162writeback_clean=false 163cpu_side=system.cpu.dcache_port 164mem_side=system.cpu.toL2Bus.slave[1] 165 166[system.cpu.dcache.tags] 167type=LRU 168assoc=2 169block_size=64 170clk_domain=system.cpu_clk_domain | 169prefetch_on_access=false 170prefetcher=Null 171response_latency=2 172sequential_access=false 173size=262144 174system=system 175tags=system.cpu.dcache.tags 176tgts_per_mshr=20 177write_buffers=8 178writeback_clean=false 179cpu_side=system.cpu.dcache_port 180mem_side=system.cpu.toL2Bus.slave[1] 181 182[system.cpu.dcache.tags] 183type=LRU 184assoc=2 185block_size=64 186clk_domain=system.cpu_clk_domain |
| 187default_p_state=UNDEFINED |
|
| 171eventq_index=0 172hit_latency=2 | 188eventq_index=0 189hit_latency=2 |
| 190p_state_clk_gate_bins=20 191p_state_clk_gate_max=1000000000000 192p_state_clk_gate_min=1000 193power_model=Null |
|
| 173sequential_access=false 174size=262144 175 176[system.cpu.dstage2_mmu] 177type=ArmStage2MMU 178children=stage2_tlb 179eventq_index=0 180stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb --- 6 unchanged lines hidden (view full) --- 187eventq_index=0 188is_stage2=true 189size=32 190walker=system.cpu.dstage2_mmu.stage2_tlb.walker 191 192[system.cpu.dstage2_mmu.stage2_tlb.walker] 193type=ArmTableWalker 194clk_domain=system.cpu_clk_domain | 194sequential_access=false 195size=262144 196 197[system.cpu.dstage2_mmu] 198type=ArmStage2MMU 199children=stage2_tlb 200eventq_index=0 201stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb --- 6 unchanged lines hidden (view full) --- 208eventq_index=0 209is_stage2=true 210size=32 211walker=system.cpu.dstage2_mmu.stage2_tlb.walker 212 213[system.cpu.dstage2_mmu.stage2_tlb.walker] 214type=ArmTableWalker 215clk_domain=system.cpu_clk_domain |
| 216default_p_state=UNDEFINED |
|
| 195eventq_index=0 196is_stage2=true 197num_squash_per_cycle=2 | 217eventq_index=0 218is_stage2=true 219num_squash_per_cycle=2 |
| 220p_state_clk_gate_bins=20 221p_state_clk_gate_max=1000000000000 222p_state_clk_gate_min=1000 223power_model=Null |
|
| 198sys=system 199 200[system.cpu.dtb] 201type=ArmTLB 202children=walker 203eventq_index=0 204is_stage2=false 205size=64 206walker=system.cpu.dtb.walker 207 208[system.cpu.dtb.walker] 209type=ArmTableWalker 210clk_domain=system.cpu_clk_domain | 224sys=system 225 226[system.cpu.dtb] 227type=ArmTLB 228children=walker 229eventq_index=0 230is_stage2=false 231size=64 232walker=system.cpu.dtb.walker 233 234[system.cpu.dtb.walker] 235type=ArmTableWalker 236clk_domain=system.cpu_clk_domain |
| 237default_p_state=UNDEFINED |
|
| 211eventq_index=0 212is_stage2=false 213num_squash_per_cycle=2 | 238eventq_index=0 239is_stage2=false 240num_squash_per_cycle=2 |
| 241p_state_clk_gate_bins=20 242p_state_clk_gate_max=1000000000000 243p_state_clk_gate_min=1000 244power_model=Null |
|
| 214sys=system 215port=system.cpu.toL2Bus.slave[3] 216 217[system.cpu.executeFuncUnits] 218type=MinorFUPool 219children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 220eventq_index=0 221funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 --- 377 unchanged lines hidden (view full) --- 599 600[system.cpu.icache] 601type=Cache 602children=tags 603addr_ranges=0:18446744073709551615 604assoc=2 605clk_domain=system.cpu_clk_domain 606clusivity=mostly_incl | 245sys=system 246port=system.cpu.toL2Bus.slave[3] 247 248[system.cpu.executeFuncUnits] 249type=MinorFUPool 250children=funcUnits0 funcUnits1 funcUnits2 funcUnits3 funcUnits4 funcUnits5 funcUnits6 251eventq_index=0 252funcUnits=system.cpu.executeFuncUnits.funcUnits0 system.cpu.executeFuncUnits.funcUnits1 system.cpu.executeFuncUnits.funcUnits2 system.cpu.executeFuncUnits.funcUnits3 system.cpu.executeFuncUnits.funcUnits4 system.cpu.executeFuncUnits.funcUnits5 system.cpu.executeFuncUnits.funcUnits6 --- 377 unchanged lines hidden (view full) --- 630 631[system.cpu.icache] 632type=Cache 633children=tags 634addr_ranges=0:18446744073709551615 635assoc=2 636clk_domain=system.cpu_clk_domain 637clusivity=mostly_incl |
| 638default_p_state=UNDEFINED |
|
| 607demand_mshr_reserve=1 608eventq_index=0 609hit_latency=2 610is_read_only=true 611max_miss_count=0 612mshrs=4 | 639demand_mshr_reserve=1 640eventq_index=0 641hit_latency=2 642is_read_only=true 643max_miss_count=0 644mshrs=4 |
| 645p_state_clk_gate_bins=20 646p_state_clk_gate_max=1000000000000 647p_state_clk_gate_min=1000 648power_model=Null |
|
| 613prefetch_on_access=false 614prefetcher=Null 615response_latency=2 616sequential_access=false 617size=131072 618system=system 619tags=system.cpu.icache.tags 620tgts_per_mshr=20 621write_buffers=8 622writeback_clean=true 623cpu_side=system.cpu.icache_port 624mem_side=system.cpu.toL2Bus.slave[0] 625 626[system.cpu.icache.tags] 627type=LRU 628assoc=2 629block_size=64 630clk_domain=system.cpu_clk_domain | 649prefetch_on_access=false 650prefetcher=Null 651response_latency=2 652sequential_access=false 653size=131072 654system=system 655tags=system.cpu.icache.tags 656tgts_per_mshr=20 657write_buffers=8 658writeback_clean=true 659cpu_side=system.cpu.icache_port 660mem_side=system.cpu.toL2Bus.slave[0] 661 662[system.cpu.icache.tags] 663type=LRU 664assoc=2 665block_size=64 666clk_domain=system.cpu_clk_domain |
| 667default_p_state=UNDEFINED |
|
| 631eventq_index=0 632hit_latency=2 | 668eventq_index=0 669hit_latency=2 |
| 670p_state_clk_gate_bins=20 671p_state_clk_gate_max=1000000000000 672p_state_clk_gate_min=1000 673power_model=Null |
|
| 633sequential_access=false 634size=131072 635 636[system.cpu.interrupts] 637type=ArmInterrupts 638eventq_index=0 639 640[system.cpu.isa] --- 41 unchanged lines hidden (view full) --- 682eventq_index=0 683is_stage2=true 684size=32 685walker=system.cpu.istage2_mmu.stage2_tlb.walker 686 687[system.cpu.istage2_mmu.stage2_tlb.walker] 688type=ArmTableWalker 689clk_domain=system.cpu_clk_domain | 674sequential_access=false 675size=131072 676 677[system.cpu.interrupts] 678type=ArmInterrupts 679eventq_index=0 680 681[system.cpu.isa] --- 41 unchanged lines hidden (view full) --- 723eventq_index=0 724is_stage2=true 725size=32 726walker=system.cpu.istage2_mmu.stage2_tlb.walker 727 728[system.cpu.istage2_mmu.stage2_tlb.walker] 729type=ArmTableWalker 730clk_domain=system.cpu_clk_domain |
| 731default_p_state=UNDEFINED |
|
| 690eventq_index=0 691is_stage2=true 692num_squash_per_cycle=2 | 732eventq_index=0 733is_stage2=true 734num_squash_per_cycle=2 |
| 735p_state_clk_gate_bins=20 736p_state_clk_gate_max=1000000000000 737p_state_clk_gate_min=1000 738power_model=Null |
|
| 693sys=system 694 695[system.cpu.itb] 696type=ArmTLB 697children=walker 698eventq_index=0 699is_stage2=false 700size=64 701walker=system.cpu.itb.walker 702 703[system.cpu.itb.walker] 704type=ArmTableWalker 705clk_domain=system.cpu_clk_domain | 739sys=system 740 741[system.cpu.itb] 742type=ArmTLB 743children=walker 744eventq_index=0 745is_stage2=false 746size=64 747walker=system.cpu.itb.walker 748 749[system.cpu.itb.walker] 750type=ArmTableWalker 751clk_domain=system.cpu_clk_domain |
| 752default_p_state=UNDEFINED |
|
| 706eventq_index=0 707is_stage2=false 708num_squash_per_cycle=2 | 753eventq_index=0 754is_stage2=false 755num_squash_per_cycle=2 |
| 756p_state_clk_gate_bins=20 757p_state_clk_gate_max=1000000000000 758p_state_clk_gate_min=1000 759power_model=Null |
|
| 709sys=system 710port=system.cpu.toL2Bus.slave[2] 711 712[system.cpu.l2cache] 713type=Cache 714children=tags 715addr_ranges=0:18446744073709551615 716assoc=8 717clk_domain=system.cpu_clk_domain 718clusivity=mostly_incl | 760sys=system 761port=system.cpu.toL2Bus.slave[2] 762 763[system.cpu.l2cache] 764type=Cache 765children=tags 766addr_ranges=0:18446744073709551615 767assoc=8 768clk_domain=system.cpu_clk_domain 769clusivity=mostly_incl |
| 770default_p_state=UNDEFINED |
|
| 719demand_mshr_reserve=1 720eventq_index=0 721hit_latency=20 722is_read_only=false 723max_miss_count=0 724mshrs=20 | 771demand_mshr_reserve=1 772eventq_index=0 773hit_latency=20 774is_read_only=false 775max_miss_count=0 776mshrs=20 |
| 777p_state_clk_gate_bins=20 778p_state_clk_gate_max=1000000000000 779p_state_clk_gate_min=1000 780power_model=Null |
|
| 725prefetch_on_access=false 726prefetcher=Null 727response_latency=20 728sequential_access=false 729size=2097152 730system=system 731tags=system.cpu.l2cache.tags 732tgts_per_mshr=12 733write_buffers=8 734writeback_clean=false 735cpu_side=system.cpu.toL2Bus.master[0] 736mem_side=system.membus.slave[1] 737 738[system.cpu.l2cache.tags] 739type=LRU 740assoc=8 741block_size=64 742clk_domain=system.cpu_clk_domain | 781prefetch_on_access=false 782prefetcher=Null 783response_latency=20 784sequential_access=false 785size=2097152 786system=system 787tags=system.cpu.l2cache.tags 788tgts_per_mshr=12 789write_buffers=8 790writeback_clean=false 791cpu_side=system.cpu.toL2Bus.master[0] 792mem_side=system.membus.slave[1] 793 794[system.cpu.l2cache.tags] 795type=LRU 796assoc=8 797block_size=64 798clk_domain=system.cpu_clk_domain |
| 799default_p_state=UNDEFINED |
|
| 743eventq_index=0 744hit_latency=20 | 800eventq_index=0 801hit_latency=20 |
| 802p_state_clk_gate_bins=20 803p_state_clk_gate_max=1000000000000 804p_state_clk_gate_min=1000 805power_model=Null |
|
| 745sequential_access=false 746size=2097152 747 748[system.cpu.toL2Bus] 749type=CoherentXBar 750children=snoop_filter 751clk_domain=system.cpu_clk_domain | 806sequential_access=false 807size=2097152 808 809[system.cpu.toL2Bus] 810type=CoherentXBar 811children=snoop_filter 812clk_domain=system.cpu_clk_domain |
| 813default_p_state=UNDEFINED |
|
| 752eventq_index=0 753forward_latency=0 754frontend_latency=1 | 814eventq_index=0 815forward_latency=0 816frontend_latency=1 |
| 817p_state_clk_gate_bins=20 818p_state_clk_gate_max=1000000000000 819p_state_clk_gate_min=1000 |
|
| 755point_of_coherency=false | 820point_of_coherency=false |
| 821power_model=Null |
|
| 756response_latency=1 757snoop_filter=system.cpu.toL2Bus.snoop_filter 758snoop_response_latency=1 759system=system 760use_default_range=false 761width=32 762master=system.cpu.l2cache.cpu_side 763slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port --- 14 unchanged lines hidden (view full) --- 778cmd=hello 779cwd= 780drivers= 781egid=100 782env= 783errout=cerr 784euid=100 785eventq_index=0 | 822response_latency=1 823snoop_filter=system.cpu.toL2Bus.snoop_filter 824snoop_response_latency=1 825system=system 826use_default_range=false 827width=32 828master=system.cpu.l2cache.cpu_side 829slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port --- 14 unchanged lines hidden (view full) --- 844cmd=hello 845cwd= 846drivers= 847egid=100 848env= 849errout=cerr 850euid=100 851eventq_index=0 |
| 786executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello | 852executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/arm/linux/hello |
| 787gid=100 788input=cin 789kvmInSE=false 790max_stack_size=67108864 791output=cout 792pid=100 793ppid=99 794simpoint=0 --- 15 unchanged lines hidden (view full) --- 810enable=false 811eventq_index=0 812sys_clk_domain=system.clk_domain 813transition_latency=100000000 814 815[system.membus] 816type=CoherentXBar 817clk_domain=system.clk_domain | 853gid=100 854input=cin 855kvmInSE=false 856max_stack_size=67108864 857output=cout 858pid=100 859ppid=99 860simpoint=0 --- 15 unchanged lines hidden (view full) --- 876enable=false 877eventq_index=0 878sys_clk_domain=system.clk_domain 879transition_latency=100000000 880 881[system.membus] 882type=CoherentXBar 883clk_domain=system.clk_domain |
| 884default_p_state=UNDEFINED |
|
| 818eventq_index=0 819forward_latency=4 820frontend_latency=3 | 885eventq_index=0 886forward_latency=4 887frontend_latency=3 |
| 888p_state_clk_gate_bins=20 889p_state_clk_gate_max=1000000000000 890p_state_clk_gate_min=1000 |
|
| 821point_of_coherency=true | 891point_of_coherency=true |
| 892power_model=Null |
|
| 822response_latency=2 823snoop_filter=Null 824snoop_response_latency=4 825system=system 826use_default_range=false 827width=16 828master=system.physmem.port 829slave=system.system_port system.cpu.l2cache.mem_side --- 27 unchanged lines hidden (view full) --- 857activation_limit=4 858addr_mapping=RoRaBaCoCh 859bank_groups_per_rank=0 860banks_per_rank=8 861burst_length=8 862channels=1 863clk_domain=system.clk_domain 864conf_table_reported=true | 893response_latency=2 894snoop_filter=Null 895snoop_response_latency=4 896system=system 897use_default_range=false 898width=16 899master=system.physmem.port 900slave=system.system_port system.cpu.l2cache.mem_side --- 27 unchanged lines hidden (view full) --- 928activation_limit=4 929addr_mapping=RoRaBaCoCh 930bank_groups_per_rank=0 931banks_per_rank=8 932burst_length=8 933channels=1 934clk_domain=system.clk_domain 935conf_table_reported=true |
| 936default_p_state=UNDEFINED |
|
| 865device_bus_width=8 866device_rowbuffer_size=1024 867device_size=536870912 868devices_per_rank=8 869dll=true 870eventq_index=0 871in_addr_map=true 872max_accesses_per_row=16 873mem_sched_policy=frfcfs 874min_writes_per_switch=16 875null=false | 937device_bus_width=8 938device_rowbuffer_size=1024 939device_size=536870912 940devices_per_rank=8 941dll=true 942eventq_index=0 943in_addr_map=true 944max_accesses_per_row=16 945mem_sched_policy=frfcfs 946min_writes_per_switch=16 947null=false |
| 948p_state_clk_gate_bins=20 949p_state_clk_gate_max=1000000000000 950p_state_clk_gate_min=1000 |
|
| 876page_policy=open_adaptive | 951page_policy=open_adaptive |
| 952power_model=Null |
|
| 877range=0:134217727 878ranks_per_channel=2 879read_buffer_size=32 880static_backend_latency=10000 881static_frontend_latency=10000 882tBURST=5000 883tCCD_L=0 884tCK=1250 --- 28 unchanged lines hidden --- | 953range=0:134217727 954ranks_per_channel=2 955read_buffer_size=32 956static_backend_latency=10000 957static_frontend_latency=10000 958tBURST=5000 959tCCD_L=0 960tCK=1250 --- 28 unchanged lines hidden --- |