25a26
> mmap_using_noreserve=false
169a171
> sys=system
187d188
< port=system.cpu.toL2Bus.slave[5]
663a665
> sys=system
681d682
< port=system.cpu.toL2Bus.slave[4]
740c741,743
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
741a745
> snoop_response_latency=1
746c750
< slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
795c799,801
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
796a803
> snoop_response_latency=4
799c806
< width=8
---
> width=16
830c837
< addr_mapping=RoRaBaChCo
---
> addr_mapping=RoRaBaCoCh