1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 9 unchanged lines hidden (view full) ---

18init_param=0
19kernel=
20kernel_addr_check=true
21load_addr_mask=1099511627775
22load_offset=0
23mem_mode=timing
24mem_ranges=
25memories=system.physmem
26num_work_ids=16
27readfile=
28symbolfile=
29work_begin_ckpt_count=0
30work_begin_cpu_id_exit=-1
31work_begin_exit_count=0
32work_cpus_ckpt_count=0
33work_end_ckpt_count=0

--- 128 unchanged lines hidden (view full) ---

162sequential_access=false
163size=262144
164
165[system.cpu.dstage2_mmu]
166type=ArmStage2MMU
167children=stage2_tlb
168eventq_index=0
169stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
170tlb=system.cpu.dtb
171
172[system.cpu.dstage2_mmu.stage2_tlb]
173type=ArmTLB
174children=walker
175eventq_index=0
176is_stage2=true
177size=32
178walker=system.cpu.dstage2_mmu.stage2_tlb.walker
179
180[system.cpu.dstage2_mmu.stage2_tlb.walker]
181type=ArmTableWalker
182clk_domain=system.cpu_clk_domain
183eventq_index=0
184is_stage2=true
185num_squash_per_cycle=2
186sys=system
187port=system.cpu.toL2Bus.slave[5]
188
189[system.cpu.dtb]
190type=ArmTLB
191children=walker
192eventq_index=0
193is_stage2=false
194size=64
195walker=system.cpu.dtb.walker

--- 460 unchanged lines hidden (view full) ---

656pmu=Null
657system=system
658
659[system.cpu.istage2_mmu]
660type=ArmStage2MMU
661children=stage2_tlb
662eventq_index=0
663stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
664tlb=system.cpu.itb
665
666[system.cpu.istage2_mmu.stage2_tlb]
667type=ArmTLB
668children=walker
669eventq_index=0
670is_stage2=true
671size=32
672walker=system.cpu.istage2_mmu.stage2_tlb.walker
673
674[system.cpu.istage2_mmu.stage2_tlb.walker]
675type=ArmTableWalker
676clk_domain=system.cpu_clk_domain
677eventq_index=0
678is_stage2=true
679num_squash_per_cycle=2
680sys=system
681port=system.cpu.toL2Bus.slave[4]
682
683[system.cpu.itb]
684type=ArmTLB
685children=walker
686eventq_index=0
687is_stage2=false
688size=64
689walker=system.cpu.itb.walker

--- 42 unchanged lines hidden (view full) ---

732hit_latency=20
733sequential_access=false
734size=2097152
735
736[system.cpu.toL2Bus]
737type=CoherentXBar
738clk_domain=system.cpu_clk_domain
739eventq_index=0
740header_cycles=1
741snoop_filter=Null
742system=system
743use_default_range=false
744width=32
745master=system.cpu.l2cache.cpu_side
746slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
747
748[system.cpu.tracer]
749type=ExeTracer
750eventq_index=0
751
752[system.cpu.workload]
753type=LiveProcess
754cmd=hello

--- 32 unchanged lines hidden (view full) ---

787eventq_index=0
788sys_clk_domain=system.clk_domain
789transition_latency=100000000
790
791[system.membus]
792type=CoherentXBar
793clk_domain=system.clk_domain
794eventq_index=0
795header_cycles=1
796snoop_filter=Null
797system=system
798use_default_range=false
799width=8
800master=system.physmem.port
801slave=system.system_port system.cpu.l2cache.mem_side
802
803[system.physmem]
804type=DRAMCtrl
805IDD0=0.075000
806IDD02=0.000000
807IDD2N=0.050000

--- 14 unchanged lines hidden (view full) ---

822IDD4W2=0.000000
823IDD5=0.220000
824IDD52=0.000000
825IDD6=0.000000
826IDD62=0.000000
827VDD=1.500000
828VDD2=0.000000
829activation_limit=4
830addr_mapping=RoRaBaChCo
831bank_groups_per_rank=0
832banks_per_rank=8
833burst_length=8
834channels=1
835clk_domain=system.clk_domain
836conf_table_reported=true
837device_bus_width=8
838device_rowbuffer_size=1024

--- 46 unchanged lines hidden ---