| stats.txt (9885:afd9ea6101d9) | stats.txt (9962:7aef35367a21) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829332 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829332 # Number of seconds simulated |
| 4sim_ticks 1829332269000 # Number of ticks simulated 5final_tick 1829332269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 1829332258000 # Number of ticks simulated 5final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 2947908 # Simulator instruction rate (inst/s) 8host_op_rate 2947905 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 89820884398 # Simulator tick rate (ticks/s) 10host_mem_usage 305960 # Number of bytes of host memory used 11host_seconds 20.37 # Real time elapsed on the host | 7host_inst_rate 1630624 # Simulator instruction rate (inst/s) 8host_op_rate 1630623 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 49684114233 # Simulator tick rate (ticks/s) 10host_mem_usage 305868 # Number of bytes of host memory used 11host_seconds 36.82 # Real time elapsed on the host |
| 12sim_insts 60038305 # Number of instructions simulated 13sim_ops 60038305 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 17system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory --- 13 unchanged lines hidden (view full) --- 33system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 60038305 # Number of instructions simulated 13sim_ops 60038305 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 17system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory --- 13 unchanged lines hidden (view full) --- 33system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) |
| 41system.physmem.readReqs 0 # Total number of read requests accepted by DRAM controller 42system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 43system.physmem.readBursts 0 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 44system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts 45system.physmem.bytesRead 0 # Total number of bytes read from memory 46system.physmem.bytesWritten 0 # Total number of bytes written to memory 47system.physmem.bytesConsumedRd 0 # bytesRead derated as per pkt->getSize() 48system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 49system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q 50system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 51system.physmem.perBankRdReqs::0 0 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::2 0 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::4 0 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::5 0 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::7 0 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::8 0 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::9 0 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::10 0 # Track reads on a per bank basis 62system.physmem.perBankRdReqs::11 0 # Track reads on a per bank basis 63system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis 64system.physmem.perBankRdReqs::13 0 # Track reads on a per bank basis 65system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 66system.physmem.perBankRdReqs::15 0 # Track reads on a per bank basis 67system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 78system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 79system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 80system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 81system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 82system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 83system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 84system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 85system.physmem.totGap 0 # Total gap between requests 86system.physmem.readPktSize::0 0 # Categorize read packet sizes 87system.physmem.readPktSize::1 0 # Categorize read packet sizes 88system.physmem.readPktSize::2 0 # Categorize read packet sizes 89system.physmem.readPktSize::3 0 # Categorize read packet sizes 90system.physmem.readPktSize::4 0 # Categorize read packet sizes 91system.physmem.readPktSize::5 0 # Categorize read packet sizes 92system.physmem.readPktSize::6 0 # Categorize read packet sizes 93system.physmem.writePktSize::0 0 # Categorize write packet sizes 94system.physmem.writePktSize::1 0 # Categorize write packet sizes 95system.physmem.writePktSize::2 0 # Categorize write packet sizes 96system.physmem.writePktSize::3 0 # Categorize write packet sizes 97system.physmem.writePktSize::4 0 # Categorize write packet sizes 98system.physmem.writePktSize::5 0 # Categorize write packet sizes 99system.physmem.writePktSize::6 0 # Categorize write packet sizes 100system.physmem.rdQLenPdf::0 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 164system.physmem.bytesPerActivate::mean nan # Bytes accessed per row activation 165system.physmem.bytesPerActivate::gmean nan # Bytes accessed per row activation 166system.physmem.bytesPerActivate::stdev nan # Bytes accessed per row activation 167system.physmem.totQLat 0 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 0 # Sum of mem lat for all requests 169system.physmem.totBusLat 0 # Total cycles spent in databus access 170system.physmem.totBankLat 0 # Total cycles spent in bank access 171system.physmem.avgQLat nan # Average queueing delay per request 172system.physmem.avgBankLat nan # Average bank access latency per request 173system.physmem.avgBusLat nan # Average bus latency per request 174system.physmem.avgMemAccLat nan # Average memory access latency 175system.physmem.avgRdBW 0.00 # Average achieved read bandwidth in MB/s 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 177system.physmem.avgConsumedRdBW 0.00 # Average consumed read bandwidth in MB/s 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 0.00 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.00 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 0 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate nan # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 187system.physmem.avgGap nan # Average gap between requests | |
| 188system.membus.throughput 42552540 # Throughput (bytes/s) 189system.membus.data_through_bus 77842734 # Total data (bytes) 190system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 191system.iocache.tags.replacements 41686 # number of replacements 192system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use 193system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 194system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 195system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. --- 75 unchanged lines hidden (view full) --- 271system.cpu.itb.write_hits 0 # DTB write hits 272system.cpu.itb.write_misses 0 # DTB write misses 273system.cpu.itb.write_acv 0 # DTB write access violations 274system.cpu.itb.write_accesses 0 # DTB write accesses 275system.cpu.itb.data_hits 0 # DTB hits 276system.cpu.itb.data_misses 0 # DTB misses 277system.cpu.itb.data_acv 0 # DTB access violations 278system.cpu.itb.data_accesses 0 # DTB accesses | 41system.membus.throughput 42552540 # Throughput (bytes/s) 42system.membus.data_through_bus 77842734 # Total data (bytes) 43system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 44system.iocache.tags.replacements 41686 # number of replacements 45system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use 46system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 47system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 48system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. --- 75 unchanged lines hidden (view full) --- 124system.cpu.itb.write_hits 0 # DTB write hits 125system.cpu.itb.write_misses 0 # DTB write misses 126system.cpu.itb.write_acv 0 # DTB write access violations 127system.cpu.itb.write_accesses 0 # DTB write accesses 128system.cpu.itb.data_hits 0 # DTB hits 129system.cpu.itb.data_misses 0 # DTB misses 130system.cpu.itb.data_acv 0 # DTB access violations 131system.cpu.itb.data_accesses 0 # DTB accesses |
| 279system.cpu.numCycles 3658664430 # number of cpu cycles simulated | 132system.cpu.numCycles 3658664408 # number of cpu cycles simulated |
| 280system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 281system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 282system.cpu.committedInsts 60038305 # Number of instructions committed 283system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed 284system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses 285system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 286system.cpu.num_func_calls 1484182 # number of times a function call or return occured 287system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls 288system.cpu.num_int_insts 55913521 # number of integer instructions 289system.cpu.num_fp_insts 324460 # number of float instructions 290system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read 291system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written 292system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 293system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 294system.cpu.num_mem_refs 16115709 # number of memory refs 295system.cpu.num_load_insts 9747513 # Number of load instructions 296system.cpu.num_store_insts 6368196 # Number of store instructions | 133system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 134system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 135system.cpu.committedInsts 60038305 # Number of instructions committed 136system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed 137system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses 138system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 139system.cpu.num_func_calls 1484182 # number of times a function call or return occured 140system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls 141system.cpu.num_int_insts 55913521 # number of integer instructions 142system.cpu.num_fp_insts 324460 # number of float instructions 143system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read 144system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written 145system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 146system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written 147system.cpu.num_mem_refs 16115709 # number of memory refs 148system.cpu.num_load_insts 9747513 # Number of load instructions 149system.cpu.num_store_insts 6368196 # Number of store instructions |
| 297system.cpu.num_idle_cycles 3598609001.180807 # Number of idle cycles | 150system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles |
| 298system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles 299system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles 300system.cpu.idle_fraction 0.983585 # Percentage of idle cycles 301system.cpu.kern.inst.arm 0 # number of arm instructions executed 302system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 303system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed 304system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 305system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 306system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 307system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl 308system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl 309system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 310system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 311system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 312system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 313system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl | 151system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles 152system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles 153system.cpu.idle_fraction 0.983585 # Percentage of idle cycles 154system.cpu.kern.inst.arm 0 # number of arm instructions executed 155system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed 156system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed 157system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 158system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 159system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl 160system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl 161system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl 162system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 163system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 164system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 165system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 166system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl |
| 314system.cpu.kern.ipl_ticks::0 1811927418500 99.05% 99.05% # number of cycles we spent at this ipl | 167system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl |
| 315system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 316system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 317system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl | 168system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 169system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl 170system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl |
| 318system.cpu.kern.ipl_ticks::total 1829332061500 # number of cycles we spent at this ipl | 171system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl |
| 319system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 320system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 321system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 322system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl 323system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl 324system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 325system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 326system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed --- 49 unchanged lines hidden (view full) --- 376system.cpu.kern.mode_good::user 1738 377system.cpu.kern.mode_good::idle 171 378system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches 379system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 380system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 381system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches 382system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode 383system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode | 172system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 173system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 174system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl 175system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl 176system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl 177system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 178system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 179system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed --- 49 unchanged lines hidden (view full) --- 229system.cpu.kern.mode_good::user 1738 230system.cpu.kern.mode_good::idle 171 231system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches 232system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 233system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches 234system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches 235system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode 236system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode |
| 384system.cpu.kern.mode_ticks::idle 1801032784000 98.45% 100.00% # number of ticks spent at the given mode | 237system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode |
| 385system.cpu.kern.swap_context 4178 # number of times the context was actually changed 386system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 387system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 388system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 389system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 390system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 391system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 392system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 18 unchanged lines hidden (view full) --- 411system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 412system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 413system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 414system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 415system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 416system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 417system.iobus.throughput 1480181 # Throughput (bytes/s) 418system.iobus.data_through_bus 2707742 # Total data (bytes) | 238system.cpu.kern.swap_context 4178 # number of times the context was actually changed 239system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 240system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 241system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 242system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 243system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 244system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 245system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR --- 18 unchanged lines hidden (view full) --- 264system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 265system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 266system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 267system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 268system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 269system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 270system.iobus.throughput 1480181 # Throughput (bytes/s) 271system.iobus.data_through_bus 2707742 # Total data (bytes) |
| 419system.cpu.icache.tags.replacements 919609 # number of replacements 420system.cpu.icache.tags.tagsinuse 511.215244 # Cycle average of tags in use 421system.cpu.icache.tags.total_refs 59129907 # Total number of references to valid blocks. 422system.cpu.icache.tags.sampled_refs 920121 # Sample count of references to valid blocks. 423system.cpu.icache.tags.avg_refs 64.263186 # Average number of references to valid blocks. | 272system.cpu.icache.tags.replacements 919594 # number of replacements 273system.cpu.icache.tags.tagsinuse 511.215243 # Cycle average of tags in use 274system.cpu.icache.tags.total_refs 59129922 # Total number of references to valid blocks. 275system.cpu.icache.tags.sampled_refs 920106 # Sample count of references to valid blocks. 276system.cpu.icache.tags.avg_refs 64.264250 # Average number of references to valid blocks. |
| 424system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. | 277system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. |
| 425system.cpu.icache.tags.occ_blocks::cpu.inst 511.215244 # Average occupied blocks per requestor | 278system.cpu.icache.tags.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor |
| 426system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 427system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy | 279system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 280system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy |
| 428system.cpu.icache.ReadReq_hits::cpu.inst 59129907 # number of ReadReq hits 429system.cpu.icache.ReadReq_hits::total 59129907 # number of ReadReq hits 430system.cpu.icache.demand_hits::cpu.inst 59129907 # number of demand (read+write) hits 431system.cpu.icache.demand_hits::total 59129907 # number of demand (read+write) hits 432system.cpu.icache.overall_hits::cpu.inst 59129907 # number of overall hits 433system.cpu.icache.overall_hits::total 59129907 # number of overall hits 434system.cpu.icache.ReadReq_misses::cpu.inst 920236 # number of ReadReq misses 435system.cpu.icache.ReadReq_misses::total 920236 # number of ReadReq misses 436system.cpu.icache.demand_misses::cpu.inst 920236 # number of demand (read+write) misses 437system.cpu.icache.demand_misses::total 920236 # number of demand (read+write) misses 438system.cpu.icache.overall_misses::cpu.inst 920236 # number of overall misses 439system.cpu.icache.overall_misses::total 920236 # number of overall misses | 281system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits 282system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits 283system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits 284system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits 285system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits 286system.cpu.icache.overall_hits::total 59129922 # number of overall hits 287system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses 288system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses 289system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses 290system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses 291system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses 292system.cpu.icache.overall_misses::total 920221 # number of overall misses |
| 440system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) 441system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) 442system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses 443system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses 444system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses 445system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses 446system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 447system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses --- 6 unchanged lines hidden (view full) --- 454system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 455system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 456system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 457system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 458system.cpu.icache.fast_writes 0 # number of fast writes performed 459system.cpu.icache.cache_copies 0 # number of cache copies performed 460system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 461system.cpu.l2cache.tags.replacements 992301 # number of replacements | 293system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses) 294system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses) 295system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses 296system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses 297system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses 298system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses 299system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 300system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses --- 6 unchanged lines hidden (view full) --- 307system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 308system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 309system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 310system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 311system.cpu.icache.fast_writes 0 # number of fast writes performed 312system.cpu.icache.cache_copies 0 # number of cache copies performed 313system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 314system.cpu.l2cache.tags.replacements 992301 # number of replacements |
| 462system.cpu.l2cache.tags.tagsinuse 65424.374219 # Cycle average of tags in use 463system.cpu.l2cache.tags.total_refs 2433263 # Total number of references to valid blocks. | 315system.cpu.l2cache.tags.tagsinuse 65424.374305 # Cycle average of tags in use 316system.cpu.l2cache.tags.total_refs 2433239 # Total number of references to valid blocks. |
| 464system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks. | 317system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks. |
| 465system.cpu.l2cache.tags.avg_refs 2.301036 # Average number of references to valid blocks. | 318system.cpu.l2cache.tags.avg_refs 2.301014 # Average number of references to valid blocks. |
| 466system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. | 319system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. |
| 467system.cpu.l2cache.tags.occ_blocks::writebacks 56309.127841 # Average occupied blocks per requestor 468system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.327126 # Average occupied blocks per requestor 469system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.919252 # Average occupied blocks per requestor | 320system.cpu.l2cache.tags.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor 321system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor 322system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor |
| 470system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy 471system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy 472system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy 473system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy | 323system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy 324system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy 325system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy 326system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy |
| 474system.cpu.l2cache.ReadReq_hits::cpu.inst 906812 # number of ReadReq hits 475system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits 476system.cpu.l2cache.ReadReq_hits::total 1718044 # number of ReadReq hits 477system.cpu.l2cache.Writeback_hits::writebacks 833497 # number of Writeback hits 478system.cpu.l2cache.Writeback_hits::total 833497 # number of Writeback hits | 327system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits 328system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits 329system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits 330system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits 331system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits |
| 479system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 480system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 332system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 333system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 481system.cpu.l2cache.ReadExReq_hits::cpu.data 187230 # number of ReadExReq hits 482system.cpu.l2cache.ReadExReq_hits::total 187230 # number of ReadExReq hits 483system.cpu.l2cache.demand_hits::cpu.inst 906812 # number of demand (read+write) hits 484system.cpu.l2cache.demand_hits::cpu.data 998462 # number of demand (read+write) hits 485system.cpu.l2cache.demand_hits::total 1905274 # number of demand (read+write) hits 486system.cpu.l2cache.overall_hits::cpu.inst 906812 # number of overall hits 487system.cpu.l2cache.overall_hits::cpu.data 998462 # number of overall hits 488system.cpu.l2cache.overall_hits::total 1905274 # number of overall hits | 334system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits 335system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits 336system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits 337system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits 338system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits 339system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits 340system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits 341system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits |
| 489system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses 490system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses 491system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses 492system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 493system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses 494system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses 495system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses 496system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses 497system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses 498system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses 499system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses 500system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses 501system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses | 342system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses 343system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses 344system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses 345system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 346system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses 347system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses 348system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses 349system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses 350system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses 351system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses 352system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses 353system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses 354system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses |
| 502system.cpu.l2cache.ReadReq_accesses::cpu.inst 920218 # number of ReadReq accesses(hits+misses) 503system.cpu.l2cache.ReadReq_accesses::cpu.data 1738872 # number of ReadReq accesses(hits+misses) 504system.cpu.l2cache.ReadReq_accesses::total 2659090 # number of ReadReq accesses(hits+misses) 505system.cpu.l2cache.Writeback_accesses::writebacks 833497 # number of Writeback accesses(hits+misses) 506system.cpu.l2cache.Writeback_accesses::total 833497 # number of Writeback accesses(hits+misses) | 355system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) 356system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses) 357system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses) 358system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) 359system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) |
| 507system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 508system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) | 360system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 361system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) |
| 509system.cpu.l2cache.ReadExReq_accesses::cpu.data 304347 # number of ReadExReq accesses(hits+misses) 510system.cpu.l2cache.ReadExReq_accesses::total 304347 # number of ReadExReq accesses(hits+misses) 511system.cpu.l2cache.demand_accesses::cpu.inst 920218 # number of demand (read+write) accesses 512system.cpu.l2cache.demand_accesses::cpu.data 2043219 # number of demand (read+write) accesses 513system.cpu.l2cache.demand_accesses::total 2963437 # number of demand (read+write) accesses 514system.cpu.l2cache.overall_accesses::cpu.inst 920218 # number of overall (read+write) accesses 515system.cpu.l2cache.overall_accesses::cpu.data 2043219 # number of overall (read+write) accesses 516system.cpu.l2cache.overall_accesses::total 2963437 # number of overall (read+write) accesses 517system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses 518system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses 519system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses | 362system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) 363system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) 364system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses 365system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses 366system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses 367system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses 368system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses 369system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses 370system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses 371system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses 372system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses |
| 520system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 521system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses | 373system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 374system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses |
| 522system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384814 # miss rate for ReadExReq accesses 523system.cpu.l2cache.ReadExReq_miss_rate::total 0.384814 # miss rate for ReadExReq accesses 524system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses 525system.cpu.l2cache.demand_miss_rate::cpu.data 0.511329 # miss rate for demand accesses 526system.cpu.l2cache.demand_miss_rate::total 0.357073 # miss rate for demand accesses 527system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses 528system.cpu.l2cache.overall_miss_rate::cpu.data 0.511329 # miss rate for overall accesses 529system.cpu.l2cache.overall_miss_rate::total 0.357073 # miss rate for overall accesses | 375system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses 376system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses 377system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses 378system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses 379system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses 380system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses 381system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses 382system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses |
| 530system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 531system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 532system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 533system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 534system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 535system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 536system.cpu.l2cache.fast_writes 0 # number of fast writes performed 537system.cpu.l2cache.cache_copies 0 # number of cache copies performed 538system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks 539system.cpu.l2cache.writebacks::total 74291 # number of writebacks 540system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 383system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 384system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 385system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 386system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 387system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 388system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 389system.cpu.l2cache.fast_writes 0 # number of fast writes performed 390system.cpu.l2cache.cache_copies 0 # number of cache copies performed 391system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks 392system.cpu.l2cache.writebacks::total 74291 # number of writebacks 393system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 541system.cpu.dcache.tags.replacements 2042706 # number of replacements | 394system.cpu.dcache.tags.replacements 2042702 # number of replacements |
| 542system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use | 395system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use |
| 543system.cpu.dcache.tags.total_refs 14038427 # Total number of references to valid blocks. 544system.cpu.dcache.tags.sampled_refs 2043218 # Sample count of references to valid blocks. 545system.cpu.dcache.tags.avg_refs 6.870744 # Average number of references to valid blocks. | 396system.cpu.dcache.tags.total_refs 14038431 # Total number of references to valid blocks. 397system.cpu.dcache.tags.sampled_refs 2043214 # Sample count of references to valid blocks. 398system.cpu.dcache.tags.avg_refs 6.870759 # Average number of references to valid blocks. |
| 546system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 547system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 548system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 549system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy | 399system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 400system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 401system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 402system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy |
| 550system.cpu.dcache.ReadReq_hits::cpu.data 7807777 # number of ReadReq hits 551system.cpu.dcache.ReadReq_hits::total 7807777 # number of ReadReq hits 552system.cpu.dcache.WriteReq_hits::cpu.data 5848211 # number of WriteReq hits 553system.cpu.dcache.WriteReq_hits::total 5848211 # number of WriteReq hits | 403system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits 404system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits 405system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits 406system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits |
| 554system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits 555system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 556system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 557system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits | 407system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits 408system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 409system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 410system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits |
| 558system.cpu.dcache.demand_hits::cpu.data 13655988 # number of demand (read+write) hits 559system.cpu.dcache.demand_hits::total 13655988 # number of demand (read+write) hits 560system.cpu.dcache.overall_hits::cpu.data 13655988 # number of overall hits 561system.cpu.dcache.overall_hits::total 13655988 # number of overall hits 562system.cpu.dcache.ReadReq_misses::cpu.data 1721710 # number of ReadReq misses 563system.cpu.dcache.ReadReq_misses::total 1721710 # number of ReadReq misses 564system.cpu.dcache.WriteReq_misses::cpu.data 304363 # number of WriteReq misses 565system.cpu.dcache.WriteReq_misses::total 304363 # number of WriteReq misses | 411system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits 412system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits 413system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits 414system.cpu.dcache.overall_hits::total 13655992 # number of overall hits 415system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses 416system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses 417system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses 418system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses |
| 566system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 567system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses | 419system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 420system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses |
| 568system.cpu.dcache.demand_misses::cpu.data 2026073 # number of demand (read+write) misses 569system.cpu.dcache.demand_misses::total 2026073 # number of demand (read+write) misses 570system.cpu.dcache.overall_misses::cpu.data 2026073 # number of overall misses 571system.cpu.dcache.overall_misses::total 2026073 # number of overall misses | 421system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses 422system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses 423system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses 424system.cpu.dcache.overall_misses::total 2026069 # number of overall misses |
| 572system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) 573system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) 574system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) 575system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) 576system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 577system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 578system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 579system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) --- 14 unchanged lines hidden (view full) --- 594system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 595system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 596system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 597system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 598system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 599system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 600system.cpu.dcache.fast_writes 0 # number of fast writes performed 601system.cpu.dcache.cache_copies 0 # number of cache copies performed | 425system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses) 426system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses) 427system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses) 428system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses) 429system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 430system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 431system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 432system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) --- 14 unchanged lines hidden (view full) --- 447system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 448system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 449system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 450system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 451system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 452system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 453system.cpu.dcache.fast_writes 0 # number of fast writes performed 454system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 602system.cpu.dcache.writebacks::writebacks 833497 # number of writebacks 603system.cpu.dcache.writebacks::total 833497 # number of writebacks | 455system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks 456system.cpu.dcache.writebacks::total 833491 # number of writebacks |
| 604system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 605system.cpu.toL2Bus.throughput 132868790 # Throughput (bytes/s) 606system.cpu.toL2Bus.data_through_bus 243051054 # Total data (bytes) | 458system.cpu.toL2Bus.throughput 132867917 # Throughput (bytes/s) 459system.cpu.toL2Bus.data_through_bus 243049454 # Total data (bytes) |
| 607system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes) 608 609---------- End Simulation Statistics ---------- | 460system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes) 461 462---------- End Simulation Statistics ---------- |