| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829332 # Number of seconds simulated 4sim_ticks 1829332258000 # Number of ticks simulated 5final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829332 # Number of seconds simulated 4sim_ticks 1829332258000 # Number of ticks simulated 5final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 4111639 # Simulator instruction rate (inst/s) 8host_op_rate 4111633 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 125278906724 # Simulator tick rate (ticks/s) 10host_mem_usage 291412 # Number of bytes of host memory used 11host_seconds 14.60 # Real time elapsed on the host | 7host_inst_rate 1921293 # Simulator instruction rate (inst/s) 8host_op_rate 1921291 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 58540553267 # Simulator tick rate (ticks/s) 10host_mem_usage 295828 # Number of bytes of host memory used 11host_seconds 31.25 # Real time elapsed on the host |
| 12sim_insts 60038305 # Number of instructions simulated 13sim_ops 60038305 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 71650816 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10156864 # Number of bytes written to this memory 17system.physmem.num_reads 1119544 # Number of read requests responded to by this memory 18system.physmem.num_writes 158701 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 64 unchanged lines hidden (view full) --- 84system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses 85system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses 86system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses 87system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses 88system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 89system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 90system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 91system.l2c.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 60038305 # Number of instructions simulated 13sim_ops 60038305 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 71650816 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 10156864 # Number of bytes written to this memory 17system.physmem.num_reads 1119544 # Number of read requests responded to by this memory 18system.physmem.num_writes 158701 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 64 unchanged lines hidden (view full) --- 84system.l2c.demand_miss_rate::cpu.inst 0.016231 # miss rate for demand accesses 85system.l2c.demand_miss_rate::cpu.data 0.520567 # miss rate for demand accesses 86system.l2c.overall_miss_rate::cpu.inst 0.016231 # miss rate for overall accesses 87system.l2c.overall_miss_rate::cpu.data 0.520567 # miss rate for overall accesses 88system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 89system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked 90system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked 91system.l2c.blocked::no_targets 0 # number of cycles access was blocked |
| 92system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 93system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 92system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 93system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 94system.l2c.fast_writes 0 # number of fast writes performed 95system.l2c.cache_copies 0 # number of cache copies performed 96system.l2c.writebacks::writebacks 117189 # number of writebacks 97system.l2c.writebacks::total 117189 # number of writebacks 98system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 99system.iocache.replacements 41686 # number of replacements 100system.iocache.tagsinuse 1.225570 # Cycle average of tags in use 101system.iocache.total_refs 0 # Total number of references to valid blocks. --- 22 unchanged lines hidden (view full) --- 124system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 125system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 126system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 127system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 128system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 129system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 131system.iocache.blocked::no_targets 0 # number of cycles access was blocked | 94system.l2c.fast_writes 0 # number of fast writes performed 95system.l2c.cache_copies 0 # number of cache copies performed 96system.l2c.writebacks::writebacks 117189 # number of writebacks 97system.l2c.writebacks::total 117189 # number of writebacks 98system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate 99system.iocache.replacements 41686 # number of replacements 100system.iocache.tagsinuse 1.225570 # Cycle average of tags in use 101system.iocache.total_refs 0 # Total number of references to valid blocks. --- 22 unchanged lines hidden (view full) --- 124system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 125system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses 126system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 127system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 128system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 129system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 130system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 131system.iocache.blocked::no_targets 0 # number of cycles access was blocked |
| 132system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 133system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 132system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 133system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 134system.iocache.fast_writes 0 # number of fast writes performed 135system.iocache.cache_copies 0 # number of cache copies performed 136system.iocache.writebacks::writebacks 41512 # number of writebacks 137system.iocache.writebacks::total 41512 # number of writebacks 138system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 139system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 140system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 141system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 144 unchanged lines hidden (view full) --- 286system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode 287system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode 288system.cpu.kern.swap_context 4178 # number of times the context was actually changed 289system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 290system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 291system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 292system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 293system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU | 134system.iocache.fast_writes 0 # number of fast writes performed 135system.iocache.cache_copies 0 # number of cache copies performed 136system.iocache.writebacks::writebacks 41512 # number of writebacks 137system.iocache.writebacks::total 41512 # number of writebacks 138system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 139system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 140system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 141system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). --- 144 unchanged lines hidden (view full) --- 286system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode 287system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode 288system.cpu.kern.swap_context 4178 # number of times the context was actually changed 289system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 290system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 291system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 292system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 293system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU |
| 294system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post | 294system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post |
| 295system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 296system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU | 295system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 296system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU |
| 297system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post | 297system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post |
| 298system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 299system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU | 298system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 299system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU |
| 300system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post | 300system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post |
| 301system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 302system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU | 301system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 302system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU |
| 303system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post | 303system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post |
| 304system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 305system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU | 304system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 305system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU |
| 306system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post | 306system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post |
| 307system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 308system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU | 307system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 308system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU |
| 309system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post | 309system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post |
| 310system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 311system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU | 310system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 311system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU |
| 312system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post | 312system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post |
| 313system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 314system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU | 313system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 314system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU |
| 315system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post | 315system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post |
| 316system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR | 316system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR |
| 317system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post | 317system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post |
| 318system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 319system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 320system.cpu.icache.replacements 919594 # number of replacements 321system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use 322system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. 323system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. 324system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. 325system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. --- 20 unchanged lines hidden (view full) --- 346system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses 347system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 348system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 349system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 350system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 351system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 352system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 353system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 318system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 319system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 320system.cpu.icache.replacements 919594 # number of replacements 321system.cpu.icache.tagsinuse 511.215243 # Cycle average of tags in use 322system.cpu.icache.total_refs 59129922 # Total number of references to valid blocks. 323system.cpu.icache.sampled_refs 920106 # Sample count of references to valid blocks. 324system.cpu.icache.avg_refs 64.264250 # Average number of references to valid blocks. 325system.cpu.icache.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. --- 20 unchanged lines hidden (view full) --- 346system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses 347system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 348system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 349system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 350system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 351system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 352system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 353system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 354system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 355system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 354system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 355system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 356system.cpu.icache.fast_writes 0 # number of fast writes performed 357system.cpu.icache.cache_copies 0 # number of cache copies performed 358system.cpu.icache.writebacks::writebacks 108 # number of writebacks 359system.cpu.icache.writebacks::total 108 # number of writebacks 360system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 361system.cpu.dcache.replacements 2042700 # number of replacements 362system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use 363system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. --- 41 unchanged lines hidden (view full) --- 405system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses 406system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses 407system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses 408system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses 409system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 356system.cpu.icache.fast_writes 0 # number of fast writes performed 357system.cpu.icache.cache_copies 0 # number of cache copies performed 358system.cpu.icache.writebacks::writebacks 108 # number of writebacks 359system.cpu.icache.writebacks::total 108 # number of writebacks 360system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 361system.cpu.dcache.replacements 2042700 # number of replacements 362system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use 363system.cpu.dcache.total_refs 14038433 # Total number of references to valid blocks. --- 41 unchanged lines hidden (view full) --- 405system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses 406system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses 407system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses 408system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses 409system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 410system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 411system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 412system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 413system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 414system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 413system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 414system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 415system.cpu.dcache.fast_writes 0 # number of fast writes performed 416system.cpu.dcache.cache_copies 0 # number of cache copies performed 417system.cpu.dcache.writebacks::writebacks 825183 # number of writebacks 418system.cpu.dcache.writebacks::total 825183 # number of writebacks 419system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 420 421---------- End Simulation Statistics ---------- | 415system.cpu.dcache.fast_writes 0 # number of fast writes performed 416system.cpu.dcache.cache_copies 0 # number of cache copies performed 417system.cpu.dcache.writebacks::writebacks 825183 # number of writebacks 418system.cpu.dcache.writebacks::total 825183 # number of writebacks 419system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 420 421---------- End Simulation Statistics ---------- |