| stats.txt (10409:8c80b91944c5) | stats.txt (10585:1c9d5d9417b3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829332 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829332 # Number of seconds simulated |
| 4sim_ticks 1829331993500 # Number of ticks simulated 5final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 1829332273500 # Number of ticks simulated 5final_tick 1829332273500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 2920462 # Simulator instruction rate (inst/s) 8host_op_rate 2920460 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 88984410684 # Simulator tick rate (ticks/s) 10host_mem_usage 366200 # Number of bytes of host memory used 11host_seconds 20.56 # Real time elapsed on the host 12sim_insts 60038469 # Number of instructions simulated 13sim_ops 60038469 # Number of ops (including micro ops) simulated | 7host_inst_rate 1690642 # Simulator instruction rate (inst/s) 8host_op_rate 1690641 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 51512796649 # Simulator tick rate (ticks/s) 10host_mem_usage 313048 # Number of bytes of host memory used 11host_seconds 35.51 # Real time elapsed on the host 12sim_insts 60038341 # Number of instructions simulated 13sim_ops 60038341 # Number of ops (including micro ops) simulated |
| 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory | 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 66856000 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 66839040 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory | 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 67714944 # Number of bytes read from this memory | 19system.physmem.bytes_read::total 67697984 # Number of bytes read from this memory |
| 20system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory | 20system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory |
| 22system.physmem.bytes_written::writebacks 4753856 # Number of bytes written to this memory 23system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory 24system.physmem.bytes_written::total 7413184 # Number of bytes written to this memory | 22system.physmem.bytes_written::writebacks 7411008 # Number of bytes written to this memory 23system.physmem.bytes_written::total 7411008 # Number of bytes written to this memory |
| 25system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory | 24system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::cpu.data 1044625 # Number of read requests responded to by this memory | 25system.physmem.num_reads::cpu.data 1044360 # Number of read requests responded to by this memory |
| 27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory | 26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory |
| 28system.physmem.num_reads::total 1058046 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 74279 # Number of write requests responded to by this memory 30system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory 31system.physmem.num_writes::total 115831 # Number of write requests responded to by this memory | 27system.physmem.num_reads::total 1057781 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 115797 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 115797 # Number of write requests responded to by this memory |
| 32system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) | 30system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s) |
| 33system.physmem.bw_read::cpu.data 36546674 # Total read bandwidth from this memory (bytes/s) | 31system.physmem.bw_read::cpu.data 36537397 # Total read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) | 32system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s) |
| 35system.physmem.bw_read::total 37016214 # Total read bandwidth from this memory (bytes/s) | 33system.physmem.bw_read::total 37006937 # Total read bandwidth from this memory (bytes/s) |
| 36system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) | 34system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s) |
| 38system.physmem.bw_write::writebacks 2598684 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s) 40system.physmem.bw_write::total 4052399 # Write bandwidth from this memory (bytes/s) 41system.physmem.bw_total::writebacks 2598684 # Total bandwidth to/from this memory (bytes/s) | 36system.physmem.bw_write::writebacks 4051209 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 4051209 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 4051209 # Total bandwidth to/from this memory (bytes/s) |
| 42system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) | 39system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s) |
| 43system.physmem.bw_total::cpu.data 36546674 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s) 45system.physmem.bw_total::total 41068613 # Total bandwidth to/from this memory (bytes/s) 46system.membus.trans_dist::ReadReq 948404 # Transaction distribution 47system.membus.trans_dist::ReadResp 948404 # Transaction distribution 48system.membus.trans_dist::WriteReq 9838 # Transaction distribution 49system.membus.trans_dist::WriteResp 9838 # Transaction distribution 50system.membus.trans_dist::Writeback 74279 # Transaction distribution 51system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 52system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 53system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 54system.membus.trans_dist::UpgradeResp 132 # Transaction distribution 55system.membus.trans_dist::ReadExReq 116985 # Transaction distribution 56system.membus.trans_dist::ReadExResp 116985 # Transaction distribution 57system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) 58system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190605 # Packet count per connected master and slave (bytes) 59system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224649 # Packet count per connected master and slave (bytes) 60system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 83452 # Packet count per connected master and slave (bytes) 61system.membus.pkt_count_system.iocache.mem_side::total 83452 # Packet count per connected master and slave (bytes) 62system.membus.pkt_count::total 2308101 # Packet count per connected master and slave (bytes) 63system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) 64system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72467840 # Cumulative packet size per connected master and slave (bytes) 65system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72513966 # Cumulative packet size per connected master and slave (bytes) 66system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2670464 # Cumulative packet size per connected master and slave (bytes) 67system.membus.pkt_size_system.iocache.mem_side::total 2670464 # Cumulative packet size per connected master and slave (bytes) 68system.membus.pkt_size::total 75184430 # Cumulative packet size per connected master and slave (bytes) 69system.membus.snoops 0 # Total snoops (count) 70system.membus.snoop_fanout::samples 1174168 # Request fanout histogram 71system.membus.snoop_fanout::mean 1 # Request fanout histogram 72system.membus.snoop_fanout::stdev 0 # Request fanout histogram 73system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 74system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 75system.membus.snoop_fanout::1 1174168 100.00% 100.00% # Request fanout histogram 76system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 77system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 78system.membus.snoop_fanout::min_value 1 # Request fanout histogram 79system.membus.snoop_fanout::max_value 1 # Request fanout histogram 80system.membus.snoop_fanout::total 1174168 # Request fanout histogram 81system.iocache.tags.replacements 41686 # number of replacements 82system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use 83system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 84system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 85system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 86system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. 87system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor 88system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy 89system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy 90system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 91system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 92system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 93system.iocache.tags.tag_accesses 375534 # Number of tag accesses 94system.iocache.tags.data_accesses 375534 # Number of data accesses 95system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits 96system.iocache.WriteInvalidateReq_hits::total 41552 # number of WriteInvalidateReq hits 97system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 98system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 99system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses 100system.iocache.demand_misses::total 174 # number of demand (read+write) misses 101system.iocache.overall_misses::tsunami.ide 174 # number of overall misses 102system.iocache.overall_misses::total 174 # number of overall misses 103system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 104system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 105system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 106system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 107system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses 108system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses 109system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses 110system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses 111system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 112system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 113system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 114system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 115system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 116system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 117system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 118system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 119system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 120system.iocache.blocked::no_targets 0 # number of cycles access was blocked 121system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 122system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 123system.iocache.fast_writes 41552 # number of fast writes performed 124system.iocache.cache_copies 0 # number of cache copies performed 125system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 126system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 127system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 128system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 129system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 130system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 131system.disk0.dma_write_txs 395 # Number of DMA write transactions. 132system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 133system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 134system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 135system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 136system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 137system.disk2.dma_write_txs 1 # Number of DMA write transactions. | 40system.physmem.bw_total::cpu.data 36537397 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 41058146 # Total bandwidth to/from this memory (bytes/s) |
| 138system.cpu_clk_domain.clock 500 # Clock period in ticks 139system.cpu.dtb.fetch_hits 0 # ITB hits 140system.cpu.dtb.fetch_misses 0 # ITB misses 141system.cpu.dtb.fetch_acv 0 # ITB acv 142system.cpu.dtb.fetch_accesses 0 # ITB accesses | 43system.cpu_clk_domain.clock 500 # Clock period in ticks 44system.cpu.dtb.fetch_hits 0 # ITB hits 45system.cpu.dtb.fetch_misses 0 # ITB misses 46system.cpu.dtb.fetch_acv 0 # ITB acv 47system.cpu.dtb.fetch_accesses 0 # ITB accesses |
| 143system.cpu.dtb.read_hits 9710423 # DTB read hits | 48system.cpu.dtb.read_hits 9710422 # DTB read hits |
| 144system.cpu.dtb.read_misses 10329 # DTB read misses 145system.cpu.dtb.read_acv 210 # DTB read access violations 146system.cpu.dtb.read_accesses 728856 # DTB read accesses 147system.cpu.dtb.write_hits 6352496 # DTB write hits 148system.cpu.dtb.write_misses 1142 # DTB write misses 149system.cpu.dtb.write_acv 157 # DTB write access violations 150system.cpu.dtb.write_accesses 291931 # DTB write accesses | 49system.cpu.dtb.read_misses 10329 # DTB read misses 50system.cpu.dtb.read_acv 210 # DTB read access violations 51system.cpu.dtb.read_accesses 728856 # DTB read accesses 52system.cpu.dtb.write_hits 6352496 # DTB write hits 53system.cpu.dtb.write_misses 1142 # DTB write misses 54system.cpu.dtb.write_acv 157 # DTB write access violations 55system.cpu.dtb.write_accesses 291931 # DTB write accesses |
| 151system.cpu.dtb.data_hits 16062919 # DTB hits | 56system.cpu.dtb.data_hits 16062918 # DTB hits |
| 152system.cpu.dtb.data_misses 11471 # DTB misses 153system.cpu.dtb.data_acv 367 # DTB access violations 154system.cpu.dtb.data_accesses 1020787 # DTB accesses | 57system.cpu.dtb.data_misses 11471 # DTB misses 58system.cpu.dtb.data_acv 367 # DTB access violations 59system.cpu.dtb.data_accesses 1020787 # DTB accesses |
| 155system.cpu.itb.fetch_hits 4974637 # ITB hits | 60system.cpu.itb.fetch_hits 4974648 # ITB hits |
| 156system.cpu.itb.fetch_misses 5006 # ITB misses 157system.cpu.itb.fetch_acv 184 # ITB acv | 61system.cpu.itb.fetch_misses 5006 # ITB misses 62system.cpu.itb.fetch_acv 184 # ITB acv |
| 158system.cpu.itb.fetch_accesses 4979643 # ITB accesses | 63system.cpu.itb.fetch_accesses 4979654 # ITB accesses |
| 159system.cpu.itb.read_hits 0 # DTB read hits 160system.cpu.itb.read_misses 0 # DTB read misses 161system.cpu.itb.read_acv 0 # DTB read access violations 162system.cpu.itb.read_accesses 0 # DTB read accesses 163system.cpu.itb.write_hits 0 # DTB write hits 164system.cpu.itb.write_misses 0 # DTB write misses 165system.cpu.itb.write_acv 0 # DTB write access violations 166system.cpu.itb.write_accesses 0 # DTB write accesses 167system.cpu.itb.data_hits 0 # DTB hits 168system.cpu.itb.data_misses 0 # DTB misses 169system.cpu.itb.data_acv 0 # DTB access violations 170system.cpu.itb.data_accesses 0 # DTB accesses | 64system.cpu.itb.read_hits 0 # DTB read hits 65system.cpu.itb.read_misses 0 # DTB read misses 66system.cpu.itb.read_acv 0 # DTB read access violations 67system.cpu.itb.read_accesses 0 # DTB read accesses 68system.cpu.itb.write_hits 0 # DTB write hits 69system.cpu.itb.write_misses 0 # DTB write misses 70system.cpu.itb.write_acv 0 # DTB write access violations 71system.cpu.itb.write_accesses 0 # DTB write accesses 72system.cpu.itb.data_hits 0 # DTB hits 73system.cpu.itb.data_misses 0 # DTB misses 74system.cpu.itb.data_acv 0 # DTB access violations 75system.cpu.itb.data_accesses 0 # DTB accesses |
| 171system.cpu.numCycles 3658670345 # number of cpu cycles simulated | 76system.cpu.numCycles 3658670905 # number of cpu cycles simulated |
| 172system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 173system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 77system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 78system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 174system.cpu.committedInsts 60038469 # Number of instructions committed 175system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed 176system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses | 79system.cpu.committedInsts 60038341 # Number of instructions committed 80system.cpu.committedOps 60038341 # Number of ops (including micro ops) committed 81system.cpu.num_int_alu_accesses 55913563 # Number of integer alu accesses |
| 177system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 178system.cpu.num_func_calls 1484182 # number of times a function call or return occured | 82system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses 83system.cpu.num_func_calls 1484182 # number of times a function call or return occured |
| 179system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls 180system.cpu.num_int_insts 55913692 # number of integer instructions | 84system.cpu.num_conditional_control_insts 7110761 # number of instructions that are conditional controls 85system.cpu.num_int_insts 55913563 # number of integer instructions |
| 181system.cpu.num_fp_insts 324460 # number of float instructions | 86system.cpu.num_fp_insts 324460 # number of float instructions |
| 182system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read 183system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written | 87system.cpu.num_int_register_reads 76954014 # number of times the integer registers were read 88system.cpu.num_int_register_writes 41740254 # number of times the integer registers were written |
| 184system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 185system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written | 89system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read 90system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written |
| 186system.cpu.num_mem_refs 16115703 # number of memory refs 187system.cpu.num_load_insts 9747509 # Number of load instructions | 91system.cpu.num_mem_refs 16115702 # number of memory refs 92system.cpu.num_load_insts 9747508 # Number of load instructions |
| 188system.cpu.num_store_insts 6368194 # Number of store instructions | 93system.cpu.num_store_insts 6368194 # Number of store instructions |
| 189system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles 190system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles | 94system.cpu.num_idle_cycles 3598621691.055137 # Number of idle cycles 95system.cpu.num_busy_cycles 60049213.944863 # Number of busy cycles |
| 191system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles 192system.cpu.idle_fraction 0.983587 # Percentage of idle cycles | 96system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles 97system.cpu.idle_fraction 0.983587 # Percentage of idle cycles |
| 193system.cpu.Branches 9064428 # Number of branches fetched 194system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction 195system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction | 98system.cpu.Branches 9064400 # Number of branches fetched 99system.cpu.op_class::No_OpClass 3199098 5.33% 5.33% # Class of executed instruction 100system.cpu.op_class::IntAlu 39448273 65.69% 71.02% # Class of executed instruction |
| 196system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction 197system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction 198system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction 199system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction 200system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction 201system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction 202system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction 203system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction --- 12 unchanged lines hidden (view full) --- 216system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction 217system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction 218system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction 219system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction 220system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction 221system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction 222system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction 223system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction | 101system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction 102system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction 103system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction 104system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction 105system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction 106system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction 107system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction 108system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction --- 12 unchanged lines hidden (view full) --- 121system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction 122system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction 123system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction 124system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction 125system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction 126system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction 127system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction 128system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction |
| 224system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction | 129system.cpu.op_class::MemRead 9975076 16.61% 87.80% # Class of executed instruction |
| 225system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction | 130system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction |
| 226system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction | 131system.cpu.op_class::IprAccess 951217 1.58% 100.00% # Class of executed instruction |
| 227system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction | 132system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| 228system.cpu.op_class::total 60050307 # Class of executed instruction | 133system.cpu.op_class::total 60050179 # Class of executed instruction |
| 229system.cpu.kern.inst.arm 0 # number of arm instructions executed 230system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed | 134system.cpu.kern.inst.arm 0 # number of arm instructions executed 135system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed |
| 231system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed | 136system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed |
| 232system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 233system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 234system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl | 137system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl 138system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl 139system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl |
| 235system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl 236system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl | 140system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl 141system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl |
| 237system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 238system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 239system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 240system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 241system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl | 142system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl 143system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl 144system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl 145system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl 146system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl |
| 242system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl | 147system.cpu.kern.ipl_ticks::0 1811929473000 99.05% 99.05% # number of cycles we spent at this ipl |
| 243system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 244system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl | 148system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl 149system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl |
| 245system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl 246system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl | 150system.cpu.kern.ipl_ticks::31 17302245000 0.95% 100.00% # number of cycles we spent at this ipl 151system.cpu.kern.ipl_ticks::total 1829332066000 # number of cycles we spent at this ipl |
| 247system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 248system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 249system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl | 152system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl 153system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl 154system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl |
| 250system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl 251system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl | 155system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl 156system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl |
| 252system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 253system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 254system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 255system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 256system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 257system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 258system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 259system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 282system.cpu.kern.syscall::total 326 # number of syscalls executed 283system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 284system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 285system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 286system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 287system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 288system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 289system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed | 157system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed 158system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed 159system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed 160system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed 161system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed 162system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed 163system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed 164system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed --- 22 unchanged lines hidden (view full) --- 187system.cpu.kern.syscall::total 326 # number of syscalls executed 188system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed 189system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed 190system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed 191system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed 192system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed 193system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed 194system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed |
| 290system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed | 195system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed |
| 291system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 292system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 293system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 294system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 295system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 296system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 297system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 298system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed | 196system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed 197system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed 198system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed 199system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed 200system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed 201system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed 202system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed 203system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed |
| 299system.cpu.kern.callpal::total 192179 # number of callpals executed | 204system.cpu.kern.callpal::total 192180 # number of callpals executed |
| 300system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches | 205system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches |
| 301system.cpu.kern.mode_switch::user 1737 # number of protection mode switches | 206system.cpu.kern.mode_switch::user 1738 # number of protection mode switches |
| 302system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches | 207system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches |
| 303system.cpu.kern.mode_good::kernel 1908 304system.cpu.kern.mode_good::user 1737 | 208system.cpu.kern.mode_good::kernel 1909 209system.cpu.kern.mode_good::user 1738 |
| 305system.cpu.kern.mode_good::idle 171 | 210system.cpu.kern.mode_good::idle 171 |
| 306system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches | 211system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches |
| 307system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 308system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches | 212system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches 213system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches |
| 309system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches 310system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode 311system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode 312system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode | 214system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches 215system.cpu.kern.mode_ticks::kernel 26833319500 1.47% 1.47% # number of ticks spent at the given mode 216system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode 217system.cpu.kern.mode_ticks::idle 1801033671500 98.45% 100.00% # number of ticks spent at the given mode |
| 313system.cpu.kern.swap_context 4178 # number of times the context was actually changed | 218system.cpu.kern.swap_context 4178 # number of times the context was actually changed |
| 314system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 315system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 316system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 317system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 318system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 319system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 320system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 321system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 322system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 323system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 324system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 325system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 326system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 327system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 328system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 329system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 330system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 331system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 332system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 333system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 334system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 335system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 336system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 337system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 338system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 339system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 340system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 341system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 342system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 343system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 344system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 345system.iobus.trans_dist::ReadReq 7358 # Transaction distribution 346system.iobus.trans_dist::ReadResp 7358 # Transaction distribution 347system.iobus.trans_dist::WriteReq 51390 # Transaction distribution 348system.iobus.trans_dist::WriteResp 9838 # Transaction distribution 349system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 350system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) 351system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) 352system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 353system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 354system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) 355system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) 356system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 357system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 358system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 359system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 360system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 361system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 362system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) 363system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 364system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 365system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) 366system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) 367system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) 368system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 369system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 370system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) 371system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) 372system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 373system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 374system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 375system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 376system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 377system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 378system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) 379system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 380system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 381system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) 382system.cpu.icache.tags.replacements 919603 # number of replacements 383system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use 384system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. 385system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks. 386system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks. | 219system.cpu.dcache.tags.replacements 2042728 # number of replacements 220system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use 221system.cpu.dcache.tags.total_refs 14038398 # Total number of references to valid blocks. 222system.cpu.dcache.tags.sampled_refs 2043240 # Sample count of references to valid blocks. 223system.cpu.dcache.tags.avg_refs 6.870655 # Average number of references to valid blocks. 224system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 225system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 226system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 227system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy 228system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id 230system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 231system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 233system.cpu.dcache.tags.tag_accesses 66369797 # Number of tag accesses 234system.cpu.dcache.tags.data_accesses 66369797 # Number of data accesses 235system.cpu.dcache.ReadReq_hits::cpu.data 7807758 # number of ReadReq hits 236system.cpu.dcache.ReadReq_hits::total 7807758 # number of ReadReq hits 237system.cpu.dcache.WriteReq_hits::cpu.data 5848202 # number of WriteReq hits 238system.cpu.dcache.WriteReq_hits::total 5848202 # number of WriteReq hits 239system.cpu.dcache.LoadLockedReq_hits::cpu.data 183140 # number of LoadLockedReq hits 240system.cpu.dcache.LoadLockedReq_hits::total 183140 # number of LoadLockedReq hits 241system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 242system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 243system.cpu.dcache.demand_hits::cpu.data 13655960 # number of demand (read+write) hits 244system.cpu.dcache.demand_hits::total 13655960 # number of demand (read+write) hits 245system.cpu.dcache.overall_hits::cpu.data 13655960 # number of overall hits 246system.cpu.dcache.overall_hits::total 13655960 # number of overall hits 247system.cpu.dcache.ReadReq_misses::cpu.data 1721724 # number of ReadReq misses 248system.cpu.dcache.ReadReq_misses::total 1721724 # number of ReadReq misses 249system.cpu.dcache.WriteReq_misses::cpu.data 304370 # number of WriteReq misses 250system.cpu.dcache.WriteReq_misses::total 304370 # number of WriteReq misses 251system.cpu.dcache.LoadLockedReq_misses::cpu.data 17163 # number of LoadLockedReq misses 252system.cpu.dcache.LoadLockedReq_misses::total 17163 # number of LoadLockedReq misses 253system.cpu.dcache.demand_misses::cpu.data 2026094 # number of demand (read+write) misses 254system.cpu.dcache.demand_misses::total 2026094 # number of demand (read+write) misses 255system.cpu.dcache.overall_misses::cpu.data 2026094 # number of overall misses 256system.cpu.dcache.overall_misses::total 2026094 # number of overall misses 257system.cpu.dcache.ReadReq_accesses::cpu.data 9529482 # number of ReadReq accesses(hits+misses) 258system.cpu.dcache.ReadReq_accesses::total 9529482 # number of ReadReq accesses(hits+misses) 259system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) 260system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) 261system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 262system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 263system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 264system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 265system.cpu.dcache.demand_accesses::cpu.data 15682054 # number of demand (read+write) accesses 266system.cpu.dcache.demand_accesses::total 15682054 # number of demand (read+write) accesses 267system.cpu.dcache.overall_accesses::cpu.data 15682054 # number of overall (read+write) accesses 268system.cpu.dcache.overall_accesses::total 15682054 # number of overall (read+write) accesses 269system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180673 # miss rate for ReadReq accesses 270system.cpu.dcache.ReadReq_miss_rate::total 0.180673 # miss rate for ReadReq accesses 271system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049470 # miss rate for WriteReq accesses 272system.cpu.dcache.WriteReq_miss_rate::total 0.049470 # miss rate for WriteReq accesses 273system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085685 # miss rate for LoadLockedReq accesses 274system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085685 # miss rate for LoadLockedReq accesses 275system.cpu.dcache.demand_miss_rate::cpu.data 0.129198 # miss rate for demand accesses 276system.cpu.dcache.demand_miss_rate::total 0.129198 # miss rate for demand accesses 277system.cpu.dcache.overall_miss_rate::cpu.data 0.129198 # miss rate for overall accesses 278system.cpu.dcache.overall_miss_rate::total 0.129198 # miss rate for overall accesses 279system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 280system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 281system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 282system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 283system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 284system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 285system.cpu.dcache.fast_writes 0 # number of fast writes performed 286system.cpu.dcache.cache_copies 0 # number of cache copies performed 287system.cpu.dcache.writebacks::writebacks 833501 # number of writebacks 288system.cpu.dcache.writebacks::total 833501 # number of writebacks 289system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 290system.cpu.icache.tags.replacements 919605 # number of replacements 291system.cpu.icache.tags.tagsinuse 511.215260 # Cycle average of tags in use 292system.cpu.icache.tags.total_refs 59129947 # Total number of references to valid blocks. 293system.cpu.icache.tags.sampled_refs 920117 # Sample count of references to valid blocks. 294system.cpu.icache.tags.avg_refs 64.263509 # Average number of references to valid blocks. |
| 387system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. | 295system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. |
| 388system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor | 296system.cpu.icache.tags.occ_blocks::cpu.inst 511.215260 # Average occupied blocks per requestor |
| 389system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 390system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy 391system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 392system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 393system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 394system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id 395system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 297system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 298system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy 299system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 300system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id 301system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 302system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id 303system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 396system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses 397system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses 398system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits 399system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits 400system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits 401system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits 402system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits 403system.cpu.icache.overall_hits::total 59130077 # number of overall hits 404system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses 405system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses 406system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses 407system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses 408system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses 409system.cpu.icache.overall_misses::total 920230 # number of overall misses 410system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses) 411system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses) 412system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses 413system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses 414system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses 415system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses | 304system.cpu.icache.tags.tag_accesses 60970411 # Number of tag accesses 305system.cpu.icache.tags.data_accesses 60970411 # Number of data accesses 306system.cpu.icache.ReadReq_hits::cpu.inst 59129947 # number of ReadReq hits 307system.cpu.icache.ReadReq_hits::total 59129947 # number of ReadReq hits 308system.cpu.icache.demand_hits::cpu.inst 59129947 # number of demand (read+write) hits 309system.cpu.icache.demand_hits::total 59129947 # number of demand (read+write) hits 310system.cpu.icache.overall_hits::cpu.inst 59129947 # number of overall hits 311system.cpu.icache.overall_hits::total 59129947 # number of overall hits 312system.cpu.icache.ReadReq_misses::cpu.inst 920232 # number of ReadReq misses 313system.cpu.icache.ReadReq_misses::total 920232 # number of ReadReq misses 314system.cpu.icache.demand_misses::cpu.inst 920232 # number of demand (read+write) misses 315system.cpu.icache.demand_misses::total 920232 # number of demand (read+write) misses 316system.cpu.icache.overall_misses::cpu.inst 920232 # number of overall misses 317system.cpu.icache.overall_misses::total 920232 # number of overall misses 318system.cpu.icache.ReadReq_accesses::cpu.inst 60050179 # number of ReadReq accesses(hits+misses) 319system.cpu.icache.ReadReq_accesses::total 60050179 # number of ReadReq accesses(hits+misses) 320system.cpu.icache.demand_accesses::cpu.inst 60050179 # number of demand (read+write) accesses 321system.cpu.icache.demand_accesses::total 60050179 # number of demand (read+write) accesses 322system.cpu.icache.overall_accesses::cpu.inst 60050179 # number of overall (read+write) accesses 323system.cpu.icache.overall_accesses::total 60050179 # number of overall (read+write) accesses |
| 416system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 417system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 418system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 419system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 420system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 421system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 422system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 423system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 424system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 425system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 426system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 427system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 428system.cpu.icache.fast_writes 0 # number of fast writes performed 429system.cpu.icache.cache_copies 0 # number of cache copies performed 430system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 324system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses 325system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses 326system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses 327system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses 328system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 329system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 330system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 331system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 332system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 333system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 334system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 335system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 336system.cpu.icache.fast_writes 0 # number of fast writes performed 337system.cpu.icache.cache_copies 0 # number of cache copies performed 338system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 431system.cpu.l2cache.tags.replacements 992289 # number of replacements 432system.cpu.l2cache.tags.tagsinuse 65424.374569 # Cycle average of tags in use 433system.cpu.l2cache.tags.total_refs 2433258 # Total number of references to valid blocks. 434system.cpu.l2cache.tags.sampled_refs 1057452 # Sample count of references to valid blocks. 435system.cpu.l2cache.tags.avg_refs 2.301058 # Average number of references to valid blocks. | 339system.cpu.l2cache.tags.replacements 992295 # number of replacements 340system.cpu.l2cache.tags.tagsinuse 65424.374284 # Cycle average of tags in use 341system.cpu.l2cache.tags.total_refs 2433284 # Total number of references to valid blocks. 342system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks. 343system.cpu.l2cache.tags.avg_refs 2.301069 # Average number of references to valid blocks. |
| 436system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. | 344system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. |
| 437system.cpu.l2cache.tags.occ_blocks::writebacks 56310.337833 # Average occupied blocks per requestor 438system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.106258 # Average occupied blocks per requestor 439system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930478 # Average occupied blocks per requestor | 345system.cpu.l2cache.tags.occ_blocks::writebacks 56310.352234 # Average occupied blocks per requestor 346system.cpu.l2cache.tags.occ_blocks::cpu.inst 4866.099732 # Average occupied blocks per requestor 347system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922318 # Average occupied blocks per requestor |
| 440system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy 441system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy 442system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy 443system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy 444system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id 445system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id 446system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id 447system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id | 348system.cpu.l2cache.tags.occ_percent::writebacks 0.859228 # Average percentage of cache occupancy 349system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074251 # Average percentage of cache occupancy 350system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy 351system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy 352system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id 353system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id 354system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id 355system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id |
| 448system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id 449system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id | 356system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3055 # Occupied blocks per task id 357system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54043 # Occupied blocks per task id |
| 450system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id | 358system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id |
| 451system.cpu.l2cache.tags.tag_accesses 31737481 # Number of tag accesses 452system.cpu.l2cache.tags.data_accesses 31737481 # Number of data accesses 453system.cpu.l2cache.ReadReq_hits::cpu.inst 906806 # number of ReadReq hits 454system.cpu.l2cache.ReadReq_hits::cpu.data 811234 # number of ReadReq hits 455system.cpu.l2cache.ReadReq_hits::total 1718040 # number of ReadReq hits 456system.cpu.l2cache.Writeback_hits::writebacks 833484 # number of Writeback hits 457system.cpu.l2cache.Writeback_hits::total 833484 # number of Writeback hits | 359system.cpu.l2cache.tags.tag_accesses 31737815 # Number of tag accesses 360system.cpu.l2cache.tags.data_accesses 31737815 # Number of data accesses 361system.cpu.l2cache.ReadReq_hits::cpu.inst 906808 # number of ReadReq hits 362system.cpu.l2cache.ReadReq_hits::cpu.data 811247 # number of ReadReq hits 363system.cpu.l2cache.ReadReq_hits::total 1718055 # number of ReadReq hits 364system.cpu.l2cache.Writeback_hits::writebacks 833501 # number of Writeback hits 365system.cpu.l2cache.Writeback_hits::total 833501 # number of Writeback hits |
| 458system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 459system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits | 366system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 367system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits |
| 460system.cpu.l2cache.ReadExReq_hits::cpu.data 187241 # number of ReadExReq hits 461system.cpu.l2cache.ReadExReq_hits::total 187241 # number of ReadExReq hits 462system.cpu.l2cache.demand_hits::cpu.inst 906806 # number of demand (read+write) hits 463system.cpu.l2cache.demand_hits::cpu.data 998475 # number of demand (read+write) hits 464system.cpu.l2cache.demand_hits::total 1905281 # number of demand (read+write) hits 465system.cpu.l2cache.overall_hits::cpu.inst 906806 # number of overall hits 466system.cpu.l2cache.overall_hits::cpu.data 998475 # number of overall hits 467system.cpu.l2cache.overall_hits::total 1905281 # number of overall hits | 368system.cpu.l2cache.ReadExReq_hits::cpu.data 187243 # number of ReadExReq hits 369system.cpu.l2cache.ReadExReq_hits::total 187243 # number of ReadExReq hits 370system.cpu.l2cache.demand_hits::cpu.inst 906808 # number of demand (read+write) hits 371system.cpu.l2cache.demand_hits::cpu.data 998490 # number of demand (read+write) hits 372system.cpu.l2cache.demand_hits::total 1905298 # number of demand (read+write) hits 373system.cpu.l2cache.overall_hits::cpu.inst 906808 # number of overall hits 374system.cpu.l2cache.overall_hits::cpu.data 998490 # number of overall hits 375system.cpu.l2cache.overall_hits::total 1905298 # number of overall hits |
| 468system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses 469system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses 470system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses 471system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 472system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses | 376system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses 377system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses 378system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses 379system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses 380system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses |
| 473system.cpu.l2cache.ReadExReq_misses::cpu.data 117105 # number of ReadExReq misses 474system.cpu.l2cache.ReadExReq_misses::total 117105 # number of ReadExReq misses | 381system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses 382system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses |
| 475system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses | 383system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses |
| 476system.cpu.l2cache.demand_misses::cpu.data 1044745 # number of demand (read+write) misses 477system.cpu.l2cache.demand_misses::total 1058151 # number of demand (read+write) misses | 384system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses 385system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses |
| 478system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses | 386system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses |
| 479system.cpu.l2cache.overall_misses::cpu.data 1044745 # number of overall misses 480system.cpu.l2cache.overall_misses::total 1058151 # number of overall misses 481system.cpu.l2cache.ReadReq_accesses::cpu.inst 920212 # number of ReadReq accesses(hits+misses) 482system.cpu.l2cache.ReadReq_accesses::cpu.data 1738874 # number of ReadReq accesses(hits+misses) 483system.cpu.l2cache.ReadReq_accesses::total 2659086 # number of ReadReq accesses(hits+misses) 484system.cpu.l2cache.Writeback_accesses::writebacks 833484 # number of Writeback accesses(hits+misses) 485system.cpu.l2cache.Writeback_accesses::total 833484 # number of Writeback accesses(hits+misses) | 387system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses 388system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses 389system.cpu.l2cache.ReadReq_accesses::cpu.inst 920214 # number of ReadReq accesses(hits+misses) 390system.cpu.l2cache.ReadReq_accesses::cpu.data 1738887 # number of ReadReq accesses(hits+misses) 391system.cpu.l2cache.ReadReq_accesses::total 2659101 # number of ReadReq accesses(hits+misses) 392system.cpu.l2cache.Writeback_accesses::writebacks 833501 # number of Writeback accesses(hits+misses) 393system.cpu.l2cache.Writeback_accesses::total 833501 # number of Writeback accesses(hits+misses) |
| 486system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 487system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) | 394system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) 395system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) |
| 488system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) 489system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) 490system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses 491system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses 492system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses 493system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses 494system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses 495system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses | 396system.cpu.l2cache.ReadExReq_accesses::cpu.data 304354 # number of ReadExReq accesses(hits+misses) 397system.cpu.l2cache.ReadExReq_accesses::total 304354 # number of ReadExReq accesses(hits+misses) 398system.cpu.l2cache.demand_accesses::cpu.inst 920214 # number of demand (read+write) accesses 399system.cpu.l2cache.demand_accesses::cpu.data 2043241 # number of demand (read+write) accesses 400system.cpu.l2cache.demand_accesses::total 2963455 # number of demand (read+write) accesses 401system.cpu.l2cache.overall_accesses::cpu.inst 920214 # number of overall (read+write) accesses 402system.cpu.l2cache.overall_accesses::cpu.data 2043241 # number of overall (read+write) accesses 403system.cpu.l2cache.overall_accesses::total 2963455 # number of overall (read+write) accesses |
| 496system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses | 404system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014568 # miss rate for ReadReq accesses |
| 497system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533472 # miss rate for ReadReq accesses 498system.cpu.l2cache.ReadReq_miss_rate::total 0.353898 # miss rate for ReadReq accesses | 405system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533468 # miss rate for ReadReq accesses 406system.cpu.l2cache.ReadReq_miss_rate::total 0.353896 # miss rate for ReadReq accesses |
| 499system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 500system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses | 407system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses 408system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses |
| 501system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384776 # miss rate for ReadExReq accesses 502system.cpu.l2cache.ReadExReq_miss_rate::total 0.384776 # miss rate for ReadExReq accesses | 409system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384785 # miss rate for ReadExReq accesses 410system.cpu.l2cache.ReadExReq_miss_rate::total 0.384785 # miss rate for ReadExReq accesses |
| 503system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses | 411system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014568 # miss rate for demand accesses |
| 504system.cpu.l2cache.demand_miss_rate::cpu.data 0.511323 # miss rate for demand accesses | 412system.cpu.l2cache.demand_miss_rate::cpu.data 0.511320 # miss rate for demand accesses |
| 505system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses 506system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses | 413system.cpu.l2cache.demand_miss_rate::total 0.357069 # miss rate for demand accesses 414system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014568 # miss rate for overall accesses |
| 507system.cpu.l2cache.overall_miss_rate::cpu.data 0.511323 # miss rate for overall accesses | 415system.cpu.l2cache.overall_miss_rate::cpu.data 0.511320 # miss rate for overall accesses |
| 508system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses 509system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 510system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 511system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 512system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 513system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 514system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 515system.cpu.l2cache.fast_writes 0 # number of fast writes performed 516system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 416system.cpu.l2cache.overall_miss_rate::total 0.357069 # miss rate for overall accesses 417system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 418system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 419system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 420system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 421system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 422system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 423system.cpu.l2cache.fast_writes 0 # number of fast writes performed 424system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 517system.cpu.l2cache.writebacks::writebacks 74279 # number of writebacks 518system.cpu.l2cache.writebacks::total 74279 # number of writebacks | 425system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks 426system.cpu.l2cache.writebacks::total 74285 # number of writebacks |
| 519system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 427system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 520system.cpu.dcache.tags.replacements 2042707 # number of replacements 521system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use 522system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks. 523system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks. 524system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks. 525system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 526system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 527system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 528system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy 529system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 530system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id 531system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id 532system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id 533system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 534system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses 535system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses 536system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits 537system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits 538system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits 539system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits 540system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits 541system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 542system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 543system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits 544system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits 545system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits 546system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits 547system.cpu.dcache.overall_hits::total 13655981 # number of overall hits 548system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses 549system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses 550system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses 551system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses 552system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses 553system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses 554system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses 555system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses 556system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses 557system.cpu.dcache.overall_misses::total 2026074 # number of overall misses 558system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses) 559system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses) 560system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses) 561system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses) 562system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses) 563system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses) 564system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses) 565system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses) 566system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses 567system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses 568system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses 569system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses 570system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses 571system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses 572system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses 573system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses 574system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses 575system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses 576system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses 577system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses 578system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses 579system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses 580system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 581system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 582system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 583system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 584system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 585system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 586system.cpu.dcache.fast_writes 0 # number of fast writes performed 587system.cpu.dcache.cache_copies 0 # number of cache copies performed 588system.cpu.dcache.writebacks::writebacks 833484 # number of writebacks 589system.cpu.dcache.writebacks::total 833484 # number of writebacks 590system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 591system.cpu.toL2Bus.trans_dist::ReadReq 2666288 # Transaction distribution 592system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution | 428system.cpu.toL2Bus.trans_dist::ReadReq 2666303 # Transaction distribution 429system.cpu.toL2Bus.trans_dist::ReadResp 2666303 # Transaction distribution |
| 593system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution 594system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution | 430system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution 431system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution |
| 595system.cpu.toL2Bus.trans_dist::Writeback 833484 # Transaction distribution | 432system.cpu.toL2Bus.trans_dist::Writeback 833501 # Transaction distribution |
| 596system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution 597system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution | 433system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution 434system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution |
| 598system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution 599system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution 600system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840460 # Packet count per connected master and slave (bytes) 601system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954000 # Packet count per connected master and slave (bytes) 602system.cpu.toL2Bus.pkt_count::total 6794460 # Packet count per connected master and slave (bytes) 603system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894720 # Cumulative packet size per connected master and slave (bytes) 604system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184155182 # Cumulative packet size per connected master and slave (bytes) 605system.cpu.toL2Bus.pkt_size::total 243049902 # Cumulative packet size per connected master and slave (bytes) | 435system.cpu.toL2Bus.trans_dist::ReadExReq 304354 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadExResp 304354 # Transaction distribution 437system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1840464 # Packet count per connected master and slave (bytes) 438system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4954059 # Packet count per connected master and slave (bytes) 439system.cpu.toL2Bus.pkt_count::total 6794523 # Packet count per connected master and slave (bytes) 440system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 58894848 # Cumulative packet size per connected master and slave (bytes) 441system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184157614 # Cumulative packet size per connected master and slave (bytes) 442system.cpu.toL2Bus.pkt_size::total 243052462 # Cumulative packet size per connected master and slave (bytes) |
| 606system.cpu.toL2Bus.snoops 41883 # Total snoops (count) | 443system.cpu.toL2Bus.snoops 41883 # Total snoops (count) |
| 607system.cpu.toL2Bus.snoop_fanout::samples 3838676 # Request fanout histogram | 444system.cpu.toL2Bus.snoop_fanout::samples 3838716 # Request fanout histogram |
| 608system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram | 445system.cpu.toL2Bus.snoop_fanout::mean 1.010870 # Request fanout histogram |
| 609system.cpu.toL2Bus.snoop_fanout::stdev 0.103691 # Request fanout histogram | 446system.cpu.toL2Bus.snoop_fanout::stdev 0.103690 # Request fanout histogram |
| 610system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 611system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram | 447system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 448system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| 612system.cpu.toL2Bus.snoop_fanout::1 3796950 98.91% 98.91% # Request fanout histogram | 449system.cpu.toL2Bus.snoop_fanout::1 3796990 98.91% 98.91% # Request fanout histogram |
| 613system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram 614system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 615system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 616system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 450system.cpu.toL2Bus.snoop_fanout::2 41726 1.09% 100.00% # Request fanout histogram 451system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 452system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 453system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 617system.cpu.toL2Bus.snoop_fanout::total 3838676 # Request fanout histogram | 454system.cpu.toL2Bus.snoop_fanout::total 3838716 # Request fanout histogram 455system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 456system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). 457system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). 458system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. 459system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. 460system.disk0.dma_write_txs 395 # Number of DMA write transactions. 461system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). 462system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). 463system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). 464system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. 465system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. 466system.disk2.dma_write_txs 1 # Number of DMA write transactions. 467system.iobus.trans_dist::ReadReq 7358 # Transaction distribution 468system.iobus.trans_dist::ReadResp 7358 # Transaction distribution 469system.iobus.trans_dist::WriteReq 51390 # Transaction distribution 470system.iobus.trans_dist::WriteResp 9838 # Transaction distribution 471system.iobus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 472system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes) 473system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 476 # Packet count per connected master and slave (bytes) 474system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes) 475system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes) 476system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes) 477system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes) 478system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes) 479system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes) 480system.iobus.pkt_count_system.bridge.master::system.tsunami.ide-pciconf 294 # Packet count per connected master and slave (bytes) 481system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes) 482system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet-pciconf 180 # Packet count per connected master and slave (bytes) 483system.iobus.pkt_count_system.bridge.master::system.tsunami.pciconfig.pio 60 # Packet count per connected master and slave (bytes) 484system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes) 485system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes) 486system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes) 487system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes) 488system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes) 489system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 1904 # Cumulative packet size per connected master and slave (bytes) 490system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes) 491system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes) 492system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes) 493system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes) 494system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes) 495system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes) 496system.iobus.pkt_size_system.bridge.master::system.tsunami.ide-pciconf 410 # Cumulative packet size per connected master and slave (bytes) 497system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes) 498system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet-pciconf 299 # Cumulative packet size per connected master and slave (bytes) 499system.iobus.pkt_size_system.bridge.master::system.tsunami.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) 500system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes) 501system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes) 502system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes) 503system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes) 504system.iocache.tags.replacements 41686 # number of replacements 505system.iocache.tags.tagsinuse 1.225572 # Cycle average of tags in use 506system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 507system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 508system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 509system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit. 510system.iocache.tags.occ_blocks::tsunami.ide 1.225572 # Average occupied blocks per requestor 511system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy 512system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy 513system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id 514system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 515system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 516system.iocache.tags.tag_accesses 375534 # Number of tag accesses 517system.iocache.tags.data_accesses 375534 # Number of data accesses 518system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 519system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 520system.iocache.WriteInvalidateReq_misses::tsunami.ide 41552 # number of WriteInvalidateReq misses 521system.iocache.WriteInvalidateReq_misses::total 41552 # number of WriteInvalidateReq misses 522system.iocache.demand_misses::tsunami.ide 174 # number of demand (read+write) misses 523system.iocache.demand_misses::total 174 # number of demand (read+write) misses 524system.iocache.overall_misses::tsunami.ide 174 # number of overall misses 525system.iocache.overall_misses::total 174 # number of overall misses 526system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 527system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 528system.iocache.WriteInvalidateReq_accesses::tsunami.ide 41552 # number of WriteInvalidateReq accesses(hits+misses) 529system.iocache.WriteInvalidateReq_accesses::total 41552 # number of WriteInvalidateReq accesses(hits+misses) 530system.iocache.demand_accesses::tsunami.ide 174 # number of demand (read+write) accesses 531system.iocache.demand_accesses::total 174 # number of demand (read+write) accesses 532system.iocache.overall_accesses::tsunami.ide 174 # number of overall (read+write) accesses 533system.iocache.overall_accesses::total 174 # number of overall (read+write) accesses 534system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 535system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 536system.iocache.WriteInvalidateReq_miss_rate::tsunami.ide 1 # miss rate for WriteInvalidateReq accesses 537system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses 538system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 539system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 540system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 541system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 542system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 543system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 544system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 545system.iocache.blocked::no_targets 0 # number of cycles access was blocked 546system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 547system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 548system.iocache.fast_writes 0 # number of fast writes performed 549system.iocache.cache_copies 0 # number of cache copies performed 550system.iocache.writebacks::writebacks 41512 # number of writebacks 551system.iocache.writebacks::total 41512 # number of writebacks 552system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate 553system.membus.trans_dist::ReadReq 948404 # Transaction distribution 554system.membus.trans_dist::ReadResp 948404 # Transaction distribution 555system.membus.trans_dist::WriteReq 9838 # Transaction distribution 556system.membus.trans_dist::WriteResp 9838 # Transaction distribution 557system.membus.trans_dist::Writeback 115797 # Transaction distribution 558system.membus.trans_dist::WriteInvalidateReq 41552 # Transaction distribution 559system.membus.trans_dist::WriteInvalidateResp 41552 # Transaction distribution 560system.membus.trans_dist::UpgradeReq 132 # Transaction distribution 561system.membus.trans_dist::UpgradeResp 132 # Transaction distribution 562system.membus.trans_dist::ReadExReq 116991 # Transaction distribution 563system.membus.trans_dist::ReadExResp 116991 # Transaction distribution 564system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes) 565system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2190623 # Packet count per connected master and slave (bytes) 566system.membus.pkt_count_system.cpu.l2cache.mem_side::total 2224667 # Packet count per connected master and slave (bytes) 567system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 124964 # Packet count per connected master and slave (bytes) 568system.membus.pkt_count_system.iocache.mem_side::total 124964 # Packet count per connected master and slave (bytes) 569system.membus.pkt_count::total 2349631 # Packet count per connected master and slave (bytes) 570system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes) 571system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72468608 # Cumulative packet size per connected master and slave (bytes) 572system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72514734 # Cumulative packet size per connected master and slave (bytes) 573system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 5327232 # Cumulative packet size per connected master and slave (bytes) 574system.membus.pkt_size_system.iocache.mem_side::total 5327232 # Cumulative packet size per connected master and slave (bytes) 575system.membus.pkt_size::total 77841966 # Cumulative packet size per connected master and slave (bytes) 576system.membus.snoops 0 # Total snoops (count) 577system.membus.snoop_fanout::samples 1215692 # Request fanout histogram 578system.membus.snoop_fanout::mean 1 # Request fanout histogram 579system.membus.snoop_fanout::stdev 0 # Request fanout histogram 580system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 581system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 582system.membus.snoop_fanout::1 1215692 100.00% 100.00% # Request fanout histogram 583system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 584system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 585system.membus.snoop_fanout::min_value 1 # Request fanout histogram 586system.membus.snoop_fanout::max_value 1 # Request fanout histogram 587system.membus.snoop_fanout::total 1215692 # Request fanout histogram 588system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA 589system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA 590system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA 591system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA 592system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU 593system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post 594system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR 595system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU 596system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post 597system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR 598system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU 599system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post 600system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR 601system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU 602system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post 603system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR 604system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU 605system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post 606system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR 607system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU 608system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post 609system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR 610system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU 611system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post 612system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR 613system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 614system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 615system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 616system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 617system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 618system.tsunami.ethernet.droppedPackets 0 # number of packets dropped |
| 618 619---------- End Simulation Statistics ---------- | 619 620---------- End Simulation Statistics ---------- |