1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829332 # Number of seconds simulated 4sim_ticks 1829332269000 # Number of ticks simulated 5final_tick 1829332269000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 2947908 # Simulator instruction rate (inst/s) 8host_op_rate 2947905 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 89820884398 # Simulator tick rate (ticks/s) 10host_mem_usage 305960 # Number of bytes of host memory used 11host_seconds 20.37 # Real time elapsed on the host |
12sim_insts 60038305 # Number of instructions simulated 13sim_ops 60038305 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory 16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory 17system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory --- 163 unchanged lines hidden (view full) --- 183system.physmem.readRowHits 0 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate nan # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 187system.physmem.avgGap nan # Average gap between requests 188system.membus.throughput 42552540 # Throughput (bytes/s) 189system.membus.data_through_bus 77842734 # Total data (bytes) 190system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
191system.iocache.tags.replacements 41686 # number of replacements 192system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use 193system.iocache.tags.total_refs 0 # Total number of references to valid blocks. 194system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks. 195system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. 196system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit. 197system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor 198system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy 199system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy |
200system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 201system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 202system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses 203system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses 204system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 205system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 206system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 207system.iocache.overall_misses::total 41726 # number of overall misses --- 203 unchanged lines hidden (view full) --- 411system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU 412system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post 413system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR 414system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post 415system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU 416system.tsunami.ethernet.droppedPackets 0 # number of packets dropped 417system.iobus.throughput 1480181 # Throughput (bytes/s) 418system.iobus.data_through_bus 2707742 # Total data (bytes) |
419system.cpu.icache.tags.replacements 919609 # number of replacements 420system.cpu.icache.tags.tagsinuse 511.215244 # Cycle average of tags in use 421system.cpu.icache.tags.total_refs 59129907 # Total number of references to valid blocks. 422system.cpu.icache.tags.sampled_refs 920121 # Sample count of references to valid blocks. 423system.cpu.icache.tags.avg_refs 64.263186 # Average number of references to valid blocks. 424system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit. 425system.cpu.icache.tags.occ_blocks::cpu.inst 511.215244 # Average occupied blocks per requestor 426system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy 427system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy |
428system.cpu.icache.ReadReq_hits::cpu.inst 59129907 # number of ReadReq hits 429system.cpu.icache.ReadReq_hits::total 59129907 # number of ReadReq hits 430system.cpu.icache.demand_hits::cpu.inst 59129907 # number of demand (read+write) hits 431system.cpu.icache.demand_hits::total 59129907 # number of demand (read+write) hits 432system.cpu.icache.overall_hits::cpu.inst 59129907 # number of overall hits 433system.cpu.icache.overall_hits::total 59129907 # number of overall hits 434system.cpu.icache.ReadReq_misses::cpu.inst 920236 # number of ReadReq misses 435system.cpu.icache.ReadReq_misses::total 920236 # number of ReadReq misses --- 17 unchanged lines hidden (view full) --- 453system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 454system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 455system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 456system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 457system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 458system.cpu.icache.fast_writes 0 # number of fast writes performed 459system.cpu.icache.cache_copies 0 # number of cache copies performed 460system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
461system.cpu.l2cache.tags.replacements 992301 # number of replacements 462system.cpu.l2cache.tags.tagsinuse 65424.374219 # Cycle average of tags in use 463system.cpu.l2cache.tags.total_refs 2433263 # Total number of references to valid blocks. 464system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks. 465system.cpu.l2cache.tags.avg_refs 2.301036 # Average number of references to valid blocks. 466system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. |
467system.cpu.l2cache.tags.occ_blocks::writebacks 56309.127841 # Average occupied blocks per requestor |
468system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.327126 # Average occupied blocks per requestor 469system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.919252 # Average occupied blocks per requestor |
470system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy 471system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy 472system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy |
473system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy |
474system.cpu.l2cache.ReadReq_hits::cpu.inst 906812 # number of ReadReq hits 475system.cpu.l2cache.ReadReq_hits::cpu.data 811232 # number of ReadReq hits 476system.cpu.l2cache.ReadReq_hits::total 1718044 # number of ReadReq hits 477system.cpu.l2cache.Writeback_hits::writebacks 833497 # number of Writeback hits 478system.cpu.l2cache.Writeback_hits::total 833497 # number of Writeback hits 479system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits 480system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits 481system.cpu.l2cache.ReadExReq_hits::cpu.data 187230 # number of ReadExReq hits --- 51 unchanged lines hidden (view full) --- 533system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 534system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 535system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 536system.cpu.l2cache.fast_writes 0 # number of fast writes performed 537system.cpu.l2cache.cache_copies 0 # number of cache copies performed 538system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks 539system.cpu.l2cache.writebacks::total 74291 # number of writebacks 540system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
541system.cpu.dcache.tags.replacements 2042706 # number of replacements 542system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use 543system.cpu.dcache.tags.total_refs 14038427 # Total number of references to valid blocks. 544system.cpu.dcache.tags.sampled_refs 2043218 # Sample count of references to valid blocks. 545system.cpu.dcache.tags.avg_refs 6.870744 # Average number of references to valid blocks. 546system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit. 547system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor 548system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy 549system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy |
550system.cpu.dcache.ReadReq_hits::cpu.data 7807777 # number of ReadReq hits 551system.cpu.dcache.ReadReq_hits::total 7807777 # number of ReadReq hits 552system.cpu.dcache.WriteReq_hits::cpu.data 5848211 # number of WriteReq hits 553system.cpu.dcache.WriteReq_hits::total 5848211 # number of WriteReq hits 554system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits 555system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits 556system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits 557system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits --- 52 unchanged lines hidden --- |