1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.829332 # Number of seconds simulated 4sim_ticks 1829331993500 # Number of ticks simulated 5final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 1840131 # Simulator instruction rate (inst/s) 8host_op_rate 1840130 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 56067507873 # Simulator tick rate (ticks/s) 10host_mem_usage 330836 # Number of bytes of host memory used 11host_seconds 32.63 # Real time elapsed on the host |
12sim_insts 60038469 # Number of instructions simulated 13sim_ops 60038469 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory 18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 67686528 # Number of bytes read from this memory --- 257 unchanged lines hidden (view full) --- 277system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses 278system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses 279system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 280system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 281system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 282system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 283system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 284system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
285system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks 286system.cpu.dcache.writebacks::total 833475 # number of writebacks |
287system.cpu.icache.tags.replacements 919603 # number of replacements 288system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use 289system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks. 290system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks. 291system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks. 292system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit. 293system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor 294system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy --- 30 unchanged lines hidden (view full) --- 325system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses 326system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses 327system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 328system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 329system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 330system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 331system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 332system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
333system.cpu.icache.writebacks::writebacks 919603 # number of writebacks 334system.cpu.icache.writebacks::total 919603 # number of writebacks |
335system.cpu.l2cache.tags.replacements 992419 # number of replacements 336system.cpu.l2cache.tags.tagsinuse 65424.374401 # Cycle average of tags in use 337system.cpu.l2cache.tags.total_refs 4560132 # Total number of references to valid blocks. 338system.cpu.l2cache.tags.sampled_refs 1057582 # Sample count of references to valid blocks. 339system.cpu.l2cache.tags.avg_refs 4.311847 # Average number of references to valid blocks. 340system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. 341system.cpu.l2cache.tags.occ_blocks::writebacks 56331.541205 # Average occupied blocks per requestor 342system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.327000 # Average occupied blocks per requestor --- 76 unchanged lines hidden (view full) --- 419system.cpu.l2cache.overall_miss_rate::cpu.data 0.511303 # miss rate for overall accesses 420system.cpu.l2cache.overall_miss_rate::total 0.357016 # miss rate for overall accesses 421system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 422system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 423system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 424system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 425system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 426system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
427system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks 428system.cpu.l2cache.writebacks::total 74359 # number of writebacks |
429system.cpu.toL2Bus.snoop_filter.tot_requests 5925776 # Total number of requests made to the snoop filter. 430system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962432 # Number of requests hitting in the snoop filter with a single holder of the requested data. 431system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 432system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter. 433system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 434system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 435system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution 436system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution --- 81 unchanged lines hidden (view full) --- 518system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id 519system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id 520system.iocache.tags.tag_accesses 375534 # Number of tag accesses 521system.iocache.tags.data_accesses 375534 # Number of data accesses 522system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses 523system.iocache.ReadReq_misses::total 174 # number of ReadReq misses 524system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses 525system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses |
526system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses 527system.iocache.demand_misses::total 41726 # number of demand (read+write) misses 528system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses 529system.iocache.overall_misses::total 41726 # number of overall misses |
530system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses) 531system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses) 532system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses) 533system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses) |
534system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses 535system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses 536system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses 537system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses |
538system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses 539system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses 540system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses 541system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses 542system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses 543system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses 544system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses 545system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses 546system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 547system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked 548system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked 549system.iocache.blocked::no_targets 0 # number of cycles access was blocked 550system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 551system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
552system.iocache.writebacks::writebacks 41512 # number of writebacks 553system.iocache.writebacks::total 41512 # number of writebacks |
554system.membus.trans_dist::ReadReq 7184 # Transaction distribution 555system.membus.trans_dist::ReadResp 948291 # Transaction distribution 556system.membus.trans_dist::WriteReq 9838 # Transaction distribution 557system.membus.trans_dist::WriteResp 9838 # Transaction distribution 558system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution 559system.membus.trans_dist::CleanEvict 917188 # Transaction distribution 560system.membus.trans_dist::UpgradeReq 147 # Transaction distribution 561system.membus.trans_dist::UpgradeResp 147 # Transaction distribution --- 62 unchanged lines hidden --- |