1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.829332 # Number of seconds simulated
4sim_ticks 1829332258000 # Number of ticks simulated
5final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.829332 # Number of seconds simulated
4sim_ticks 1829332258000 # Number of ticks simulated
5final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1630624 # Simulator instruction rate (inst/s)
8host_op_rate 1630623 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 49684114233 # Simulator tick rate (ticks/s)
10host_mem_usage 305868 # Number of bytes of host memory used
11host_seconds 36.82 # Real time elapsed on the host
| 7host_inst_rate 1538182 # Simulator instruction rate (inst/s)
8host_op_rate 1538181 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 46867449524 # Simulator tick rate (ticks/s)
10host_mem_usage 350908 # Number of bytes of host memory used
11host_seconds 39.03 # Real time elapsed on the host
|
12sim_insts 60038305 # Number of instructions simulated
13sim_ops 60038305 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory
16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
17system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
20system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory
21system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory
22system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory
24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s)
41system.membus.throughput 42552540 # Throughput (bytes/s)
42system.membus.data_through_bus 77842734 # Total data (bytes)
43system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
44system.iocache.tags.replacements 41686 # number of replacements
45system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use
46system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
47system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
48system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
49system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
50system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor
51system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
52system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
53system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
54system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
55system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
56system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
57system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
58system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
59system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
60system.iocache.overall_misses::total 41726 # number of overall misses
61system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
62system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
63system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
64system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
65system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
66system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
67system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
68system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
69system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
70system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
71system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
72system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
73system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
74system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
75system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
76system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
77system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
78system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
79system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
80system.iocache.blocked::no_targets 0 # number of cycles access was blocked
81system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
82system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
83system.iocache.fast_writes 0 # number of fast writes performed
84system.iocache.cache_copies 0 # number of cache copies performed
85system.iocache.writebacks::writebacks 41512 # number of writebacks
86system.iocache.writebacks::total 41512 # number of writebacks
87system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
88system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
89system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
90system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
91system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
92system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
93system.disk0.dma_write_txs 395 # Number of DMA write transactions.
94system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
95system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
96system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
97system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
98system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
99system.disk2.dma_write_txs 1 # Number of DMA write transactions.
100system.cpu.dtb.fetch_hits 0 # ITB hits
101system.cpu.dtb.fetch_misses 0 # ITB misses
102system.cpu.dtb.fetch_acv 0 # ITB acv
103system.cpu.dtb.fetch_accesses 0 # ITB accesses
104system.cpu.dtb.read_hits 9710427 # DTB read hits
105system.cpu.dtb.read_misses 10329 # DTB read misses
106system.cpu.dtb.read_acv 210 # DTB read access violations
107system.cpu.dtb.read_accesses 728856 # DTB read accesses
108system.cpu.dtb.write_hits 6352498 # DTB write hits
109system.cpu.dtb.write_misses 1142 # DTB write misses
110system.cpu.dtb.write_acv 157 # DTB write access violations
111system.cpu.dtb.write_accesses 291931 # DTB write accesses
112system.cpu.dtb.data_hits 16062925 # DTB hits
113system.cpu.dtb.data_misses 11471 # DTB misses
114system.cpu.dtb.data_acv 367 # DTB access violations
115system.cpu.dtb.data_accesses 1020787 # DTB accesses
116system.cpu.itb.fetch_hits 4974648 # ITB hits
117system.cpu.itb.fetch_misses 5006 # ITB misses
118system.cpu.itb.fetch_acv 184 # ITB acv
119system.cpu.itb.fetch_accesses 4979654 # ITB accesses
120system.cpu.itb.read_hits 0 # DTB read hits
121system.cpu.itb.read_misses 0 # DTB read misses
122system.cpu.itb.read_acv 0 # DTB read access violations
123system.cpu.itb.read_accesses 0 # DTB read accesses
124system.cpu.itb.write_hits 0 # DTB write hits
125system.cpu.itb.write_misses 0 # DTB write misses
126system.cpu.itb.write_acv 0 # DTB write access violations
127system.cpu.itb.write_accesses 0 # DTB write accesses
128system.cpu.itb.data_hits 0 # DTB hits
129system.cpu.itb.data_misses 0 # DTB misses
130system.cpu.itb.data_acv 0 # DTB access violations
131system.cpu.itb.data_accesses 0 # DTB accesses
| 12sim_insts 60038305 # Number of instructions simulated
13sim_ops 60038305 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 66839424 # Number of bytes read from this memory
16system.physmem.bytes_read::tsunami.ide 2652288 # Number of bytes read from this memory
17system.physmem.bytes_read::total 70349696 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
20system.physmem.bytes_written::writebacks 7411392 # Number of bytes written to this memory
21system.physmem.bytes_written::total 7411392 # Number of bytes written to this memory
22system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 1044366 # Number of read requests responded to by this memory
24system.physmem.num_reads::tsunami.ide 41442 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 1099214 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 115803 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 115803 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 36537607 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::tsunami.ide 1449867 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::total 38456489 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
34system.physmem.bw_write::writebacks 4051419 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_write::total 4051419 # Write bandwidth from this memory (bytes/s)
36system.physmem.bw_total::writebacks 4051419 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::cpu.data 36537607 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::tsunami.ide 1449867 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s)
41system.membus.throughput 42552540 # Throughput (bytes/s)
42system.membus.data_through_bus 77842734 # Total data (bytes)
43system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
44system.iocache.tags.replacements 41686 # number of replacements
45system.iocache.tags.tagsinuse 1.225570 # Cycle average of tags in use
46system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
47system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
48system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
49system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
50system.iocache.tags.occ_blocks::tsunami.ide 1.225570 # Average occupied blocks per requestor
51system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
52system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
53system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
54system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
55system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
56system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses
57system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
58system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
59system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
60system.iocache.overall_misses::total 41726 # number of overall misses
61system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
62system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
63system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
64system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
65system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
66system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
67system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
68system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
69system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
70system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
71system.iocache.WriteReq_miss_rate::tsunami.ide 1 # miss rate for WriteReq accesses
72system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
73system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
74system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
75system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
76system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
77system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
78system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
79system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
80system.iocache.blocked::no_targets 0 # number of cycles access was blocked
81system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
82system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
83system.iocache.fast_writes 0 # number of fast writes performed
84system.iocache.cache_copies 0 # number of cache copies performed
85system.iocache.writebacks::writebacks 41512 # number of writebacks
86system.iocache.writebacks::total 41512 # number of writebacks
87system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
88system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
89system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
90system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
91system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
92system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
93system.disk0.dma_write_txs 395 # Number of DMA write transactions.
94system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
95system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
96system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
97system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
98system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
99system.disk2.dma_write_txs 1 # Number of DMA write transactions.
100system.cpu.dtb.fetch_hits 0 # ITB hits
101system.cpu.dtb.fetch_misses 0 # ITB misses
102system.cpu.dtb.fetch_acv 0 # ITB acv
103system.cpu.dtb.fetch_accesses 0 # ITB accesses
104system.cpu.dtb.read_hits 9710427 # DTB read hits
105system.cpu.dtb.read_misses 10329 # DTB read misses
106system.cpu.dtb.read_acv 210 # DTB read access violations
107system.cpu.dtb.read_accesses 728856 # DTB read accesses
108system.cpu.dtb.write_hits 6352498 # DTB write hits
109system.cpu.dtb.write_misses 1142 # DTB write misses
110system.cpu.dtb.write_acv 157 # DTB write access violations
111system.cpu.dtb.write_accesses 291931 # DTB write accesses
112system.cpu.dtb.data_hits 16062925 # DTB hits
113system.cpu.dtb.data_misses 11471 # DTB misses
114system.cpu.dtb.data_acv 367 # DTB access violations
115system.cpu.dtb.data_accesses 1020787 # DTB accesses
116system.cpu.itb.fetch_hits 4974648 # ITB hits
117system.cpu.itb.fetch_misses 5006 # ITB misses
118system.cpu.itb.fetch_acv 184 # ITB acv
119system.cpu.itb.fetch_accesses 4979654 # ITB accesses
120system.cpu.itb.read_hits 0 # DTB read hits
121system.cpu.itb.read_misses 0 # DTB read misses
122system.cpu.itb.read_acv 0 # DTB read access violations
123system.cpu.itb.read_accesses 0 # DTB read accesses
124system.cpu.itb.write_hits 0 # DTB write hits
125system.cpu.itb.write_misses 0 # DTB write misses
126system.cpu.itb.write_acv 0 # DTB write access violations
127system.cpu.itb.write_accesses 0 # DTB write accesses
128system.cpu.itb.data_hits 0 # DTB hits
129system.cpu.itb.data_misses 0 # DTB misses
130system.cpu.itb.data_acv 0 # DTB access violations
131system.cpu.itb.data_accesses 0 # DTB accesses
|
132system.cpu.numCycles 3658664408 # number of cpu cycles simulated
| 132system.cpu.numCycles 3658664517 # number of cpu cycles simulated
|
133system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
134system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
135system.cpu.committedInsts 60038305 # Number of instructions committed
136system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed
137system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses
138system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
139system.cpu.num_func_calls 1484182 # number of times a function call or return occured
140system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls
141system.cpu.num_int_insts 55913521 # number of integer instructions
142system.cpu.num_fp_insts 324460 # number of float instructions
143system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read
144system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written
145system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
146system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
147system.cpu.num_mem_refs 16115709 # number of memory refs
148system.cpu.num_load_insts 9747513 # Number of load instructions
149system.cpu.num_store_insts 6368196 # Number of store instructions
| 133system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
134system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
135system.cpu.committedInsts 60038305 # Number of instructions committed
136system.cpu.committedOps 60038305 # Number of ops (including micro ops) committed
137system.cpu.num_int_alu_accesses 55913521 # Number of integer alu accesses
138system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
139system.cpu.num_func_calls 1484182 # number of times a function call or return occured
140system.cpu.num_conditional_control_insts 7110746 # number of instructions that are conditional controls
141system.cpu.num_int_insts 55913521 # number of integer instructions
142system.cpu.num_fp_insts 324460 # number of float instructions
143system.cpu.num_int_register_reads 76953934 # number of times the integer registers were read
144system.cpu.num_int_register_writes 41740225 # number of times the integer registers were written
145system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
146system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
147system.cpu.num_mem_refs 16115709 # number of memory refs
148system.cpu.num_load_insts 9747513 # Number of load instructions
149system.cpu.num_store_insts 6368196 # Number of store instructions
|
150system.cpu.num_idle_cycles 3598608979.180807 # Number of idle cycles
151system.cpu.num_busy_cycles 60055428.819193 # Number of busy cycles
| 150system.cpu.num_idle_cycles 3598609086.391618 # Number of idle cycles
151system.cpu.num_busy_cycles 60055430.608382 # Number of busy cycles
|
152system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
153system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
154system.cpu.kern.inst.arm 0 # number of arm instructions executed
155system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
156system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
157system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
158system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
159system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
160system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
161system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
162system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
163system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
164system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
165system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
166system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
167system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl
168system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
169system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
170system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl
171system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl
172system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
173system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
174system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
175system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
176system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl
177system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
178system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
179system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
180system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
181system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
182system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
183system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
184system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
185system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
186system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
187system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
188system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
189system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
190system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
191system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
192system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
193system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
194system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
195system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
196system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
197system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
198system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
199system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
200system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
201system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
202system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
203system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
204system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
205system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
206system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
207system.cpu.kern.syscall::total 326 # number of syscalls executed
208system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
209system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
210system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
211system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
212system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
213system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
214system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
215system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
216system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
217system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
218system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
219system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
220system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
221system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
222system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
223system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
224system.cpu.kern.callpal::total 192180 # number of callpals executed
225system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
226system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
227system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
228system.cpu.kern.mode_good::kernel 1909
229system.cpu.kern.mode_good::user 1738
230system.cpu.kern.mode_good::idle 171
231system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
232system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
233system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
234system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches
235system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode
236system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
237system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode
238system.cpu.kern.swap_context 4178 # number of times the context was actually changed
239system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
240system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
241system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
242system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
243system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
244system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
245system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
246system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
247system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
248system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
249system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
250system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
251system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
252system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
253system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
254system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
255system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
256system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
257system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
258system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
259system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
260system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
261system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
262system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
263system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
264system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
265system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
266system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
267system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
268system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
269system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
270system.iobus.throughput 1480181 # Throughput (bytes/s)
271system.iobus.data_through_bus 2707742 # Total data (bytes)
272system.cpu.icache.tags.replacements 919594 # number of replacements
273system.cpu.icache.tags.tagsinuse 511.215243 # Cycle average of tags in use
274system.cpu.icache.tags.total_refs 59129922 # Total number of references to valid blocks.
275system.cpu.icache.tags.sampled_refs 920106 # Sample count of references to valid blocks.
276system.cpu.icache.tags.avg_refs 64.264250 # Average number of references to valid blocks.
277system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
278system.cpu.icache.tags.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor
279system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
280system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
281system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits
282system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits
283system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits
284system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits
285system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits
286system.cpu.icache.overall_hits::total 59129922 # number of overall hits
287system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses
288system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses
289system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses
290system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses
291system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses
292system.cpu.icache.overall_misses::total 920221 # number of overall misses
293system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses)
294system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses)
295system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses
296system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses
297system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses
298system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses
299system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
300system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
301system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
302system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
303system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
304system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
305system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
306system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
307system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
308system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
309system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
310system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
311system.cpu.icache.fast_writes 0 # number of fast writes performed
312system.cpu.icache.cache_copies 0 # number of cache copies performed
313system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
314system.cpu.l2cache.tags.replacements 992301 # number of replacements
315system.cpu.l2cache.tags.tagsinuse 65424.374305 # Cycle average of tags in use
316system.cpu.l2cache.tags.total_refs 2433239 # Total number of references to valid blocks.
317system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks.
318system.cpu.l2cache.tags.avg_refs 2.301014 # Average number of references to valid blocks.
319system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
320system.cpu.l2cache.tags.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor
321system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor
322system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor
323system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
324system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
325system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
326system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
327system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits
328system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits
329system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits
330system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
331system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
332system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
333system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
334system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits
335system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits
336system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits
337system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits
338system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits
339system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits
340system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits
341system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits
342system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
343system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
344system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
345system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
346system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
347system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses
348system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses
349system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
350system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses
351system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses
352system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
353system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses
354system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses
355system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses)
356system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses)
357system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses)
358system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
359system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
360system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
361system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
362system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
363system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
364system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses
365system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses
366system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses
367system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses
368system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses
369system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses
370system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses
371system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses
372system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses
373system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
374system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
375system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses
376system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses
377system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses
378system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses
379system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses
380system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses
381system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses
382system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses
383system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
384system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
385system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
386system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
387system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
388system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
389system.cpu.l2cache.fast_writes 0 # number of fast writes performed
390system.cpu.l2cache.cache_copies 0 # number of cache copies performed
391system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks
392system.cpu.l2cache.writebacks::total 74291 # number of writebacks
393system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
394system.cpu.dcache.tags.replacements 2042702 # number of replacements
395system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
396system.cpu.dcache.tags.total_refs 14038431 # Total number of references to valid blocks.
397system.cpu.dcache.tags.sampled_refs 2043214 # Sample count of references to valid blocks.
398system.cpu.dcache.tags.avg_refs 6.870759 # Average number of references to valid blocks.
399system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
400system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
401system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
402system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
403system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits
404system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits
405system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits
406system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits
407system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
408system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
409system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
410system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
411system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits
412system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits
413system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits
414system.cpu.dcache.overall_hits::total 13655992 # number of overall hits
415system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses
416system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses
417system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
418system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
419system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
420system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
421system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses
422system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses
423system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses
424system.cpu.dcache.overall_misses::total 2026069 # number of overall misses
425system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses)
426system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
427system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
428system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
429system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
430system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
431system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
432system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
433system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses
434system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses
435system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses
436system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses
437system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
438system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
439system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
440system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
441system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
442system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
443system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
444system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
445system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
446system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
447system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
448system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
449system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
450system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
451system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
452system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
453system.cpu.dcache.fast_writes 0 # number of fast writes performed
454system.cpu.dcache.cache_copies 0 # number of cache copies performed
455system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
456system.cpu.dcache.writebacks::total 833491 # number of writebacks
457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
458system.cpu.toL2Bus.throughput 132867917 # Throughput (bytes/s)
459system.cpu.toL2Bus.data_through_bus 243049454 # Total data (bytes)
460system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes)
461
462---------- End Simulation Statistics ----------
| 152system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
153system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
154system.cpu.kern.inst.arm 0 # number of arm instructions executed
155system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
156system.cpu.kern.inst.hwrei 211319 # number of hwrei instructions executed
157system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
158system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
159system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
160system.cpu.kern.ipl_count::31 105623 57.86% 100.00% # number of times we switched to this ipl
161system.cpu.kern.ipl_count::total 182562 # number of times we switched to this ipl
162system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
163system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
164system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
165system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
166system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
167system.cpu.kern.ipl_ticks::0 1811927407500 99.05% 99.05% # number of cycles we spent at this ipl
168system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
169system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
170system.cpu.kern.ipl_ticks::31 17304295000 0.95% 100.00% # number of cycles we spent at this ipl
171system.cpu.kern.ipl_ticks::total 1829332050500 # number of cycles we spent at this ipl
172system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
173system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
174system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
175system.cpu.kern.ipl_used::31 0.695521 # fraction of swpipl calls that actually changed the ipl
176system.cpu.kern.ipl_used::total 0.816353 # fraction of swpipl calls that actually changed the ipl
177system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
178system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
179system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
180system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
181system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
182system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
183system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
184system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
185system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
186system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
187system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
188system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
189system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
190system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
191system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
192system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
193system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
194system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
195system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
196system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
197system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
198system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
199system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
200system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
201system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
202system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
203system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
204system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
205system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
206system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
207system.cpu.kern.syscall::total 326 # number of syscalls executed
208system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
209system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
210system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
211system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
212system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
213system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
214system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
215system.cpu.kern.callpal::swpipl 175249 91.19% 93.40% # number of callpals executed
216system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
217system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
218system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
219system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
220system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
221system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
222system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
223system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
224system.cpu.kern.callpal::total 192180 # number of callpals executed
225system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
226system.cpu.kern.mode_switch::user 1738 # number of protection mode switches
227system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
228system.cpu.kern.mode_good::kernel 1909
229system.cpu.kern.mode_good::user 1738
230system.cpu.kern.mode_good::idle 171
231system.cpu.kern.mode_switch_good::kernel 0.320894 # fraction of useful protection mode switches
232system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
233system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
234system.cpu.kern.mode_switch_good::total 0.390229 # fraction of useful protection mode switches
235system.cpu.kern.mode_ticks::kernel 26834202500 1.47% 1.47% # number of ticks spent at the given mode
236system.cpu.kern.mode_ticks::user 1465074000 0.08% 1.55% # number of ticks spent at the given mode
237system.cpu.kern.mode_ticks::idle 1801032773000 98.45% 100.00% # number of ticks spent at the given mode
238system.cpu.kern.swap_context 4178 # number of times the context was actually changed
239system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
240system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
241system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
242system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
243system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
244system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
245system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
246system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
247system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
248system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
249system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
250system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
251system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
252system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
253system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
254system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
255system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
256system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
257system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
258system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
259system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
260system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
261system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
262system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
263system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
264system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
265system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
266system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
267system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
268system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
269system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
270system.iobus.throughput 1480181 # Throughput (bytes/s)
271system.iobus.data_through_bus 2707742 # Total data (bytes)
272system.cpu.icache.tags.replacements 919594 # number of replacements
273system.cpu.icache.tags.tagsinuse 511.215243 # Cycle average of tags in use
274system.cpu.icache.tags.total_refs 59129922 # Total number of references to valid blocks.
275system.cpu.icache.tags.sampled_refs 920106 # Sample count of references to valid blocks.
276system.cpu.icache.tags.avg_refs 64.264250 # Average number of references to valid blocks.
277system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
278system.cpu.icache.tags.occ_blocks::cpu.inst 511.215243 # Average occupied blocks per requestor
279system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
280system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
281system.cpu.icache.ReadReq_hits::cpu.inst 59129922 # number of ReadReq hits
282system.cpu.icache.ReadReq_hits::total 59129922 # number of ReadReq hits
283system.cpu.icache.demand_hits::cpu.inst 59129922 # number of demand (read+write) hits
284system.cpu.icache.demand_hits::total 59129922 # number of demand (read+write) hits
285system.cpu.icache.overall_hits::cpu.inst 59129922 # number of overall hits
286system.cpu.icache.overall_hits::total 59129922 # number of overall hits
287system.cpu.icache.ReadReq_misses::cpu.inst 920221 # number of ReadReq misses
288system.cpu.icache.ReadReq_misses::total 920221 # number of ReadReq misses
289system.cpu.icache.demand_misses::cpu.inst 920221 # number of demand (read+write) misses
290system.cpu.icache.demand_misses::total 920221 # number of demand (read+write) misses
291system.cpu.icache.overall_misses::cpu.inst 920221 # number of overall misses
292system.cpu.icache.overall_misses::total 920221 # number of overall misses
293system.cpu.icache.ReadReq_accesses::cpu.inst 60050143 # number of ReadReq accesses(hits+misses)
294system.cpu.icache.ReadReq_accesses::total 60050143 # number of ReadReq accesses(hits+misses)
295system.cpu.icache.demand_accesses::cpu.inst 60050143 # number of demand (read+write) accesses
296system.cpu.icache.demand_accesses::total 60050143 # number of demand (read+write) accesses
297system.cpu.icache.overall_accesses::cpu.inst 60050143 # number of overall (read+write) accesses
298system.cpu.icache.overall_accesses::total 60050143 # number of overall (read+write) accesses
299system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
300system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
301system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
302system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
303system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
304system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
305system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
306system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
307system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
308system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
309system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
310system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
311system.cpu.icache.fast_writes 0 # number of fast writes performed
312system.cpu.icache.cache_copies 0 # number of cache copies performed
313system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
314system.cpu.l2cache.tags.replacements 992301 # number of replacements
315system.cpu.l2cache.tags.tagsinuse 65424.374305 # Cycle average of tags in use
316system.cpu.l2cache.tags.total_refs 2433239 # Total number of references to valid blocks.
317system.cpu.l2cache.tags.sampled_refs 1057464 # Sample count of references to valid blocks.
318system.cpu.l2cache.tags.avg_refs 2.301014 # Average number of references to valid blocks.
319system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
320system.cpu.l2cache.tags.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor
321system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor
322system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.922119 # Average occupied blocks per requestor
323system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
324system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
325system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
326system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
327system.cpu.l2cache.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits
328system.cpu.l2cache.ReadReq_hits::cpu.data 811229 # number of ReadReq hits
329system.cpu.l2cache.ReadReq_hits::total 1718026 # number of ReadReq hits
330system.cpu.l2cache.Writeback_hits::writebacks 833491 # number of Writeback hits
331system.cpu.l2cache.Writeback_hits::total 833491 # number of Writeback hits
332system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
333system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
334system.cpu.l2cache.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits
335system.cpu.l2cache.ReadExReq_hits::total 187229 # number of ReadExReq hits
336system.cpu.l2cache.demand_hits::cpu.inst 906797 # number of demand (read+write) hits
337system.cpu.l2cache.demand_hits::cpu.data 998458 # number of demand (read+write) hits
338system.cpu.l2cache.demand_hits::total 1905255 # number of demand (read+write) hits
339system.cpu.l2cache.overall_hits::cpu.inst 906797 # number of overall hits
340system.cpu.l2cache.overall_hits::cpu.data 998458 # number of overall hits
341system.cpu.l2cache.overall_hits::total 1905255 # number of overall hits
342system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
343system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
344system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
345system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
346system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
347system.cpu.l2cache.ReadExReq_misses::cpu.data 117117 # number of ReadExReq misses
348system.cpu.l2cache.ReadExReq_misses::total 117117 # number of ReadExReq misses
349system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
350system.cpu.l2cache.demand_misses::cpu.data 1044757 # number of demand (read+write) misses
351system.cpu.l2cache.demand_misses::total 1058163 # number of demand (read+write) misses
352system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
353system.cpu.l2cache.overall_misses::cpu.data 1044757 # number of overall misses
354system.cpu.l2cache.overall_misses::total 1058163 # number of overall misses
355system.cpu.l2cache.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses)
356system.cpu.l2cache.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses)
357system.cpu.l2cache.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses)
358system.cpu.l2cache.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses)
359system.cpu.l2cache.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses)
360system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
361system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
362system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
363system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
364system.cpu.l2cache.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses
365system.cpu.l2cache.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses
366system.cpu.l2cache.demand_accesses::total 2963418 # number of demand (read+write) accesses
367system.cpu.l2cache.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses
368system.cpu.l2cache.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses
369system.cpu.l2cache.overall_accesses::total 2963418 # number of overall (read+write) accesses
370system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses
371system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses
372system.cpu.l2cache.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses
373system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
374system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
375system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses
376system.cpu.l2cache.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses
377system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses
378system.cpu.l2cache.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses
379system.cpu.l2cache.demand_miss_rate::total 0.357075 # miss rate for demand accesses
380system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses
381system.cpu.l2cache.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses
382system.cpu.l2cache.overall_miss_rate::total 0.357075 # miss rate for overall accesses
383system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
384system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
385system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
386system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
387system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
388system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
389system.cpu.l2cache.fast_writes 0 # number of fast writes performed
390system.cpu.l2cache.cache_copies 0 # number of cache copies performed
391system.cpu.l2cache.writebacks::writebacks 74291 # number of writebacks
392system.cpu.l2cache.writebacks::total 74291 # number of writebacks
393system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
394system.cpu.dcache.tags.replacements 2042702 # number of replacements
395system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
396system.cpu.dcache.tags.total_refs 14038431 # Total number of references to valid blocks.
397system.cpu.dcache.tags.sampled_refs 2043214 # Sample count of references to valid blocks.
398system.cpu.dcache.tags.avg_refs 6.870759 # Average number of references to valid blocks.
399system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
400system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
401system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
402system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
403system.cpu.dcache.ReadReq_hits::cpu.data 7807780 # number of ReadReq hits
404system.cpu.dcache.ReadReq_hits::total 7807780 # number of ReadReq hits
405system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits
406system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits
407system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
408system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
409system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
410system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
411system.cpu.dcache.demand_hits::cpu.data 13655992 # number of demand (read+write) hits
412system.cpu.dcache.demand_hits::total 13655992 # number of demand (read+write) hits
413system.cpu.dcache.overall_hits::cpu.data 13655992 # number of overall hits
414system.cpu.dcache.overall_hits::total 13655992 # number of overall hits
415system.cpu.dcache.ReadReq_misses::cpu.data 1721707 # number of ReadReq misses
416system.cpu.dcache.ReadReq_misses::total 1721707 # number of ReadReq misses
417system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
418system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
419system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
420system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
421system.cpu.dcache.demand_misses::cpu.data 2026069 # number of demand (read+write) misses
422system.cpu.dcache.demand_misses::total 2026069 # number of demand (read+write) misses
423system.cpu.dcache.overall_misses::cpu.data 2026069 # number of overall misses
424system.cpu.dcache.overall_misses::total 2026069 # number of overall misses
425system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses)
426system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
427system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
428system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
429system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
430system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
431system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
432system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
433system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses
434system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses
435system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses
436system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses
437system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
438system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
439system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
440system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
441system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
442system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
443system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
444system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
445system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
446system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
447system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
448system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
449system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
450system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
451system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
452system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
453system.cpu.dcache.fast_writes 0 # number of fast writes performed
454system.cpu.dcache.cache_copies 0 # number of cache copies performed
455system.cpu.dcache.writebacks::writebacks 833491 # number of writebacks
456system.cpu.dcache.writebacks::total 833491 # number of writebacks
457system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
458system.cpu.toL2Bus.throughput 132867917 # Throughput (bytes/s)
459system.cpu.toL2Bus.data_through_bus 243049454 # Total data (bytes)
460system.cpu.toL2Bus.snoop_data_through_bus 10112 # Total snoop data (bytes)
461
462---------- End Simulation Statistics ----------
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