1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.829332 # Number of seconds simulated
4sim_ticks 1829331993500 # Number of ticks simulated
5final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.829332 # Number of seconds simulated
4sim_ticks 1829331993500 # Number of ticks simulated
5final_tick 1829331993500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 1838030 # Simulator instruction rate (inst/s)
8host_op_rate 1838029 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 56003449171 # Simulator tick rate (ticks/s)
10host_mem_usage 325188 # Number of bytes of host memory used
11host_seconds 32.66 # Real time elapsed on the host
| 7host_inst_rate 2717372 # Simulator instruction rate (inst/s)
8host_op_rate 2717371 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 82796436895 # Simulator tick rate (ticks/s)
10host_mem_usage 372644 # Number of bytes of host memory used
11host_seconds 22.09 # Real time elapsed on the host
|
12sim_insts 60038469 # Number of instructions simulated
13sim_ops 60038469 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
| 12sim_insts 60038469 # Number of instructions simulated
13sim_ops 60038469 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
|
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
16system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::total 67686528 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory
23system.physmem.bytes_written::total 7415744 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory
26system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 36535234 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 36535234 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s)
| 17system.physmem.bytes_read::cpu.inst 850496 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 66835072 # Number of bytes read from this memory
19system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
20system.physmem.bytes_read::total 67686528 # Number of bytes read from this memory
21system.physmem.bytes_inst_read::cpu.inst 850496 # Number of instructions bytes read from this memory
22system.physmem.bytes_inst_read::total 850496 # Number of instructions bytes read from this memory
23system.physmem.bytes_written::writebacks 7415744 # Number of bytes written to this memory
24system.physmem.bytes_written::total 7415744 # Number of bytes written to this memory
25system.physmem.num_reads::cpu.inst 13289 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 1044298 # Number of read requests responded to by this memory
27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
28system.physmem.num_reads::total 1057602 # Number of read requests responded to by this memory
29system.physmem.num_writes::writebacks 115871 # Number of write requests responded to by this memory
30system.physmem.num_writes::total 115871 # Number of write requests responded to by this memory
31system.physmem.bw_read::cpu.inst 464922 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.data 36535234 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::total 37000680 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::cpu.inst 464922 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::total 464922 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_write::writebacks 4053799 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_write::total 4053799 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_total::writebacks 4053799 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.inst 464922 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.data 36535234 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::tsunami.ide 525 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::total 41054479 # Total bandwidth to/from this memory (bytes/s)
|
| 44system.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
45system.bridge.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
43system.cpu_clk_domain.clock 500 # Clock period in ticks
44system.cpu.dtb.fetch_hits 0 # ITB hits
45system.cpu.dtb.fetch_misses 0 # ITB misses
46system.cpu.dtb.fetch_acv 0 # ITB acv
47system.cpu.dtb.fetch_accesses 0 # ITB accesses
48system.cpu.dtb.read_hits 9710423 # DTB read hits
49system.cpu.dtb.read_misses 10329 # DTB read misses
50system.cpu.dtb.read_acv 210 # DTB read access violations
51system.cpu.dtb.read_accesses 728856 # DTB read accesses
52system.cpu.dtb.write_hits 6352496 # DTB write hits
53system.cpu.dtb.write_misses 1142 # DTB write misses
54system.cpu.dtb.write_acv 157 # DTB write access violations
55system.cpu.dtb.write_accesses 291931 # DTB write accesses
56system.cpu.dtb.data_hits 16062919 # DTB hits
57system.cpu.dtb.data_misses 11471 # DTB misses
58system.cpu.dtb.data_acv 367 # DTB access violations
59system.cpu.dtb.data_accesses 1020787 # DTB accesses
60system.cpu.itb.fetch_hits 4974637 # ITB hits
61system.cpu.itb.fetch_misses 5006 # ITB misses
62system.cpu.itb.fetch_acv 184 # ITB acv
63system.cpu.itb.fetch_accesses 4979643 # ITB accesses
64system.cpu.itb.read_hits 0 # DTB read hits
65system.cpu.itb.read_misses 0 # DTB read misses
66system.cpu.itb.read_acv 0 # DTB read access violations
67system.cpu.itb.read_accesses 0 # DTB read accesses
68system.cpu.itb.write_hits 0 # DTB write hits
69system.cpu.itb.write_misses 0 # DTB write misses
70system.cpu.itb.write_acv 0 # DTB write access violations
71system.cpu.itb.write_accesses 0 # DTB write accesses
72system.cpu.itb.data_hits 0 # DTB hits
73system.cpu.itb.data_misses 0 # DTB misses
74system.cpu.itb.data_acv 0 # DTB access violations
75system.cpu.itb.data_accesses 0 # DTB accesses
| 46system.cpu_clk_domain.clock 500 # Clock period in ticks
47system.cpu.dtb.fetch_hits 0 # ITB hits
48system.cpu.dtb.fetch_misses 0 # ITB misses
49system.cpu.dtb.fetch_acv 0 # ITB acv
50system.cpu.dtb.fetch_accesses 0 # ITB accesses
51system.cpu.dtb.read_hits 9710423 # DTB read hits
52system.cpu.dtb.read_misses 10329 # DTB read misses
53system.cpu.dtb.read_acv 210 # DTB read access violations
54system.cpu.dtb.read_accesses 728856 # DTB read accesses
55system.cpu.dtb.write_hits 6352496 # DTB write hits
56system.cpu.dtb.write_misses 1142 # DTB write misses
57system.cpu.dtb.write_acv 157 # DTB write access violations
58system.cpu.dtb.write_accesses 291931 # DTB write accesses
59system.cpu.dtb.data_hits 16062919 # DTB hits
60system.cpu.dtb.data_misses 11471 # DTB misses
61system.cpu.dtb.data_acv 367 # DTB access violations
62system.cpu.dtb.data_accesses 1020787 # DTB accesses
63system.cpu.itb.fetch_hits 4974637 # ITB hits
64system.cpu.itb.fetch_misses 5006 # ITB misses
65system.cpu.itb.fetch_acv 184 # ITB acv
66system.cpu.itb.fetch_accesses 4979643 # ITB accesses
67system.cpu.itb.read_hits 0 # DTB read hits
68system.cpu.itb.read_misses 0 # DTB read misses
69system.cpu.itb.read_acv 0 # DTB read access violations
70system.cpu.itb.read_accesses 0 # DTB read accesses
71system.cpu.itb.write_hits 0 # DTB write hits
72system.cpu.itb.write_misses 0 # DTB write misses
73system.cpu.itb.write_acv 0 # DTB write access violations
74system.cpu.itb.write_accesses 0 # DTB write accesses
75system.cpu.itb.data_hits 0 # DTB hits
76system.cpu.itb.data_misses 0 # DTB misses
77system.cpu.itb.data_acv 0 # DTB access violations
78system.cpu.itb.data_accesses 0 # DTB accesses
|
| 79system.cpu.numPwrStateTransitions 12714 # Number of power state transitions
80system.cpu.pwrStateClkGateDist::samples 6357 # Distribution of time spent in the clock gated state
81system.cpu.pwrStateClkGateDist::mean 283043475.573698 # Distribution of time spent in the clock gated state
82system.cpu.pwrStateClkGateDist::stdev 441371914.604153 # Distribution of time spent in the clock gated state
83system.cpu.pwrStateClkGateDist::1000-5e+10 6357 100.00% 100.00% # Distribution of time spent in the clock gated state
84system.cpu.pwrStateClkGateDist::min_value 386000 # Distribution of time spent in the clock gated state
85system.cpu.pwrStateClkGateDist::max_value 2000000000 # Distribution of time spent in the clock gated state
86system.cpu.pwrStateClkGateDist::total 6357 # Distribution of time spent in the clock gated state
87system.cpu.pwrStateResidencyTicks::ON 30024619278 # Cumulative time (in ticks) in various power states
88system.cpu.pwrStateResidencyTicks::CLK_GATED 1799307374222 # Cumulative time (in ticks) in various power states
|
76system.cpu.numCycles 3658670345 # number of cpu cycles simulated
77system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
78system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
79system.cpu.kern.inst.arm 0 # number of arm instructions executed
80system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
81system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
82system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
83system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
84system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
85system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl
86system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl
87system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
88system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
89system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
90system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
91system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
92system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl
93system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
94system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
95system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl
96system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl
97system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
98system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
99system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
100system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl
101system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl
102system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
103system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
104system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
105system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
106system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
107system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
108system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
109system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
110system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
111system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
112system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
113system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
114system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
115system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
116system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
117system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
118system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
119system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
120system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
121system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
122system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
123system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
124system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
125system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
126system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
127system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
128system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
129system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
130system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
131system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
132system.cpu.kern.syscall::total 326 # number of syscalls executed
133system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
134system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
135system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
136system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
137system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
138system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
139system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
140system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed
141system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
142system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
143system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
144system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
145system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
146system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
147system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
148system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
149system.cpu.kern.callpal::total 192179 # number of callpals executed
150system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
151system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
152system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
153system.cpu.kern.mode_good::kernel 1908
154system.cpu.kern.mode_good::user 1737
155system.cpu.kern.mode_good::idle 171
156system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches
157system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
158system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
159system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
160system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode
161system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
162system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode
163system.cpu.kern.swap_context 4178 # number of times the context was actually changed
164system.cpu.committedInsts 60038469 # Number of instructions committed
165system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed
166system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses
167system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
168system.cpu.num_func_calls 1484182 # number of times a function call or return occured
169system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls
170system.cpu.num_int_insts 55913692 # number of integer instructions
171system.cpu.num_fp_insts 324460 # number of float instructions
172system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read
173system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written
174system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
175system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
176system.cpu.num_mem_refs 16115703 # number of memory refs
177system.cpu.num_load_insts 9747509 # Number of load instructions
178system.cpu.num_store_insts 6368194 # Number of store instructions
179system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles
180system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles
181system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
182system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
183system.cpu.Branches 9064428 # Number of branches fetched
184system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction
185system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction
186system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
187system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
188system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
189system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
190system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
191system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
192system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
193system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
194system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
195system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction
196system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction
197system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction
198system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction
199system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction
200system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction
201system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction
202system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction
203system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction
204system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction
205system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction
206system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
207system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
208system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
209system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
210system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
211system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
212system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
213system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
214system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction
215system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
216system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
217system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
218system.cpu.op_class::total 60050307 # Class of executed instruction
| 89system.cpu.numCycles 3658670345 # number of cpu cycles simulated
90system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
91system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
92system.cpu.kern.inst.arm 0 # number of arm instructions executed
93system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
94system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
95system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
96system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
97system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
98system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl
99system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl
100system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
101system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
102system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
103system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
104system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
105system.cpu.kern.ipl_ticks::0 1811929127500 99.05% 99.05% # number of cycles we spent at this ipl
106system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
107system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
108system.cpu.kern.ipl_ticks::31 17302310500 0.95% 100.00% # number of cycles we spent at this ipl
109system.cpu.kern.ipl_ticks::total 1829331786000 # number of cycles we spent at this ipl
110system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
111system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
112system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
113system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl
114system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl
115system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
116system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
117system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
118system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed
119system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed
120system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed
121system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed
122system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed
123system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed
124system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed
125system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed
126system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed
127system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed
128system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed
129system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed
130system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed
131system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed
132system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed
133system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed
134system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed
135system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed
136system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed
137system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed
138system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed
139system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed
140system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed
141system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed
142system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed
143system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed
144system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed
145system.cpu.kern.syscall::total 326 # number of syscalls executed
146system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed
147system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed
148system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed
149system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed
150system.cpu.kern.callpal::swpctx 4177 2.17% 2.18% # number of callpals executed
151system.cpu.kern.callpal::tbi 54 0.03% 2.20% # number of callpals executed
152system.cpu.kern.callpal::wrent 7 0.00% 2.21% # number of callpals executed
153system.cpu.kern.callpal::swpipl 175248 91.19% 93.40% # number of callpals executed
154system.cpu.kern.callpal::rdps 6771 3.52% 96.92% # number of callpals executed
155system.cpu.kern.callpal::wrkgp 1 0.00% 96.92% # number of callpals executed
156system.cpu.kern.callpal::wrusp 7 0.00% 96.92% # number of callpals executed
157system.cpu.kern.callpal::rdusp 9 0.00% 96.93% # number of callpals executed
158system.cpu.kern.callpal::whami 2 0.00% 96.93% # number of callpals executed
159system.cpu.kern.callpal::rti 5203 2.71% 99.64% # number of callpals executed
160system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed
161system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed
162system.cpu.kern.callpal::total 192179 # number of callpals executed
163system.cpu.kern.mode_switch::kernel 5949 # number of protection mode switches
164system.cpu.kern.mode_switch::user 1737 # number of protection mode switches
165system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
166system.cpu.kern.mode_good::kernel 1908
167system.cpu.kern.mode_good::user 1737
168system.cpu.kern.mode_good::idle 171
169system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches
170system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
171system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
172system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
173system.cpu.kern.mode_ticks::kernel 26833316500 1.47% 1.47% # number of ticks spent at the given mode
174system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
175system.cpu.kern.mode_ticks::idle 1801033399500 98.45% 100.00% # number of ticks spent at the given mode
176system.cpu.kern.swap_context 4178 # number of times the context was actually changed
177system.cpu.committedInsts 60038469 # Number of instructions committed
178system.cpu.committedOps 60038469 # Number of ops (including micro ops) committed
179system.cpu.num_int_alu_accesses 55913692 # Number of integer alu accesses
180system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
181system.cpu.num_func_calls 1484182 # number of times a function call or return occured
182system.cpu.num_conditional_control_insts 7110791 # number of instructions that are conditional controls
183system.cpu.num_int_insts 55913692 # number of integer instructions
184system.cpu.num_fp_insts 324460 # number of float instructions
185system.cpu.num_int_register_reads 76954245 # number of times the integer registers were read
186system.cpu.num_int_register_writes 41740352 # number of times the integer registers were written
187system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
188system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
189system.cpu.num_mem_refs 16115703 # number of memory refs
190system.cpu.num_load_insts 9747509 # Number of load instructions
191system.cpu.num_store_insts 6368194 # Number of store instructions
192system.cpu.num_idle_cycles 3598621002.088897 # Number of idle cycles
193system.cpu.num_busy_cycles 60049342.911103 # Number of busy cycles
194system.cpu.not_idle_fraction 0.016413 # Percentage of non-idle cycles
195system.cpu.idle_fraction 0.983587 # Percentage of idle cycles
196system.cpu.Branches 9064428 # Number of branches fetched
197system.cpu.op_class::No_OpClass 3199100 5.33% 5.33% # Class of executed instruction
198system.cpu.op_class::IntAlu 39448406 65.69% 71.02% # Class of executed instruction
199system.cpu.op_class::IntMult 60677 0.10% 71.12% # Class of executed instruction
200system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
201system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
202system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
203system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
204system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
205system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
206system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
207system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
208system.cpu.op_class::SimdAddAcc 0 0.00% 71.19% # Class of executed instruction
209system.cpu.op_class::SimdAlu 0 0.00% 71.19% # Class of executed instruction
210system.cpu.op_class::SimdCmp 0 0.00% 71.19% # Class of executed instruction
211system.cpu.op_class::SimdCvt 0 0.00% 71.19% # Class of executed instruction
212system.cpu.op_class::SimdMisc 0 0.00% 71.19% # Class of executed instruction
213system.cpu.op_class::SimdMult 0 0.00% 71.19% # Class of executed instruction
214system.cpu.op_class::SimdMultAcc 0 0.00% 71.19% # Class of executed instruction
215system.cpu.op_class::SimdShift 0 0.00% 71.19% # Class of executed instruction
216system.cpu.op_class::SimdShiftAcc 0 0.00% 71.19% # Class of executed instruction
217system.cpu.op_class::SimdSqrt 0 0.00% 71.19% # Class of executed instruction
218system.cpu.op_class::SimdFloatAdd 0 0.00% 71.19% # Class of executed instruction
219system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
220system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
221system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
222system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
223system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
224system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
225system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
226system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
227system.cpu.op_class::MemRead 9975077 16.61% 87.80% # Class of executed instruction
228system.cpu.op_class::MemWrite 6374115 10.61% 98.42% # Class of executed instruction
229system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
230system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
231system.cpu.op_class::total 60050307 # Class of executed instruction
|
| 232system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
219system.cpu.dcache.tags.replacements 2042707 # number of replacements
220system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
221system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks.
222system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks.
223system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks.
224system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
225system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
226system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
227system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
228system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
230system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
231system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
232system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
233system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses
234system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses
| 233system.cpu.dcache.tags.replacements 2042707 # number of replacements
234system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
235system.cpu.dcache.tags.total_refs 14038420 # Total number of references to valid blocks.
236system.cpu.dcache.tags.sampled_refs 2043219 # Sample count of references to valid blocks.
237system.cpu.dcache.tags.avg_refs 6.870737 # Average number of references to valid blocks.
238system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
239system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
240system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
241system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
242system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
243system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
244system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
245system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
246system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
247system.cpu.dcache.tags.tag_accesses 66369780 # Number of tag accesses
248system.cpu.dcache.tags.data_accesses 66369780 # Number of data accesses
|
| 249system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
235system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits
236system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits
237system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits
238system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits
239system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
240system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
241system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
242system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
243system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits
244system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits
245system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits
246system.cpu.dcache.overall_hits::total 13655981 # number of overall hits
247system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses
248system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses
249system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
250system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
251system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
252system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
253system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
254system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
255system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
256system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
257system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses)
258system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses)
259system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses)
260system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses)
261system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
262system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
263system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
264system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
265system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses
266system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses
267system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses
268system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses
269system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
270system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
271system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
272system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
273system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
274system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
275system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
276system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
277system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
278system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
279system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
280system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
281system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
282system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
283system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
284system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
285system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks
286system.cpu.dcache.writebacks::total 833475 # number of writebacks
| 250system.cpu.dcache.ReadReq_hits::cpu.data 7807771 # number of ReadReq hits
251system.cpu.dcache.ReadReq_hits::total 7807771 # number of ReadReq hits
252system.cpu.dcache.WriteReq_hits::cpu.data 5848210 # number of WriteReq hits
253system.cpu.dcache.WriteReq_hits::total 5848210 # number of WriteReq hits
254system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
255system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
256system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
257system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
258system.cpu.dcache.demand_hits::cpu.data 13655981 # number of demand (read+write) hits
259system.cpu.dcache.demand_hits::total 13655981 # number of demand (read+write) hits
260system.cpu.dcache.overall_hits::cpu.data 13655981 # number of overall hits
261system.cpu.dcache.overall_hits::total 13655981 # number of overall hits
262system.cpu.dcache.ReadReq_misses::cpu.data 1721712 # number of ReadReq misses
263system.cpu.dcache.ReadReq_misses::total 1721712 # number of ReadReq misses
264system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
265system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
266system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
267system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
268system.cpu.dcache.demand_misses::cpu.data 2026074 # number of demand (read+write) misses
269system.cpu.dcache.demand_misses::total 2026074 # number of demand (read+write) misses
270system.cpu.dcache.overall_misses::cpu.data 2026074 # number of overall misses
271system.cpu.dcache.overall_misses::total 2026074 # number of overall misses
272system.cpu.dcache.ReadReq_accesses::cpu.data 9529483 # number of ReadReq accesses(hits+misses)
273system.cpu.dcache.ReadReq_accesses::total 9529483 # number of ReadReq accesses(hits+misses)
274system.cpu.dcache.WriteReq_accesses::cpu.data 6152572 # number of WriteReq accesses(hits+misses)
275system.cpu.dcache.WriteReq_accesses::total 6152572 # number of WriteReq accesses(hits+misses)
276system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
277system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
278system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
279system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
280system.cpu.dcache.demand_accesses::cpu.data 15682055 # number of demand (read+write) accesses
281system.cpu.dcache.demand_accesses::total 15682055 # number of demand (read+write) accesses
282system.cpu.dcache.overall_accesses::cpu.data 15682055 # number of overall (read+write) accesses
283system.cpu.dcache.overall_accesses::total 15682055 # number of overall (read+write) accesses
284system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180672 # miss rate for ReadReq accesses
285system.cpu.dcache.ReadReq_miss_rate::total 0.180672 # miss rate for ReadReq accesses
286system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
287system.cpu.dcache.WriteReq_miss_rate::total 0.049469 # miss rate for WriteReq accesses
288system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
289system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085680 # miss rate for LoadLockedReq accesses
290system.cpu.dcache.demand_miss_rate::cpu.data 0.129197 # miss rate for demand accesses
291system.cpu.dcache.demand_miss_rate::total 0.129197 # miss rate for demand accesses
292system.cpu.dcache.overall_miss_rate::cpu.data 0.129197 # miss rate for overall accesses
293system.cpu.dcache.overall_miss_rate::total 0.129197 # miss rate for overall accesses
294system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
295system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
296system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
297system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
298system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
299system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
300system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks
301system.cpu.dcache.writebacks::total 833475 # number of writebacks
|
| 302system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
287system.cpu.icache.tags.replacements 919603 # number of replacements
288system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use
289system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks.
290system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks.
291system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks.
292system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit.
293system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor
294system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
295system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
296system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
297system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
298system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
299system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
300system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
301system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses
302system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses
| 303system.cpu.icache.tags.replacements 919603 # number of replacements
304system.cpu.icache.tags.tagsinuse 511.215257 # Cycle average of tags in use
305system.cpu.icache.tags.total_refs 59130077 # Total number of references to valid blocks.
306system.cpu.icache.tags.sampled_refs 920115 # Sample count of references to valid blocks.
307system.cpu.icache.tags.avg_refs 64.263790 # Average number of references to valid blocks.
308system.cpu.icache.tags.warmup_cycle 9686452000 # Cycle when the warmup percentage was hit.
309system.cpu.icache.tags.occ_blocks::cpu.inst 511.215257 # Average occupied blocks per requestor
310system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
311system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
312system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
313system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
314system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
315system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
316system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
317system.cpu.icache.tags.tag_accesses 60970537 # Number of tag accesses
318system.cpu.icache.tags.data_accesses 60970537 # Number of data accesses
|
| 319system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
303system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits
304system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits
305system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits
306system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits
307system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits
308system.cpu.icache.overall_hits::total 59130077 # number of overall hits
309system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses
310system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses
311system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses
312system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses
313system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses
314system.cpu.icache.overall_misses::total 920230 # number of overall misses
315system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses)
316system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses)
317system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses
318system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses
319system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses
320system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses
321system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
322system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
323system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
324system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
325system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
326system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
327system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
328system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
329system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
330system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
331system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
332system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
333system.cpu.icache.writebacks::writebacks 919603 # number of writebacks
334system.cpu.icache.writebacks::total 919603 # number of writebacks
| 320system.cpu.icache.ReadReq_hits::cpu.inst 59130077 # number of ReadReq hits
321system.cpu.icache.ReadReq_hits::total 59130077 # number of ReadReq hits
322system.cpu.icache.demand_hits::cpu.inst 59130077 # number of demand (read+write) hits
323system.cpu.icache.demand_hits::total 59130077 # number of demand (read+write) hits
324system.cpu.icache.overall_hits::cpu.inst 59130077 # number of overall hits
325system.cpu.icache.overall_hits::total 59130077 # number of overall hits
326system.cpu.icache.ReadReq_misses::cpu.inst 920230 # number of ReadReq misses
327system.cpu.icache.ReadReq_misses::total 920230 # number of ReadReq misses
328system.cpu.icache.demand_misses::cpu.inst 920230 # number of demand (read+write) misses
329system.cpu.icache.demand_misses::total 920230 # number of demand (read+write) misses
330system.cpu.icache.overall_misses::cpu.inst 920230 # number of overall misses
331system.cpu.icache.overall_misses::total 920230 # number of overall misses
332system.cpu.icache.ReadReq_accesses::cpu.inst 60050307 # number of ReadReq accesses(hits+misses)
333system.cpu.icache.ReadReq_accesses::total 60050307 # number of ReadReq accesses(hits+misses)
334system.cpu.icache.demand_accesses::cpu.inst 60050307 # number of demand (read+write) accesses
335system.cpu.icache.demand_accesses::total 60050307 # number of demand (read+write) accesses
336system.cpu.icache.overall_accesses::cpu.inst 60050307 # number of overall (read+write) accesses
337system.cpu.icache.overall_accesses::total 60050307 # number of overall (read+write) accesses
338system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
339system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
340system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
341system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
342system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
343system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
344system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
345system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
346system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
347system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
348system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
349system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
350system.cpu.icache.writebacks::writebacks 919603 # number of writebacks
351system.cpu.icache.writebacks::total 919603 # number of writebacks
|
| 352system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
335system.cpu.l2cache.tags.replacements 992419 # number of replacements
336system.cpu.l2cache.tags.tagsinuse 65424.374401 # Cycle average of tags in use
337system.cpu.l2cache.tags.total_refs 4560132 # Total number of references to valid blocks.
338system.cpu.l2cache.tags.sampled_refs 1057582 # Sample count of references to valid blocks.
339system.cpu.l2cache.tags.avg_refs 4.311847 # Average number of references to valid blocks.
340system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
341system.cpu.l2cache.tags.occ_blocks::writebacks 56331.541205 # Average occupied blocks per requestor
342system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.327000 # Average occupied blocks per requestor
343system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.506195 # Average occupied blocks per requestor
344system.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy
345system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy
346system.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy
347system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
348system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
349system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
350system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id
351system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id
352system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3046 # Occupied blocks per task id
353system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54052 # Occupied blocks per task id
354system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
355system.cpu.l2cache.tags.tag_accesses 48753652 # Number of tag accesses
356system.cpu.l2cache.tags.data_accesses 48753652 # Number of data accesses
| 353system.cpu.l2cache.tags.replacements 992419 # number of replacements
354system.cpu.l2cache.tags.tagsinuse 65424.374401 # Cycle average of tags in use
355system.cpu.l2cache.tags.total_refs 4560132 # Total number of references to valid blocks.
356system.cpu.l2cache.tags.sampled_refs 1057582 # Sample count of references to valid blocks.
357system.cpu.l2cache.tags.avg_refs 4.311847 # Average number of references to valid blocks.
358system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
359system.cpu.l2cache.tags.occ_blocks::writebacks 56331.541205 # Average occupied blocks per requestor
360system.cpu.l2cache.tags.occ_blocks::cpu.inst 4843.327000 # Average occupied blocks per requestor
361system.cpu.l2cache.tags.occ_blocks::cpu.data 4249.506195 # Average occupied blocks per requestor
362system.cpu.l2cache.tags.occ_percent::writebacks 0.859551 # Average percentage of cache occupancy
363system.cpu.l2cache.tags.occ_percent::cpu.inst 0.073903 # Average percentage of cache occupancy
364system.cpu.l2cache.tags.occ_percent::cpu.data 0.064842 # Average percentage of cache occupancy
365system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
366system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
367system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
368system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id
369system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id
370system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3046 # Occupied blocks per task id
371system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54052 # Occupied blocks per task id
372system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
373system.cpu.l2cache.tags.tag_accesses 48753652 # Number of tag accesses
374system.cpu.l2cache.tags.data_accesses 48753652 # Number of data accesses
|
| 375system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
357system.cpu.l2cache.WritebackDirty_hits::writebacks 833475 # number of WritebackDirty hits
358system.cpu.l2cache.WritebackDirty_hits::total 833475 # number of WritebackDirty hits
359system.cpu.l2cache.WritebackClean_hits::writebacks 919351 # number of WritebackClean hits
360system.cpu.l2cache.WritebackClean_hits::total 919351 # number of WritebackClean hits
361system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
362system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
363system.cpu.l2cache.ReadExReq_hits::cpu.data 187286 # number of ReadExReq hits
364system.cpu.l2cache.ReadExReq_hits::total 187286 # number of ReadExReq hits
365system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906923 # number of ReadCleanReq hits
366system.cpu.l2cache.ReadCleanReq_hits::total 906923 # number of ReadCleanReq hits
367system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits
368system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits
369system.cpu.l2cache.demand_hits::cpu.inst 906923 # number of demand (read+write) hits
370system.cpu.l2cache.demand_hits::cpu.data 998516 # number of demand (read+write) hits
371system.cpu.l2cache.demand_hits::total 1905439 # number of demand (read+write) hits
372system.cpu.l2cache.overall_hits::cpu.inst 906923 # number of overall hits
373system.cpu.l2cache.overall_hits::cpu.data 998516 # number of overall hits
374system.cpu.l2cache.overall_hits::total 1905439 # number of overall hits
375system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
376system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
377system.cpu.l2cache.ReadExReq_misses::cpu.data 117060 # number of ReadExReq misses
378system.cpu.l2cache.ReadExReq_misses::total 117060 # number of ReadExReq misses
379system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses
380system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses
381system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses
382system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses
383system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses
384system.cpu.l2cache.demand_misses::cpu.data 1044704 # number of demand (read+write) misses
385system.cpu.l2cache.demand_misses::total 1057993 # number of demand (read+write) misses
386system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses
387system.cpu.l2cache.overall_misses::cpu.data 1044704 # number of overall misses
388system.cpu.l2cache.overall_misses::total 1057993 # number of overall misses
389system.cpu.l2cache.WritebackDirty_accesses::writebacks 833475 # number of WritebackDirty accesses(hits+misses)
390system.cpu.l2cache.WritebackDirty_accesses::total 833475 # number of WritebackDirty accesses(hits+misses)
391system.cpu.l2cache.WritebackClean_accesses::writebacks 919351 # number of WritebackClean accesses(hits+misses)
392system.cpu.l2cache.WritebackClean_accesses::total 919351 # number of WritebackClean accesses(hits+misses)
393system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
394system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
395system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
396system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
397system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920212 # number of ReadCleanReq accesses(hits+misses)
398system.cpu.l2cache.ReadCleanReq_accesses::total 920212 # number of ReadCleanReq accesses(hits+misses)
399system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses)
400system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses)
401system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses
402system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses
403system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses
404system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses
405system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses
406system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses
407system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
408system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
409system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384628 # miss rate for ReadExReq accesses
410system.cpu.l2cache.ReadExReq_miss_rate::total 0.384628 # miss rate for ReadExReq accesses
411system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses
412system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses
413system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses
414system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses
415system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses
416system.cpu.l2cache.demand_miss_rate::cpu.data 0.511303 # miss rate for demand accesses
417system.cpu.l2cache.demand_miss_rate::total 0.357016 # miss rate for demand accesses
418system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses
419system.cpu.l2cache.overall_miss_rate::cpu.data 0.511303 # miss rate for overall accesses
420system.cpu.l2cache.overall_miss_rate::total 0.357016 # miss rate for overall accesses
421system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
422system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
423system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
424system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
425system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
426system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
427system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks
428system.cpu.l2cache.writebacks::total 74359 # number of writebacks
429system.cpu.toL2Bus.snoop_filter.tot_requests 5925776 # Total number of requests made to the snoop filter.
430system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962432 # Number of requests hitting in the snoop filter with a single holder of the requested data.
431system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
432system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter.
433system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
434system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
| 376system.cpu.l2cache.WritebackDirty_hits::writebacks 833475 # number of WritebackDirty hits
377system.cpu.l2cache.WritebackDirty_hits::total 833475 # number of WritebackDirty hits
378system.cpu.l2cache.WritebackClean_hits::writebacks 919351 # number of WritebackClean hits
379system.cpu.l2cache.WritebackClean_hits::total 919351 # number of WritebackClean hits
380system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
381system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
382system.cpu.l2cache.ReadExReq_hits::cpu.data 187286 # number of ReadExReq hits
383system.cpu.l2cache.ReadExReq_hits::total 187286 # number of ReadExReq hits
384system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 906923 # number of ReadCleanReq hits
385system.cpu.l2cache.ReadCleanReq_hits::total 906923 # number of ReadCleanReq hits
386system.cpu.l2cache.ReadSharedReq_hits::cpu.data 811230 # number of ReadSharedReq hits
387system.cpu.l2cache.ReadSharedReq_hits::total 811230 # number of ReadSharedReq hits
388system.cpu.l2cache.demand_hits::cpu.inst 906923 # number of demand (read+write) hits
389system.cpu.l2cache.demand_hits::cpu.data 998516 # number of demand (read+write) hits
390system.cpu.l2cache.demand_hits::total 1905439 # number of demand (read+write) hits
391system.cpu.l2cache.overall_hits::cpu.inst 906923 # number of overall hits
392system.cpu.l2cache.overall_hits::cpu.data 998516 # number of overall hits
393system.cpu.l2cache.overall_hits::total 1905439 # number of overall hits
394system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
395system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
396system.cpu.l2cache.ReadExReq_misses::cpu.data 117060 # number of ReadExReq misses
397system.cpu.l2cache.ReadExReq_misses::total 117060 # number of ReadExReq misses
398system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 13289 # number of ReadCleanReq misses
399system.cpu.l2cache.ReadCleanReq_misses::total 13289 # number of ReadCleanReq misses
400system.cpu.l2cache.ReadSharedReq_misses::cpu.data 927644 # number of ReadSharedReq misses
401system.cpu.l2cache.ReadSharedReq_misses::total 927644 # number of ReadSharedReq misses
402system.cpu.l2cache.demand_misses::cpu.inst 13289 # number of demand (read+write) misses
403system.cpu.l2cache.demand_misses::cpu.data 1044704 # number of demand (read+write) misses
404system.cpu.l2cache.demand_misses::total 1057993 # number of demand (read+write) misses
405system.cpu.l2cache.overall_misses::cpu.inst 13289 # number of overall misses
406system.cpu.l2cache.overall_misses::cpu.data 1044704 # number of overall misses
407system.cpu.l2cache.overall_misses::total 1057993 # number of overall misses
408system.cpu.l2cache.WritebackDirty_accesses::writebacks 833475 # number of WritebackDirty accesses(hits+misses)
409system.cpu.l2cache.WritebackDirty_accesses::total 833475 # number of WritebackDirty accesses(hits+misses)
410system.cpu.l2cache.WritebackClean_accesses::writebacks 919351 # number of WritebackClean accesses(hits+misses)
411system.cpu.l2cache.WritebackClean_accesses::total 919351 # number of WritebackClean accesses(hits+misses)
412system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
413system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
414system.cpu.l2cache.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses)
415system.cpu.l2cache.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses)
416system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 920212 # number of ReadCleanReq accesses(hits+misses)
417system.cpu.l2cache.ReadCleanReq_accesses::total 920212 # number of ReadCleanReq accesses(hits+misses)
418system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 1738874 # number of ReadSharedReq accesses(hits+misses)
419system.cpu.l2cache.ReadSharedReq_accesses::total 1738874 # number of ReadSharedReq accesses(hits+misses)
420system.cpu.l2cache.demand_accesses::cpu.inst 920212 # number of demand (read+write) accesses
421system.cpu.l2cache.demand_accesses::cpu.data 2043220 # number of demand (read+write) accesses
422system.cpu.l2cache.demand_accesses::total 2963432 # number of demand (read+write) accesses
423system.cpu.l2cache.overall_accesses::cpu.inst 920212 # number of overall (read+write) accesses
424system.cpu.l2cache.overall_accesses::cpu.data 2043220 # number of overall (read+write) accesses
425system.cpu.l2cache.overall_accesses::total 2963432 # number of overall (read+write) accesses
426system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
427system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
428system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384628 # miss rate for ReadExReq accesses
429system.cpu.l2cache.ReadExReq_miss_rate::total 0.384628 # miss rate for ReadExReq accesses
430system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.014441 # miss rate for ReadCleanReq accesses
431system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.014441 # miss rate for ReadCleanReq accesses
432system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.533474 # miss rate for ReadSharedReq accesses
433system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.533474 # miss rate for ReadSharedReq accesses
434system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014441 # miss rate for demand accesses
435system.cpu.l2cache.demand_miss_rate::cpu.data 0.511303 # miss rate for demand accesses
436system.cpu.l2cache.demand_miss_rate::total 0.357016 # miss rate for demand accesses
437system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014441 # miss rate for overall accesses
438system.cpu.l2cache.overall_miss_rate::cpu.data 0.511303 # miss rate for overall accesses
439system.cpu.l2cache.overall_miss_rate::total 0.357016 # miss rate for overall accesses
440system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
441system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
442system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
443system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
444system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
445system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
446system.cpu.l2cache.writebacks::writebacks 74359 # number of writebacks
447system.cpu.l2cache.writebacks::total 74359 # number of writebacks
448system.cpu.toL2Bus.snoop_filter.tot_requests 5925776 # Total number of requests made to the snoop filter.
449system.cpu.toL2Bus.snoop_filter.hit_single_requests 2962432 # Number of requests hitting in the snoop filter with a single holder of the requested data.
450system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1834 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
451system.cpu.toL2Bus.snoop_filter.tot_snoops 1449 # Total number of snoops made to the snoop filter.
452system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1449 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
453system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
| 454system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
435system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution
436system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution
437system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
438system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
439system.cpu.toL2Bus.trans_dist::WritebackDirty 833475 # Transaction distribution
440system.cpu.toL2Bus.trans_dist::WritebackClean 919603 # Transaction distribution
441system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution
442system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
443system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
444system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution
445system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution
446system.cpu.toL2Bus.trans_dist::ReadCleanReq 920230 # Transaction distribution
447system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution
448system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760063 # Packet count per connected master and slave (bytes)
449system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163223 # Packet count per connected master and slave (bytes)
450system.cpu.toL2Bus.pkt_count::total 8923286 # Packet count per connected master and slave (bytes)
451system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749312 # Cumulative packet size per connected master and slave (bytes)
452system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154606 # Cumulative packet size per connected master and slave (bytes)
453system.cpu.toL2Bus.pkt_size::total 301903918 # Cumulative packet size per connected master and slave (bytes)
454system.cpu.toL2Bus.snoops 1075988 # Total snoops (count)
455system.cpu.toL2Bus.snoop_fanout::samples 7018629 # Request fanout histogram
456system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram
457system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram
458system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
459system.cpu.toL2Bus.snoop_fanout::0 7013406 99.93% 99.93% # Request fanout histogram
460system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram
461system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
462system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
463system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
464system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
465system.cpu.toL2Bus.snoop_fanout::total 7018629 # Request fanout histogram
466system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
467system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
468system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
469system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
470system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
471system.disk0.dma_write_txs 395 # Number of DMA write transactions.
472system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
473system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
474system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
475system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
476system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
477system.disk2.dma_write_txs 1 # Number of DMA write transactions.
| 455system.cpu.toL2Bus.trans_dist::ReadReq 7184 # Transaction distribution
456system.cpu.toL2Bus.trans_dist::ReadResp 2666288 # Transaction distribution
457system.cpu.toL2Bus.trans_dist::WriteReq 9838 # Transaction distribution
458system.cpu.toL2Bus.trans_dist::WriteResp 9838 # Transaction distribution
459system.cpu.toL2Bus.trans_dist::WritebackDirty 833475 # Transaction distribution
460system.cpu.toL2Bus.trans_dist::WritebackClean 919603 # Transaction distribution
461system.cpu.toL2Bus.trans_dist::CleanEvict 1209232 # Transaction distribution
462system.cpu.toL2Bus.trans_dist::UpgradeReq 16 # Transaction distribution
463system.cpu.toL2Bus.trans_dist::UpgradeResp 16 # Transaction distribution
464system.cpu.toL2Bus.trans_dist::ReadExReq 304346 # Transaction distribution
465system.cpu.toL2Bus.trans_dist::ReadExResp 304346 # Transaction distribution
466system.cpu.toL2Bus.trans_dist::ReadCleanReq 920230 # Transaction distribution
467system.cpu.toL2Bus.trans_dist::ReadSharedReq 1738874 # Transaction distribution
468system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2760063 # Packet count per connected master and slave (bytes)
469system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6163223 # Packet count per connected master and slave (bytes)
470system.cpu.toL2Bus.pkt_count::total 8923286 # Packet count per connected master and slave (bytes)
471system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 117749312 # Cumulative packet size per connected master and slave (bytes)
472system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 184154606 # Cumulative packet size per connected master and slave (bytes)
473system.cpu.toL2Bus.pkt_size::total 301903918 # Cumulative packet size per connected master and slave (bytes)
474system.cpu.toL2Bus.snoops 1075988 # Total snoops (count)
475system.cpu.toL2Bus.snoop_fanout::samples 7018629 # Request fanout histogram
476system.cpu.toL2Bus.snoop_fanout::mean 0.000744 # Request fanout histogram
477system.cpu.toL2Bus.snoop_fanout::stdev 0.027269 # Request fanout histogram
478system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
479system.cpu.toL2Bus.snoop_fanout::0 7013406 99.93% 99.93% # Request fanout histogram
480system.cpu.toL2Bus.snoop_fanout::1 5223 0.07% 100.00% # Request fanout histogram
481system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
482system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
483system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
484system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
485system.cpu.toL2Bus.snoop_fanout::total 7018629 # Request fanout histogram
486system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
487system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
488system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
489system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes.
490system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes.
491system.disk0.dma_write_txs 395 # Number of DMA write transactions.
492system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
493system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
494system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD).
495system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
496system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
497system.disk2.dma_write_txs 1 # Number of DMA write transactions.
|
| 498system.iobus.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
478system.iobus.trans_dist::ReadReq 7358 # Transaction distribution
479system.iobus.trans_dist::ReadResp 7358 # Transaction distribution
480system.iobus.trans_dist::WriteReq 51390 # Transaction distribution
481system.iobus.trans_dist::WriteResp 51390 # Transaction distribution
482system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes)
483system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes)
484system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
485system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
486system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes)
487system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes)
488system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
489system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
490system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
491system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes)
492system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
493system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
494system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes)
495system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes)
496system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes)
497system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
498system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
499system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes)
500system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes)
501system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
502system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
503system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
504system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes)
505system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
506system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
507system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes)
| 499system.iobus.trans_dist::ReadReq 7358 # Transaction distribution
500system.iobus.trans_dist::ReadResp 7358 # Transaction distribution
501system.iobus.trans_dist::WriteReq 51390 # Transaction distribution
502system.iobus.trans_dist::WriteResp 51390 # Transaction distribution
503system.iobus.pkt_count_system.bridge.master::system.tsunami.cchip.pio 5248 # Packet count per connected master and slave (bytes)
504system.iobus.pkt_count_system.bridge.master::system.tsunami.pchip.pio 1010 # Packet count per connected master and slave (bytes)
505system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_sm_chip.pio 10 # Packet count per connected master and slave (bytes)
506system.iobus.pkt_count_system.bridge.master::system.tsunami.fake_uart4.pio 10 # Packet count per connected master and slave (bytes)
507system.iobus.pkt_count_system.bridge.master::system.tsunami.io.pio 1076 # Packet count per connected master and slave (bytes)
508system.iobus.pkt_count_system.bridge.master::system.tsunami.uart.pio 18012 # Packet count per connected master and slave (bytes)
509system.iobus.pkt_count_system.bridge.master::system.tsunami.backdoor.pio 1904 # Packet count per connected master and slave (bytes)
510system.iobus.pkt_count_system.bridge.master::system.tsunami.ide.pio 6672 # Packet count per connected master and slave (bytes)
511system.iobus.pkt_count_system.bridge.master::system.tsunami.ethernet.pio 102 # Packet count per connected master and slave (bytes)
512system.iobus.pkt_count_system.bridge.master::total 34044 # Packet count per connected master and slave (bytes)
513system.iobus.pkt_count_system.tsunami.ide.dma::system.iocache.cpu_side 83452 # Packet count per connected master and slave (bytes)
514system.iobus.pkt_count_system.tsunami.ide.dma::total 83452 # Packet count per connected master and slave (bytes)
515system.iobus.pkt_count::total 117496 # Packet count per connected master and slave (bytes)
516system.iobus.pkt_size_system.bridge.master::system.tsunami.cchip.pio 20992 # Cumulative packet size per connected master and slave (bytes)
517system.iobus.pkt_size_system.bridge.master::system.tsunami.pchip.pio 2733 # Cumulative packet size per connected master and slave (bytes)
518system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_sm_chip.pio 5 # Cumulative packet size per connected master and slave (bytes)
519system.iobus.pkt_size_system.bridge.master::system.tsunami.fake_uart4.pio 5 # Cumulative packet size per connected master and slave (bytes)
520system.iobus.pkt_size_system.bridge.master::system.tsunami.io.pio 1392 # Cumulative packet size per connected master and slave (bytes)
521system.iobus.pkt_size_system.bridge.master::system.tsunami.uart.pio 9006 # Cumulative packet size per connected master and slave (bytes)
522system.iobus.pkt_size_system.bridge.master::system.tsunami.backdoor.pio 7596 # Cumulative packet size per connected master and slave (bytes)
523system.iobus.pkt_size_system.bridge.master::system.tsunami.ide.pio 4193 # Cumulative packet size per connected master and slave (bytes)
524system.iobus.pkt_size_system.bridge.master::system.tsunami.ethernet.pio 204 # Cumulative packet size per connected master and slave (bytes)
525system.iobus.pkt_size_system.bridge.master::total 46126 # Cumulative packet size per connected master and slave (bytes)
526system.iobus.pkt_size_system.tsunami.ide.dma::system.iocache.cpu_side 2661616 # Cumulative packet size per connected master and slave (bytes)
527system.iobus.pkt_size_system.tsunami.ide.dma::total 2661616 # Cumulative packet size per connected master and slave (bytes)
528system.iobus.pkt_size::total 2707742 # Cumulative packet size per connected master and slave (bytes)
|
| 529system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
508system.iocache.tags.replacements 41686 # number of replacements
509system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use
510system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
511system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
512system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
513system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit.
514system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor
515system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
516system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
517system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
518system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
519system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
520system.iocache.tags.tag_accesses 375534 # Number of tag accesses
521system.iocache.tags.data_accesses 375534 # Number of data accesses
| 530system.iocache.tags.replacements 41686 # number of replacements
531system.iocache.tags.tagsinuse 1.225569 # Cycle average of tags in use
532system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
533system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
534system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
535system.iocache.tags.warmup_cycle 1685780587017 # Cycle when the warmup percentage was hit.
536system.iocache.tags.occ_blocks::tsunami.ide 1.225569 # Average occupied blocks per requestor
537system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
538system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
539system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
540system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
541system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
542system.iocache.tags.tag_accesses 375534 # Number of tag accesses
543system.iocache.tags.data_accesses 375534 # Number of data accesses
|
| 544system.iocache.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
522system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
523system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
524system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
525system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
526system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
527system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
528system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
529system.iocache.overall_misses::total 41726 # number of overall misses
530system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
531system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
532system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
533system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
534system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
535system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
536system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
537system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
538system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
539system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
540system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
541system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
542system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
543system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
544system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
545system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
546system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
547system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
548system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
549system.iocache.blocked::no_targets 0 # number of cycles access was blocked
550system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
551system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
552system.iocache.writebacks::writebacks 41512 # number of writebacks
553system.iocache.writebacks::total 41512 # number of writebacks
| 545system.iocache.ReadReq_misses::tsunami.ide 174 # number of ReadReq misses
546system.iocache.ReadReq_misses::total 174 # number of ReadReq misses
547system.iocache.WriteLineReq_misses::tsunami.ide 41552 # number of WriteLineReq misses
548system.iocache.WriteLineReq_misses::total 41552 # number of WriteLineReq misses
549system.iocache.demand_misses::tsunami.ide 41726 # number of demand (read+write) misses
550system.iocache.demand_misses::total 41726 # number of demand (read+write) misses
551system.iocache.overall_misses::tsunami.ide 41726 # number of overall misses
552system.iocache.overall_misses::total 41726 # number of overall misses
553system.iocache.ReadReq_accesses::tsunami.ide 174 # number of ReadReq accesses(hits+misses)
554system.iocache.ReadReq_accesses::total 174 # number of ReadReq accesses(hits+misses)
555system.iocache.WriteLineReq_accesses::tsunami.ide 41552 # number of WriteLineReq accesses(hits+misses)
556system.iocache.WriteLineReq_accesses::total 41552 # number of WriteLineReq accesses(hits+misses)
557system.iocache.demand_accesses::tsunami.ide 41726 # number of demand (read+write) accesses
558system.iocache.demand_accesses::total 41726 # number of demand (read+write) accesses
559system.iocache.overall_accesses::tsunami.ide 41726 # number of overall (read+write) accesses
560system.iocache.overall_accesses::total 41726 # number of overall (read+write) accesses
561system.iocache.ReadReq_miss_rate::tsunami.ide 1 # miss rate for ReadReq accesses
562system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
563system.iocache.WriteLineReq_miss_rate::tsunami.ide 1 # miss rate for WriteLineReq accesses
564system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses
565system.iocache.demand_miss_rate::tsunami.ide 1 # miss rate for demand accesses
566system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
567system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
568system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
569system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
570system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
571system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
572system.iocache.blocked::no_targets 0 # number of cycles access was blocked
573system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
574system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
575system.iocache.writebacks::writebacks 41512 # number of writebacks
576system.iocache.writebacks::total 41512 # number of writebacks
|
| 577system.membus.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
554system.membus.trans_dist::ReadReq 7184 # Transaction distribution
555system.membus.trans_dist::ReadResp 948291 # Transaction distribution
556system.membus.trans_dist::WriteReq 9838 # Transaction distribution
557system.membus.trans_dist::WriteResp 9838 # Transaction distribution
558system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution
559system.membus.trans_dist::CleanEvict 917188 # Transaction distribution
560system.membus.trans_dist::UpgradeReq 147 # Transaction distribution
561system.membus.trans_dist::UpgradeResp 147 # Transaction distribution
562system.membus.trans_dist::ReadExReq 116925 # Transaction distribution
563system.membus.trans_dist::ReadExResp 116925 # Transaction distribution
564system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution
565system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
566system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
567system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
568system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107383 # Packet count per connected master and slave (bytes)
569system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141427 # Packet count per connected master and slave (bytes)
570system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes)
571system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes)
572system.membus.pkt_count::total 3266565 # Packet count per connected master and slave (bytes)
573system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
574system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes)
575system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes)
576system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes)
577system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes)
578system.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes)
579system.membus.snoops 0 # Total snoops (count)
580system.membus.snoop_fanout::samples 2149812 # Request fanout histogram
581system.membus.snoop_fanout::mean 1 # Request fanout histogram
582system.membus.snoop_fanout::stdev 0 # Request fanout histogram
583system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
584system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
585system.membus.snoop_fanout::1 2149812 100.00% 100.00% # Request fanout histogram
586system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
587system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
588system.membus.snoop_fanout::min_value 1 # Request fanout histogram
589system.membus.snoop_fanout::max_value 1 # Request fanout histogram
590system.membus.snoop_fanout::total 2149812 # Request fanout histogram
| 578system.membus.trans_dist::ReadReq 7184 # Transaction distribution
579system.membus.trans_dist::ReadResp 948291 # Transaction distribution
580system.membus.trans_dist::WriteReq 9838 # Transaction distribution
581system.membus.trans_dist::WriteResp 9838 # Transaction distribution
582system.membus.trans_dist::WritebackDirty 115871 # Transaction distribution
583system.membus.trans_dist::CleanEvict 917188 # Transaction distribution
584system.membus.trans_dist::UpgradeReq 147 # Transaction distribution
585system.membus.trans_dist::UpgradeResp 147 # Transaction distribution
586system.membus.trans_dist::ReadExReq 116925 # Transaction distribution
587system.membus.trans_dist::ReadExResp 116925 # Transaction distribution
588system.membus.trans_dist::ReadSharedReq 941107 # Transaction distribution
589system.membus.trans_dist::InvalidateReq 41552 # Transaction distribution
590system.membus.trans_dist::InvalidateResp 41552 # Transaction distribution
591system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 34044 # Packet count per connected master and slave (bytes)
592system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 3107383 # Packet count per connected master and slave (bytes)
593system.membus.pkt_count_system.cpu.l2cache.mem_side::total 3141427 # Packet count per connected master and slave (bytes)
594system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 125138 # Packet count per connected master and slave (bytes)
595system.membus.pkt_count_system.iocache.mem_side::total 125138 # Packet count per connected master and slave (bytes)
596system.membus.pkt_count::total 3266565 # Packet count per connected master and slave (bytes)
597system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 46126 # Cumulative packet size per connected master and slave (bytes)
598system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 72461888 # Cumulative packet size per connected master and slave (bytes)
599system.membus.pkt_size_system.cpu.l2cache.mem_side::total 72508014 # Cumulative packet size per connected master and slave (bytes)
600system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2667904 # Cumulative packet size per connected master and slave (bytes)
601system.membus.pkt_size_system.iocache.mem_side::total 2667904 # Cumulative packet size per connected master and slave (bytes)
602system.membus.pkt_size::total 75175918 # Cumulative packet size per connected master and slave (bytes)
603system.membus.snoops 0 # Total snoops (count)
604system.membus.snoop_fanout::samples 2149812 # Request fanout histogram
605system.membus.snoop_fanout::mean 1 # Request fanout histogram
606system.membus.snoop_fanout::stdev 0 # Request fanout histogram
607system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
608system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
609system.membus.snoop_fanout::1 2149812 100.00% 100.00% # Request fanout histogram
610system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
611system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
612system.membus.snoop_fanout::min_value 1 # Request fanout histogram
613system.membus.snoop_fanout::max_value 1 # Request fanout histogram
614system.membus.snoop_fanout::total 2149812 # Request fanout histogram
|
| 615system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
616system.tsunami.backdoor.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
617system.tsunami.cchip.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
618system.tsunami.pchip.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
619system.tsunami.ethernet.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
591system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
592system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
593system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
594system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
595system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
596system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
597system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
598system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
599system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
600system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
601system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
602system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
603system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
604system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
605system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
606system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
607system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
608system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
609system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
610system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
611system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
612system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
613system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
614system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
615system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
616system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
617system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
618system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
619system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
620system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
621system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
| 620system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
621system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
622system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
623system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
624system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
625system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
626system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
627system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
628system.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
629system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
630system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
631system.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
632system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR
633system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
634system.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
635system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
636system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
637system.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
638system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR
639system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
640system.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
641system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
642system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
643system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
644system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
645system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
646system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
647system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
648system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
649system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
650system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
|
| 651system.tsunami.fake_OROM.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
652system.tsunami.fake_ata0.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
653system.tsunami.fake_ata1.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
654system.tsunami.fake_pnp_addr.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
655system.tsunami.fake_pnp_read0.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
656system.tsunami.fake_pnp_read1.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
657system.tsunami.fake_pnp_read2.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
658system.tsunami.fake_pnp_read3.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
659system.tsunami.fake_pnp_read4.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
660system.tsunami.fake_pnp_read5.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
661system.tsunami.fake_pnp_read6.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
662system.tsunami.fake_pnp_read7.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
663system.tsunami.fake_pnp_write.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
664system.tsunami.fake_ppc.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
665system.tsunami.fake_sm_chip.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
666system.tsunami.fake_uart1.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
667system.tsunami.fake_uart2.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
668system.tsunami.fake_uart3.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
669system.tsunami.fake_uart4.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
670system.tsunami.fb.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
671system.tsunami.ide.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
672system.tsunami.io.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
673system.tsunami.uart.pwrStateResidencyTicks::UNDEFINED 1829331993500 # Cumulative time (in ticks) in various power states
|
622
623---------- End Simulation Statistics ----------
| 674
675---------- End Simulation Statistics ----------
|