1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.829332 # Number of seconds simulated
4sim_ticks 1829332049000 # Number of ticks simulated
5final_tick 1829332049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 2314619 # Simulator instruction rate (inst/s)
8host_op_rate 2314617 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 70524837278 # Simulator tick rate (ticks/s)
10host_mem_usage 315304 # Number of bytes of host memory used
11host_seconds 25.94 # Real time elapsed on the host
12sim_insts 60038433 # Number of instructions simulated
13sim_ops 60038433 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 66856384 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::total 67715328 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 4754240 # Number of bytes written to this memory
23system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
24system.physmem.bytes_written::total 7413568 # Number of bytes written to this memory
25system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 1044631 # Number of read requests responded to by this memory
27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
28system.physmem.num_reads::total 1058052 # Number of read requests responded to by this memory
29system.physmem.num_writes::writebacks 74285 # Number of write requests responded to by this memory
30system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
31system.physmem.num_writes::total 115837 # Number of write requests responded to by this memory
32system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.data 36546883 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::total 37016422 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
38system.physmem.bw_write::writebacks 2598894 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s)
40system.physmem.bw_write::total 4052609 # Write bandwidth from this memory (bytes/s)
41system.physmem.bw_total::writebacks 2598894 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::cpu.data 36546883 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::total 41069032 # Total bandwidth to/from this memory (bytes/s)
46system.membus.throughput 41099809 # Throughput (bytes/s)
47system.membus.data_through_bus 75185198 # Total data (bytes)
48system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
49system.iocache.tags.replacements 41686 # number of replacements
50system.iocache.tags.tagsinuse 1.225568 # Cycle average of tags in use
51system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
52system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
53system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
54system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
55system.iocache.tags.occ_blocks::tsunami.ide 1.225568 # Average occupied blocks per requestor
56system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
57system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
58system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
59system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
60system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
61system.iocache.tags.tag_accesses 375534 # Number of tag accesses
62system.iocache.tags.data_accesses 375534 # Number of data accesses
63system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
--- 39 unchanged lines hidden (view full) ---
103system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
104system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
105system.disk2.dma_write_txs 1 # Number of DMA write transactions.
106system.cpu_clk_domain.clock 500 # Clock period in ticks
107system.cpu.dtb.fetch_hits 0 # ITB hits
108system.cpu.dtb.fetch_misses 0 # ITB misses
109system.cpu.dtb.fetch_acv 0 # ITB acv
110system.cpu.dtb.fetch_accesses 0 # ITB accesses
111system.cpu.dtb.read_hits 9710428 # DTB read hits
112system.cpu.dtb.read_misses 10329 # DTB read misses
113system.cpu.dtb.read_acv 210 # DTB read access violations
114system.cpu.dtb.read_accesses 728856 # DTB read accesses
115system.cpu.dtb.write_hits 6352498 # DTB write hits
116system.cpu.dtb.write_misses 1142 # DTB write misses
117system.cpu.dtb.write_acv 157 # DTB write access violations
118system.cpu.dtb.write_accesses 291931 # DTB write accesses
119system.cpu.dtb.data_hits 16062926 # DTB hits
120system.cpu.dtb.data_misses 11471 # DTB misses
121system.cpu.dtb.data_acv 367 # DTB access violations
122system.cpu.dtb.data_accesses 1020787 # DTB accesses
123system.cpu.itb.fetch_hits 4974637 # ITB hits
124system.cpu.itb.fetch_misses 5006 # ITB misses
125system.cpu.itb.fetch_acv 184 # ITB acv
126system.cpu.itb.fetch_accesses 4979643 # ITB accesses
127system.cpu.itb.read_hits 0 # DTB read hits
128system.cpu.itb.read_misses 0 # DTB read misses
129system.cpu.itb.read_acv 0 # DTB read access violations
130system.cpu.itb.read_accesses 0 # DTB read accesses
131system.cpu.itb.write_hits 0 # DTB write hits
132system.cpu.itb.write_misses 0 # DTB write misses
133system.cpu.itb.write_acv 0 # DTB write access violations
134system.cpu.itb.write_accesses 0 # DTB write accesses
135system.cpu.itb.data_hits 0 # DTB hits
136system.cpu.itb.data_misses 0 # DTB misses
137system.cpu.itb.data_acv 0 # DTB access violations
138system.cpu.itb.data_accesses 0 # DTB accesses
139system.cpu.numCycles 3658664099 # number of cpu cycles simulated
140system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
141system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
142system.cpu.committedInsts 60038433 # Number of instructions committed
143system.cpu.committedOps 60038433 # Number of ops (including micro ops) committed
144system.cpu.num_int_alu_accesses 55913650 # Number of integer alu accesses
145system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
146system.cpu.num_func_calls 1484182 # number of times a function call or return occured
147system.cpu.num_conditional_control_insts 7110776 # number of instructions that are conditional controls
148system.cpu.num_int_insts 55913650 # number of integer instructions
149system.cpu.num_fp_insts 324460 # number of float instructions
150system.cpu.num_int_register_reads 76954165 # number of times the integer registers were read
151system.cpu.num_int_register_writes 41740323 # number of times the integer registers were written
152system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
153system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
154system.cpu.num_mem_refs 16115710 # number of memory refs
155system.cpu.num_load_insts 9747514 # Number of load instructions
156system.cpu.num_store_insts 6368196 # Number of store instructions
157system.cpu.num_idle_cycles 3598608539.425618 # Number of idle cycles
158system.cpu.num_busy_cycles 60055559.574382 # Number of busy cycles
159system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
160system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
161system.cpu.Branches 9064413 # Number of branches fetched
162system.cpu.op_class::No_OpClass 3199106 5.33% 5.33% # Class of executed instruction
163system.cpu.op_class::IntAlu 39448354 65.69% 71.02% # Class of executed instruction
164system.cpu.op_class::IntMult 60680 0.10% 71.12% # Class of executed instruction
165system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
166system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
167system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
168system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
169system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
170system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
171system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
172system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
--- 11 unchanged lines hidden (view full) ---
184system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
185system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
186system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
187system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
188system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
189system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
190system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
191system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
192system.cpu.op_class::MemRead 9975082 16.61% 87.80% # Class of executed instruction
193system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction
194system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
195system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
196system.cpu.op_class::total 60050271 # Class of executed instruction
197system.cpu.kern.inst.arm 0 # number of arm instructions executed
198system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
199system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
200system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
201system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
202system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
203system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl
204system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl
205system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
206system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
207system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
208system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
209system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
210system.cpu.kern.ipl_ticks::0 1811927133000 99.05% 99.05% # number of cycles we spent at this ipl
211system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
212system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
213system.cpu.kern.ipl_ticks::31 17304360500 0.95% 100.00% # number of cycles we spent at this ipl
214system.cpu.kern.ipl_ticks::total 1829331841500 # number of cycles we spent at this ipl
215system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
216system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
217system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
218system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl
219system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl
220system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
221system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
222system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
--- 47 unchanged lines hidden (view full) ---
270system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
271system.cpu.kern.mode_good::kernel 1908
272system.cpu.kern.mode_good::user 1737
273system.cpu.kern.mode_good::idle 171
274system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches
275system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
276system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
277system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
278system.cpu.kern.mode_ticks::kernel 26834199500 1.47% 1.47% # number of ticks spent at the given mode
279system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
280system.cpu.kern.mode_ticks::idle 1801032572000 98.45% 100.00% # number of ticks spent at the given mode
281system.cpu.kern.swap_context 4178 # number of times the context was actually changed
282system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
283system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
284system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
285system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
286system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
287system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
288system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
--- 16 unchanged lines hidden (view full) ---
305system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
306system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
307system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
308system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
309system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
310system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
311system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
312system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
313system.iobus.throughput 1480181 # Throughput (bytes/s)
314system.iobus.data_through_bus 2707742 # Total data (bytes)
315system.cpu.icache.tags.replacements 919591 # number of replacements
316system.cpu.icache.tags.tagsinuse 511.215239 # Cycle average of tags in use
317system.cpu.icache.tags.total_refs 59130053 # Total number of references to valid blocks.
318system.cpu.icache.tags.sampled_refs 920103 # Sample count of references to valid blocks.
319system.cpu.icache.tags.avg_refs 64.264602 # Average number of references to valid blocks.
320system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
321system.cpu.icache.tags.occ_blocks::cpu.inst 511.215239 # Average occupied blocks per requestor
322system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
323system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
324system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
325system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
326system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
327system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
328system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
329system.cpu.icache.tags.tag_accesses 60970489 # Number of tag accesses
330system.cpu.icache.tags.data_accesses 60970489 # Number of data accesses
331system.cpu.icache.ReadReq_hits::cpu.inst 59130053 # number of ReadReq hits
332system.cpu.icache.ReadReq_hits::total 59130053 # number of ReadReq hits
333system.cpu.icache.demand_hits::cpu.inst 59130053 # number of demand (read+write) hits
334system.cpu.icache.demand_hits::total 59130053 # number of demand (read+write) hits
335system.cpu.icache.overall_hits::cpu.inst 59130053 # number of overall hits
336system.cpu.icache.overall_hits::total 59130053 # number of overall hits
337system.cpu.icache.ReadReq_misses::cpu.inst 920218 # number of ReadReq misses
338system.cpu.icache.ReadReq_misses::total 920218 # number of ReadReq misses
339system.cpu.icache.demand_misses::cpu.inst 920218 # number of demand (read+write) misses
340system.cpu.icache.demand_misses::total 920218 # number of demand (read+write) misses
341system.cpu.icache.overall_misses::cpu.inst 920218 # number of overall misses
342system.cpu.icache.overall_misses::total 920218 # number of overall misses
343system.cpu.icache.ReadReq_accesses::cpu.inst 60050271 # number of ReadReq accesses(hits+misses)
344system.cpu.icache.ReadReq_accesses::total 60050271 # number of ReadReq accesses(hits+misses)
345system.cpu.icache.demand_accesses::cpu.inst 60050271 # number of demand (read+write) accesses
346system.cpu.icache.demand_accesses::total 60050271 # number of demand (read+write) accesses
347system.cpu.icache.overall_accesses::cpu.inst 60050271 # number of overall (read+write) accesses
348system.cpu.icache.overall_accesses::total 60050271 # number of overall (read+write) accesses
349system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
350system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
351system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
352system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
353system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
354system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
355system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
356system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
357system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
358system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
359system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
360system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
361system.cpu.icache.fast_writes 0 # number of fast writes performed
362system.cpu.icache.cache_copies 0 # number of cache copies performed
363system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
364system.cpu.l2cache.tags.replacements 992295 # number of replacements
365system.cpu.l2cache.tags.tagsinuse 65424.374544 # Cycle average of tags in use
366system.cpu.l2cache.tags.total_refs 2433214 # Total number of references to valid blocks.
367system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks.
368system.cpu.l2cache.tags.avg_refs 2.301003 # Average number of references to valid blocks.
369system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
370system.cpu.l2cache.tags.occ_blocks::writebacks 56309.107765 # Average occupied blocks per requestor
371system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.336412 # Average occupied blocks per requestor
372system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930367 # Average occupied blocks per requestor
373system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
374system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
375system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
376system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
377system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
378system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
379system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id
380system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id
381system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id
382system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id
383system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
384system.cpu.l2cache.tags.tag_accesses 31737120 # Number of tag accesses
385system.cpu.l2cache.tags.data_accesses 31737120 # Number of data accesses
386system.cpu.l2cache.ReadReq_hits::cpu.inst 906794 # number of ReadReq hits
387system.cpu.l2cache.ReadReq_hits::cpu.data 811217 # number of ReadReq hits
388system.cpu.l2cache.ReadReq_hits::total 1718011 # number of ReadReq hits
389system.cpu.l2cache.Writeback_hits::writebacks 833475 # number of Writeback hits
390system.cpu.l2cache.Writeback_hits::total 833475 # number of Writeback hits
391system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
392system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
393system.cpu.l2cache.ReadExReq_hits::cpu.data 187228 # number of ReadExReq hits
394system.cpu.l2cache.ReadExReq_hits::total 187228 # number of ReadExReq hits
395system.cpu.l2cache.demand_hits::cpu.inst 906794 # number of demand (read+write) hits
396system.cpu.l2cache.demand_hits::cpu.data 998445 # number of demand (read+write) hits
397system.cpu.l2cache.demand_hits::total 1905239 # number of demand (read+write) hits
398system.cpu.l2cache.overall_hits::cpu.inst 906794 # number of overall hits
399system.cpu.l2cache.overall_hits::cpu.data 998445 # number of overall hits
400system.cpu.l2cache.overall_hits::total 1905239 # number of overall hits
401system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
402system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
403system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
404system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
405system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
406system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses
407system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses
408system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
409system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses
410system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses
411system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
412system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses
413system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses
414system.cpu.l2cache.ReadReq_accesses::cpu.inst 920200 # number of ReadReq accesses(hits+misses)
415system.cpu.l2cache.ReadReq_accesses::cpu.data 1738857 # number of ReadReq accesses(hits+misses)
416system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses)
417system.cpu.l2cache.Writeback_accesses::writebacks 833475 # number of Writeback accesses(hits+misses)
418system.cpu.l2cache.Writeback_accesses::total 833475 # number of Writeback accesses(hits+misses)
419system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
420system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
421system.cpu.l2cache.ReadExReq_accesses::cpu.data 304339 # number of ReadExReq accesses(hits+misses)
422system.cpu.l2cache.ReadExReq_accesses::total 304339 # number of ReadExReq accesses(hits+misses)
423system.cpu.l2cache.demand_accesses::cpu.inst 920200 # number of demand (read+write) accesses
424system.cpu.l2cache.demand_accesses::cpu.data 2043196 # number of demand (read+write) accesses
425system.cpu.l2cache.demand_accesses::total 2963396 # number of demand (read+write) accesses
426system.cpu.l2cache.overall_accesses::cpu.inst 920200 # number of overall (read+write) accesses
427system.cpu.l2cache.overall_accesses::cpu.data 2043196 # number of overall (read+write) accesses
428system.cpu.l2cache.overall_accesses::total 2963396 # number of overall (read+write) accesses
429system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses
430system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533477 # miss rate for ReadReq accesses
431system.cpu.l2cache.ReadReq_miss_rate::total 0.353902 # miss rate for ReadReq accesses
432system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
433system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
434system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384804 # miss rate for ReadExReq accesses
435system.cpu.l2cache.ReadExReq_miss_rate::total 0.384804 # miss rate for ReadExReq accesses
436system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses
437system.cpu.l2cache.demand_miss_rate::cpu.data 0.511332 # miss rate for demand accesses
438system.cpu.l2cache.demand_miss_rate::total 0.357076 # miss rate for demand accesses
439system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses
440system.cpu.l2cache.overall_miss_rate::cpu.data 0.511332 # miss rate for overall accesses
441system.cpu.l2cache.overall_miss_rate::total 0.357076 # miss rate for overall accesses
442system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
443system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
444system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
445system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
446system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
447system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
448system.cpu.l2cache.fast_writes 0 # number of fast writes performed
449system.cpu.l2cache.cache_copies 0 # number of cache copies performed
450system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks
451system.cpu.l2cache.writebacks::total 74285 # number of writebacks
452system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
453system.cpu.dcache.tags.replacements 2042683 # number of replacements
454system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
455system.cpu.dcache.tags.total_refs 14038451 # Total number of references to valid blocks.
456system.cpu.dcache.tags.sampled_refs 2043195 # Sample count of references to valid blocks.
457system.cpu.dcache.tags.avg_refs 6.870833 # Average number of references to valid blocks.
458system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
459system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
460system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
461system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
462system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
463system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
464system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
465system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
466system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
467system.cpu.dcache.tags.tag_accesses 66369784 # Number of tag accesses
468system.cpu.dcache.tags.data_accesses 66369784 # Number of data accesses
469system.cpu.dcache.ReadReq_hits::cpu.data 7807792 # number of ReadReq hits
470system.cpu.dcache.ReadReq_hits::total 7807792 # number of ReadReq hits
471system.cpu.dcache.WriteReq_hits::cpu.data 5848219 # number of WriteReq hits
472system.cpu.dcache.WriteReq_hits::total 5848219 # number of WriteReq hits
473system.cpu.dcache.LoadLockedReq_hits::cpu.data 183142 # number of LoadLockedReq hits
474system.cpu.dcache.LoadLockedReq_hits::total 183142 # number of LoadLockedReq hits
475system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
476system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
477system.cpu.dcache.demand_hits::cpu.data 13656011 # number of demand (read+write) hits
478system.cpu.dcache.demand_hits::total 13656011 # number of demand (read+write) hits
479system.cpu.dcache.overall_hits::cpu.data 13656011 # number of overall hits
480system.cpu.dcache.overall_hits::total 13656011 # number of overall hits
481system.cpu.dcache.ReadReq_misses::cpu.data 1721696 # number of ReadReq misses
482system.cpu.dcache.ReadReq_misses::total 1721696 # number of ReadReq misses
483system.cpu.dcache.WriteReq_misses::cpu.data 304355 # number of WriteReq misses
484system.cpu.dcache.WriteReq_misses::total 304355 # number of WriteReq misses
485system.cpu.dcache.LoadLockedReq_misses::cpu.data 17161 # number of LoadLockedReq misses
486system.cpu.dcache.LoadLockedReq_misses::total 17161 # number of LoadLockedReq misses
487system.cpu.dcache.demand_misses::cpu.data 2026051 # number of demand (read+write) misses
488system.cpu.dcache.demand_misses::total 2026051 # number of demand (read+write) misses
489system.cpu.dcache.overall_misses::cpu.data 2026051 # number of overall misses
490system.cpu.dcache.overall_misses::total 2026051 # number of overall misses
491system.cpu.dcache.ReadReq_accesses::cpu.data 9529488 # number of ReadReq accesses(hits+misses)
492system.cpu.dcache.ReadReq_accesses::total 9529488 # number of ReadReq accesses(hits+misses)
493system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
494system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
495system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
496system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
497system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
498system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
499system.cpu.dcache.demand_accesses::cpu.data 15682062 # number of demand (read+write) accesses
500system.cpu.dcache.demand_accesses::total 15682062 # number of demand (read+write) accesses
501system.cpu.dcache.overall_accesses::cpu.data 15682062 # number of overall (read+write) accesses
502system.cpu.dcache.overall_accesses::total 15682062 # number of overall (read+write) accesses
503system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180670 # miss rate for ReadReq accesses
504system.cpu.dcache.ReadReq_miss_rate::total 0.180670 # miss rate for ReadReq accesses
505system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses
506system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses
507system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085675 # miss rate for LoadLockedReq accesses
508system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085675 # miss rate for LoadLockedReq accesses
509system.cpu.dcache.demand_miss_rate::cpu.data 0.129195 # miss rate for demand accesses
510system.cpu.dcache.demand_miss_rate::total 0.129195 # miss rate for demand accesses
511system.cpu.dcache.overall_miss_rate::cpu.data 0.129195 # miss rate for overall accesses
512system.cpu.dcache.overall_miss_rate::total 0.129195 # miss rate for overall accesses
513system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
514system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
515system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
516system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
517system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
518system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
519system.cpu.dcache.fast_writes 0 # number of fast writes performed
520system.cpu.dcache.cache_copies 0 # number of cache copies performed
521system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks
522system.cpu.dcache.writebacks::total 833475 # number of writebacks
523system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
524system.cpu.toL2Bus.throughput 134320283 # Throughput (bytes/s)
525system.cpu.toL2Bus.data_through_bus 243047022 # Total data (bytes)
526system.cpu.toL2Bus.snoop_data_through_bus 2669376 # Total snoop data (bytes)
527
528---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.829332 # Number of seconds simulated
4sim_ticks 1829332049000 # Number of ticks simulated
5final_tick 1829332049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 2314619 # Simulator instruction rate (inst/s)
8host_op_rate 2314617 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 70524837278 # Simulator tick rate (ticks/s)
10host_mem_usage 315304 # Number of bytes of host memory used
11host_seconds 25.94 # Real time elapsed on the host
12sim_insts 60038433 # Number of instructions simulated
13sim_ops 60038433 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 66856384 # Number of bytes read from this memory
18system.physmem.bytes_read::tsunami.ide 960 # Number of bytes read from this memory
19system.physmem.bytes_read::total 67715328 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 857984 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 857984 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 4754240 # Number of bytes written to this memory
23system.physmem.bytes_written::tsunami.ide 2659328 # Number of bytes written to this memory
24system.physmem.bytes_written::total 7413568 # Number of bytes written to this memory
25system.physmem.num_reads::cpu.inst 13406 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.data 1044631 # Number of read requests responded to by this memory
27system.physmem.num_reads::tsunami.ide 15 # Number of read requests responded to by this memory
28system.physmem.num_reads::total 1058052 # Number of read requests responded to by this memory
29system.physmem.num_writes::writebacks 74285 # Number of write requests responded to by this memory
30system.physmem.num_writes::tsunami.ide 41552 # Number of write requests responded to by this memory
31system.physmem.num_writes::total 115837 # Number of write requests responded to by this memory
32system.physmem.bw_read::cpu.inst 469015 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::cpu.data 36546883 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_read::tsunami.ide 525 # Total read bandwidth from this memory (bytes/s)
35system.physmem.bw_read::total 37016422 # Total read bandwidth from this memory (bytes/s)
36system.physmem.bw_inst_read::cpu.inst 469015 # Instruction read bandwidth from this memory (bytes/s)
37system.physmem.bw_inst_read::total 469015 # Instruction read bandwidth from this memory (bytes/s)
38system.physmem.bw_write::writebacks 2598894 # Write bandwidth from this memory (bytes/s)
39system.physmem.bw_write::tsunami.ide 1453715 # Write bandwidth from this memory (bytes/s)
40system.physmem.bw_write::total 4052609 # Write bandwidth from this memory (bytes/s)
41system.physmem.bw_total::writebacks 2598894 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::cpu.inst 469015 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.bw_total::cpu.data 36546883 # Total bandwidth to/from this memory (bytes/s)
44system.physmem.bw_total::tsunami.ide 1454240 # Total bandwidth to/from this memory (bytes/s)
45system.physmem.bw_total::total 41069032 # Total bandwidth to/from this memory (bytes/s)
46system.membus.throughput 41099809 # Throughput (bytes/s)
47system.membus.data_through_bus 75185198 # Total data (bytes)
48system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
49system.iocache.tags.replacements 41686 # number of replacements
50system.iocache.tags.tagsinuse 1.225568 # Cycle average of tags in use
51system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
52system.iocache.tags.sampled_refs 41702 # Sample count of references to valid blocks.
53system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
54system.iocache.tags.warmup_cycle 1685780659017 # Cycle when the warmup percentage was hit.
55system.iocache.tags.occ_blocks::tsunami.ide 1.225568 # Average occupied blocks per requestor
56system.iocache.tags.occ_percent::tsunami.ide 0.076598 # Average percentage of cache occupancy
57system.iocache.tags.occ_percent::total 0.076598 # Average percentage of cache occupancy
58system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
59system.iocache.tags.age_task_id_blocks_1023::2 16 # Occupied blocks per task id
60system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
61system.iocache.tags.tag_accesses 375534 # Number of tag accesses
62system.iocache.tags.data_accesses 375534 # Number of data accesses
63system.iocache.WriteInvalidateReq_hits::tsunami.ide 41552 # number of WriteInvalidateReq hits
--- 39 unchanged lines hidden (view full) ---
103system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
104system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
105system.disk2.dma_write_txs 1 # Number of DMA write transactions.
106system.cpu_clk_domain.clock 500 # Clock period in ticks
107system.cpu.dtb.fetch_hits 0 # ITB hits
108system.cpu.dtb.fetch_misses 0 # ITB misses
109system.cpu.dtb.fetch_acv 0 # ITB acv
110system.cpu.dtb.fetch_accesses 0 # ITB accesses
111system.cpu.dtb.read_hits 9710428 # DTB read hits
112system.cpu.dtb.read_misses 10329 # DTB read misses
113system.cpu.dtb.read_acv 210 # DTB read access violations
114system.cpu.dtb.read_accesses 728856 # DTB read accesses
115system.cpu.dtb.write_hits 6352498 # DTB write hits
116system.cpu.dtb.write_misses 1142 # DTB write misses
117system.cpu.dtb.write_acv 157 # DTB write access violations
118system.cpu.dtb.write_accesses 291931 # DTB write accesses
119system.cpu.dtb.data_hits 16062926 # DTB hits
120system.cpu.dtb.data_misses 11471 # DTB misses
121system.cpu.dtb.data_acv 367 # DTB access violations
122system.cpu.dtb.data_accesses 1020787 # DTB accesses
123system.cpu.itb.fetch_hits 4974637 # ITB hits
124system.cpu.itb.fetch_misses 5006 # ITB misses
125system.cpu.itb.fetch_acv 184 # ITB acv
126system.cpu.itb.fetch_accesses 4979643 # ITB accesses
127system.cpu.itb.read_hits 0 # DTB read hits
128system.cpu.itb.read_misses 0 # DTB read misses
129system.cpu.itb.read_acv 0 # DTB read access violations
130system.cpu.itb.read_accesses 0 # DTB read accesses
131system.cpu.itb.write_hits 0 # DTB write hits
132system.cpu.itb.write_misses 0 # DTB write misses
133system.cpu.itb.write_acv 0 # DTB write access violations
134system.cpu.itb.write_accesses 0 # DTB write accesses
135system.cpu.itb.data_hits 0 # DTB hits
136system.cpu.itb.data_misses 0 # DTB misses
137system.cpu.itb.data_acv 0 # DTB access violations
138system.cpu.itb.data_accesses 0 # DTB accesses
139system.cpu.numCycles 3658664099 # number of cpu cycles simulated
140system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
141system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
142system.cpu.committedInsts 60038433 # Number of instructions committed
143system.cpu.committedOps 60038433 # Number of ops (including micro ops) committed
144system.cpu.num_int_alu_accesses 55913650 # Number of integer alu accesses
145system.cpu.num_fp_alu_accesses 324460 # Number of float alu accesses
146system.cpu.num_func_calls 1484182 # number of times a function call or return occured
147system.cpu.num_conditional_control_insts 7110776 # number of instructions that are conditional controls
148system.cpu.num_int_insts 55913650 # number of integer instructions
149system.cpu.num_fp_insts 324460 # number of float instructions
150system.cpu.num_int_register_reads 76954165 # number of times the integer registers were read
151system.cpu.num_int_register_writes 41740323 # number of times the integer registers were written
152system.cpu.num_fp_register_reads 163642 # number of times the floating registers were read
153system.cpu.num_fp_register_writes 166520 # number of times the floating registers were written
154system.cpu.num_mem_refs 16115710 # number of memory refs
155system.cpu.num_load_insts 9747514 # Number of load instructions
156system.cpu.num_store_insts 6368196 # Number of store instructions
157system.cpu.num_idle_cycles 3598608539.425618 # Number of idle cycles
158system.cpu.num_busy_cycles 60055559.574382 # Number of busy cycles
159system.cpu.not_idle_fraction 0.016415 # Percentage of non-idle cycles
160system.cpu.idle_fraction 0.983585 # Percentage of idle cycles
161system.cpu.Branches 9064413 # Number of branches fetched
162system.cpu.op_class::No_OpClass 3199106 5.33% 5.33% # Class of executed instruction
163system.cpu.op_class::IntAlu 39448354 65.69% 71.02% # Class of executed instruction
164system.cpu.op_class::IntMult 60680 0.10% 71.12% # Class of executed instruction
165system.cpu.op_class::IntDiv 0 0.00% 71.12% # Class of executed instruction
166system.cpu.op_class::FloatAdd 38087 0.06% 71.18% # Class of executed instruction
167system.cpu.op_class::FloatCmp 0 0.00% 71.18% # Class of executed instruction
168system.cpu.op_class::FloatCvt 0 0.00% 71.18% # Class of executed instruction
169system.cpu.op_class::FloatMult 0 0.00% 71.18% # Class of executed instruction
170system.cpu.op_class::FloatDiv 3636 0.01% 71.19% # Class of executed instruction
171system.cpu.op_class::FloatSqrt 0 0.00% 71.19% # Class of executed instruction
172system.cpu.op_class::SimdAdd 0 0.00% 71.19% # Class of executed instruction
--- 11 unchanged lines hidden (view full) ---
184system.cpu.op_class::SimdFloatAlu 0 0.00% 71.19% # Class of executed instruction
185system.cpu.op_class::SimdFloatCmp 0 0.00% 71.19% # Class of executed instruction
186system.cpu.op_class::SimdFloatCvt 0 0.00% 71.19% # Class of executed instruction
187system.cpu.op_class::SimdFloatDiv 0 0.00% 71.19% # Class of executed instruction
188system.cpu.op_class::SimdFloatMisc 0 0.00% 71.19% # Class of executed instruction
189system.cpu.op_class::SimdFloatMult 0 0.00% 71.19% # Class of executed instruction
190system.cpu.op_class::SimdFloatMultAcc 0 0.00% 71.19% # Class of executed instruction
191system.cpu.op_class::SimdFloatSqrt 0 0.00% 71.19% # Class of executed instruction
192system.cpu.op_class::MemRead 9975082 16.61% 87.80% # Class of executed instruction
193system.cpu.op_class::MemWrite 6374117 10.61% 98.42% # Class of executed instruction
194system.cpu.op_class::IprAccess 951209 1.58% 100.00% # Class of executed instruction
195system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
196system.cpu.op_class::total 60050271 # Class of executed instruction
197system.cpu.kern.inst.arm 0 # number of arm instructions executed
198system.cpu.kern.inst.quiesce 6357 # number of quiesce instructions executed
199system.cpu.kern.inst.hwrei 211318 # number of hwrei instructions executed
200system.cpu.kern.ipl_count::0 74830 40.99% 40.99% # number of times we switched to this ipl
201system.cpu.kern.ipl_count::21 243 0.13% 41.12% # number of times we switched to this ipl
202system.cpu.kern.ipl_count::22 1866 1.02% 42.14% # number of times we switched to this ipl
203system.cpu.kern.ipl_count::31 105622 57.86% 100.00% # number of times we switched to this ipl
204system.cpu.kern.ipl_count::total 182561 # number of times we switched to this ipl
205system.cpu.kern.ipl_good::0 73463 49.29% 49.29% # number of times we switched to this ipl from a different ipl
206system.cpu.kern.ipl_good::21 243 0.16% 49.46% # number of times we switched to this ipl from a different ipl
207system.cpu.kern.ipl_good::22 1866 1.25% 50.71% # number of times we switched to this ipl from a different ipl
208system.cpu.kern.ipl_good::31 73463 49.29% 100.00% # number of times we switched to this ipl from a different ipl
209system.cpu.kern.ipl_good::total 149035 # number of times we switched to this ipl from a different ipl
210system.cpu.kern.ipl_ticks::0 1811927133000 99.05% 99.05% # number of cycles we spent at this ipl
211system.cpu.kern.ipl_ticks::21 20110000 0.00% 99.05% # number of cycles we spent at this ipl
212system.cpu.kern.ipl_ticks::22 80238000 0.00% 99.05% # number of cycles we spent at this ipl
213system.cpu.kern.ipl_ticks::31 17304360500 0.95% 100.00% # number of cycles we spent at this ipl
214system.cpu.kern.ipl_ticks::total 1829331841500 # number of cycles we spent at this ipl
215system.cpu.kern.ipl_used::0 0.981732 # fraction of swpipl calls that actually changed the ipl
216system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
217system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
218system.cpu.kern.ipl_used::31 0.695527 # fraction of swpipl calls that actually changed the ipl
219system.cpu.kern.ipl_used::total 0.816357 # fraction of swpipl calls that actually changed the ipl
220system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed
221system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed
222system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed
--- 47 unchanged lines hidden (view full) ---
270system.cpu.kern.mode_switch::idle 2097 # number of protection mode switches
271system.cpu.kern.mode_good::kernel 1908
272system.cpu.kern.mode_good::user 1737
273system.cpu.kern.mode_good::idle 171
274system.cpu.kern.mode_switch_good::kernel 0.320726 # fraction of useful protection mode switches
275system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
276system.cpu.kern.mode_switch_good::idle 0.081545 # fraction of useful protection mode switches
277system.cpu.kern.mode_switch_good::total 0.390064 # fraction of useful protection mode switches
278system.cpu.kern.mode_ticks::kernel 26834199500 1.47% 1.47% # number of ticks spent at the given mode
279system.cpu.kern.mode_ticks::user 1465069000 0.08% 1.55% # number of ticks spent at the given mode
280system.cpu.kern.mode_ticks::idle 1801032572000 98.45% 100.00% # number of ticks spent at the given mode
281system.cpu.kern.swap_context 4178 # number of times the context was actually changed
282system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
283system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
284system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
285system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
286system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU
287system.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
288system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR
--- 16 unchanged lines hidden (view full) ---
305system.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
306system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
307system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
308system.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
309system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
310system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
311system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
312system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
313system.iobus.throughput 1480181 # Throughput (bytes/s)
314system.iobus.data_through_bus 2707742 # Total data (bytes)
315system.cpu.icache.tags.replacements 919591 # number of replacements
316system.cpu.icache.tags.tagsinuse 511.215239 # Cycle average of tags in use
317system.cpu.icache.tags.total_refs 59130053 # Total number of references to valid blocks.
318system.cpu.icache.tags.sampled_refs 920103 # Sample count of references to valid blocks.
319system.cpu.icache.tags.avg_refs 64.264602 # Average number of references to valid blocks.
320system.cpu.icache.tags.warmup_cycle 9686972500 # Cycle when the warmup percentage was hit.
321system.cpu.icache.tags.occ_blocks::cpu.inst 511.215239 # Average occupied blocks per requestor
322system.cpu.icache.tags.occ_percent::cpu.inst 0.998467 # Average percentage of cache occupancy
323system.cpu.icache.tags.occ_percent::total 0.998467 # Average percentage of cache occupancy
324system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
325system.cpu.icache.tags.age_task_id_blocks_1024::0 63 # Occupied blocks per task id
326system.cpu.icache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
327system.cpu.icache.tags.age_task_id_blocks_1024::2 332 # Occupied blocks per task id
328system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
329system.cpu.icache.tags.tag_accesses 60970489 # Number of tag accesses
330system.cpu.icache.tags.data_accesses 60970489 # Number of data accesses
331system.cpu.icache.ReadReq_hits::cpu.inst 59130053 # number of ReadReq hits
332system.cpu.icache.ReadReq_hits::total 59130053 # number of ReadReq hits
333system.cpu.icache.demand_hits::cpu.inst 59130053 # number of demand (read+write) hits
334system.cpu.icache.demand_hits::total 59130053 # number of demand (read+write) hits
335system.cpu.icache.overall_hits::cpu.inst 59130053 # number of overall hits
336system.cpu.icache.overall_hits::total 59130053 # number of overall hits
337system.cpu.icache.ReadReq_misses::cpu.inst 920218 # number of ReadReq misses
338system.cpu.icache.ReadReq_misses::total 920218 # number of ReadReq misses
339system.cpu.icache.demand_misses::cpu.inst 920218 # number of demand (read+write) misses
340system.cpu.icache.demand_misses::total 920218 # number of demand (read+write) misses
341system.cpu.icache.overall_misses::cpu.inst 920218 # number of overall misses
342system.cpu.icache.overall_misses::total 920218 # number of overall misses
343system.cpu.icache.ReadReq_accesses::cpu.inst 60050271 # number of ReadReq accesses(hits+misses)
344system.cpu.icache.ReadReq_accesses::total 60050271 # number of ReadReq accesses(hits+misses)
345system.cpu.icache.demand_accesses::cpu.inst 60050271 # number of demand (read+write) accesses
346system.cpu.icache.demand_accesses::total 60050271 # number of demand (read+write) accesses
347system.cpu.icache.overall_accesses::cpu.inst 60050271 # number of overall (read+write) accesses
348system.cpu.icache.overall_accesses::total 60050271 # number of overall (read+write) accesses
349system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.015324 # miss rate for ReadReq accesses
350system.cpu.icache.ReadReq_miss_rate::total 0.015324 # miss rate for ReadReq accesses
351system.cpu.icache.demand_miss_rate::cpu.inst 0.015324 # miss rate for demand accesses
352system.cpu.icache.demand_miss_rate::total 0.015324 # miss rate for demand accesses
353system.cpu.icache.overall_miss_rate::cpu.inst 0.015324 # miss rate for overall accesses
354system.cpu.icache.overall_miss_rate::total 0.015324 # miss rate for overall accesses
355system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
356system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
357system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
358system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
359system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
360system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
361system.cpu.icache.fast_writes 0 # number of fast writes performed
362system.cpu.icache.cache_copies 0 # number of cache copies performed
363system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
364system.cpu.l2cache.tags.replacements 992295 # number of replacements
365system.cpu.l2cache.tags.tagsinuse 65424.374544 # Cycle average of tags in use
366system.cpu.l2cache.tags.total_refs 2433214 # Total number of references to valid blocks.
367system.cpu.l2cache.tags.sampled_refs 1057458 # Sample count of references to valid blocks.
368system.cpu.l2cache.tags.avg_refs 2.301003 # Average number of references to valid blocks.
369system.cpu.l2cache.tags.warmup_cycle 614754000 # Cycle when the warmup percentage was hit.
370system.cpu.l2cache.tags.occ_blocks::writebacks 56309.107765 # Average occupied blocks per requestor
371system.cpu.l2cache.tags.occ_blocks::cpu.inst 4867.336412 # Average occupied blocks per requestor
372system.cpu.l2cache.tags.occ_blocks::cpu.data 4247.930367 # Average occupied blocks per requestor
373system.cpu.l2cache.tags.occ_percent::writebacks 0.859209 # Average percentage of cache occupancy
374system.cpu.l2cache.tags.occ_percent::cpu.inst 0.074270 # Average percentage of cache occupancy
375system.cpu.l2cache.tags.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy
376system.cpu.l2cache.tags.occ_percent::total 0.998297 # Average percentage of cache occupancy
377system.cpu.l2cache.tags.occ_task_id_blocks::1024 65163 # Occupied blocks per task id
378system.cpu.l2cache.tags.age_task_id_blocks_1024::0 781 # Occupied blocks per task id
379system.cpu.l2cache.tags.age_task_id_blocks_1024::1 3260 # Occupied blocks per task id
380system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4024 # Occupied blocks per task id
381system.cpu.l2cache.tags.age_task_id_blocks_1024::3 3048 # Occupied blocks per task id
382system.cpu.l2cache.tags.age_task_id_blocks_1024::4 54050 # Occupied blocks per task id
383system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994308 # Percentage of cache occupancy per task id
384system.cpu.l2cache.tags.tag_accesses 31737120 # Number of tag accesses
385system.cpu.l2cache.tags.data_accesses 31737120 # Number of data accesses
386system.cpu.l2cache.ReadReq_hits::cpu.inst 906794 # number of ReadReq hits
387system.cpu.l2cache.ReadReq_hits::cpu.data 811217 # number of ReadReq hits
388system.cpu.l2cache.ReadReq_hits::total 1718011 # number of ReadReq hits
389system.cpu.l2cache.Writeback_hits::writebacks 833475 # number of Writeback hits
390system.cpu.l2cache.Writeback_hits::total 833475 # number of Writeback hits
391system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
392system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
393system.cpu.l2cache.ReadExReq_hits::cpu.data 187228 # number of ReadExReq hits
394system.cpu.l2cache.ReadExReq_hits::total 187228 # number of ReadExReq hits
395system.cpu.l2cache.demand_hits::cpu.inst 906794 # number of demand (read+write) hits
396system.cpu.l2cache.demand_hits::cpu.data 998445 # number of demand (read+write) hits
397system.cpu.l2cache.demand_hits::total 1905239 # number of demand (read+write) hits
398system.cpu.l2cache.overall_hits::cpu.inst 906794 # number of overall hits
399system.cpu.l2cache.overall_hits::cpu.data 998445 # number of overall hits
400system.cpu.l2cache.overall_hits::total 1905239 # number of overall hits
401system.cpu.l2cache.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses
402system.cpu.l2cache.ReadReq_misses::cpu.data 927640 # number of ReadReq misses
403system.cpu.l2cache.ReadReq_misses::total 941046 # number of ReadReq misses
404system.cpu.l2cache.UpgradeReq_misses::cpu.data 12 # number of UpgradeReq misses
405system.cpu.l2cache.UpgradeReq_misses::total 12 # number of UpgradeReq misses
406system.cpu.l2cache.ReadExReq_misses::cpu.data 117111 # number of ReadExReq misses
407system.cpu.l2cache.ReadExReq_misses::total 117111 # number of ReadExReq misses
408system.cpu.l2cache.demand_misses::cpu.inst 13406 # number of demand (read+write) misses
409system.cpu.l2cache.demand_misses::cpu.data 1044751 # number of demand (read+write) misses
410system.cpu.l2cache.demand_misses::total 1058157 # number of demand (read+write) misses
411system.cpu.l2cache.overall_misses::cpu.inst 13406 # number of overall misses
412system.cpu.l2cache.overall_misses::cpu.data 1044751 # number of overall misses
413system.cpu.l2cache.overall_misses::total 1058157 # number of overall misses
414system.cpu.l2cache.ReadReq_accesses::cpu.inst 920200 # number of ReadReq accesses(hits+misses)
415system.cpu.l2cache.ReadReq_accesses::cpu.data 1738857 # number of ReadReq accesses(hits+misses)
416system.cpu.l2cache.ReadReq_accesses::total 2659057 # number of ReadReq accesses(hits+misses)
417system.cpu.l2cache.Writeback_accesses::writebacks 833475 # number of Writeback accesses(hits+misses)
418system.cpu.l2cache.Writeback_accesses::total 833475 # number of Writeback accesses(hits+misses)
419system.cpu.l2cache.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses)
420system.cpu.l2cache.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses)
421system.cpu.l2cache.ReadExReq_accesses::cpu.data 304339 # number of ReadExReq accesses(hits+misses)
422system.cpu.l2cache.ReadExReq_accesses::total 304339 # number of ReadExReq accesses(hits+misses)
423system.cpu.l2cache.demand_accesses::cpu.inst 920200 # number of demand (read+write) accesses
424system.cpu.l2cache.demand_accesses::cpu.data 2043196 # number of demand (read+write) accesses
425system.cpu.l2cache.demand_accesses::total 2963396 # number of demand (read+write) accesses
426system.cpu.l2cache.overall_accesses::cpu.inst 920200 # number of overall (read+write) accesses
427system.cpu.l2cache.overall_accesses::cpu.data 2043196 # number of overall (read+write) accesses
428system.cpu.l2cache.overall_accesses::total 2963396 # number of overall (read+write) accesses
429system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses
430system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.533477 # miss rate for ReadReq accesses
431system.cpu.l2cache.ReadReq_miss_rate::total 0.353902 # miss rate for ReadReq accesses
432system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses
433system.cpu.l2cache.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses
434system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.384804 # miss rate for ReadExReq accesses
435system.cpu.l2cache.ReadExReq_miss_rate::total 0.384804 # miss rate for ReadExReq accesses
436system.cpu.l2cache.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses
437system.cpu.l2cache.demand_miss_rate::cpu.data 0.511332 # miss rate for demand accesses
438system.cpu.l2cache.demand_miss_rate::total 0.357076 # miss rate for demand accesses
439system.cpu.l2cache.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses
440system.cpu.l2cache.overall_miss_rate::cpu.data 0.511332 # miss rate for overall accesses
441system.cpu.l2cache.overall_miss_rate::total 0.357076 # miss rate for overall accesses
442system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
443system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
444system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
445system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
446system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
447system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
448system.cpu.l2cache.fast_writes 0 # number of fast writes performed
449system.cpu.l2cache.cache_copies 0 # number of cache copies performed
450system.cpu.l2cache.writebacks::writebacks 74285 # number of writebacks
451system.cpu.l2cache.writebacks::total 74285 # number of writebacks
452system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
453system.cpu.dcache.tags.replacements 2042683 # number of replacements
454system.cpu.dcache.tags.tagsinuse 511.997802 # Cycle average of tags in use
455system.cpu.dcache.tags.total_refs 14038451 # Total number of references to valid blocks.
456system.cpu.dcache.tags.sampled_refs 2043195 # Sample count of references to valid blocks.
457system.cpu.dcache.tags.avg_refs 6.870833 # Average number of references to valid blocks.
458system.cpu.dcache.tags.warmup_cycle 10840000 # Cycle when the warmup percentage was hit.
459system.cpu.dcache.tags.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
460system.cpu.dcache.tags.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
461system.cpu.dcache.tags.occ_percent::total 0.999996 # Average percentage of cache occupancy
462system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
463system.cpu.dcache.tags.age_task_id_blocks_1024::0 443 # Occupied blocks per task id
464system.cpu.dcache.tags.age_task_id_blocks_1024::1 66 # Occupied blocks per task id
465system.cpu.dcache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
466system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
467system.cpu.dcache.tags.tag_accesses 66369784 # Number of tag accesses
468system.cpu.dcache.tags.data_accesses 66369784 # Number of data accesses
469system.cpu.dcache.ReadReq_hits::cpu.data 7807792 # number of ReadReq hits
470system.cpu.dcache.ReadReq_hits::total 7807792 # number of ReadReq hits
471system.cpu.dcache.WriteReq_hits::cpu.data 5848219 # number of WriteReq hits
472system.cpu.dcache.WriteReq_hits::total 5848219 # number of WriteReq hits
473system.cpu.dcache.LoadLockedReq_hits::cpu.data 183142 # number of LoadLockedReq hits
474system.cpu.dcache.LoadLockedReq_hits::total 183142 # number of LoadLockedReq hits
475system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
476system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
477system.cpu.dcache.demand_hits::cpu.data 13656011 # number of demand (read+write) hits
478system.cpu.dcache.demand_hits::total 13656011 # number of demand (read+write) hits
479system.cpu.dcache.overall_hits::cpu.data 13656011 # number of overall hits
480system.cpu.dcache.overall_hits::total 13656011 # number of overall hits
481system.cpu.dcache.ReadReq_misses::cpu.data 1721696 # number of ReadReq misses
482system.cpu.dcache.ReadReq_misses::total 1721696 # number of ReadReq misses
483system.cpu.dcache.WriteReq_misses::cpu.data 304355 # number of WriteReq misses
484system.cpu.dcache.WriteReq_misses::total 304355 # number of WriteReq misses
485system.cpu.dcache.LoadLockedReq_misses::cpu.data 17161 # number of LoadLockedReq misses
486system.cpu.dcache.LoadLockedReq_misses::total 17161 # number of LoadLockedReq misses
487system.cpu.dcache.demand_misses::cpu.data 2026051 # number of demand (read+write) misses
488system.cpu.dcache.demand_misses::total 2026051 # number of demand (read+write) misses
489system.cpu.dcache.overall_misses::cpu.data 2026051 # number of overall misses
490system.cpu.dcache.overall_misses::total 2026051 # number of overall misses
491system.cpu.dcache.ReadReq_accesses::cpu.data 9529488 # number of ReadReq accesses(hits+misses)
492system.cpu.dcache.ReadReq_accesses::total 9529488 # number of ReadReq accesses(hits+misses)
493system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
494system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
495system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
496system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
497system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
498system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
499system.cpu.dcache.demand_accesses::cpu.data 15682062 # number of demand (read+write) accesses
500system.cpu.dcache.demand_accesses::total 15682062 # number of demand (read+write) accesses
501system.cpu.dcache.overall_accesses::cpu.data 15682062 # number of overall (read+write) accesses
502system.cpu.dcache.overall_accesses::total 15682062 # number of overall (read+write) accesses
503system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180670 # miss rate for ReadReq accesses
504system.cpu.dcache.ReadReq_miss_rate::total 0.180670 # miss rate for ReadReq accesses
505system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049468 # miss rate for WriteReq accesses
506system.cpu.dcache.WriteReq_miss_rate::total 0.049468 # miss rate for WriteReq accesses
507system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085675 # miss rate for LoadLockedReq accesses
508system.cpu.dcache.LoadLockedReq_miss_rate::total 0.085675 # miss rate for LoadLockedReq accesses
509system.cpu.dcache.demand_miss_rate::cpu.data 0.129195 # miss rate for demand accesses
510system.cpu.dcache.demand_miss_rate::total 0.129195 # miss rate for demand accesses
511system.cpu.dcache.overall_miss_rate::cpu.data 0.129195 # miss rate for overall accesses
512system.cpu.dcache.overall_miss_rate::total 0.129195 # miss rate for overall accesses
513system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
514system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
515system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
516system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
517system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
518system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
519system.cpu.dcache.fast_writes 0 # number of fast writes performed
520system.cpu.dcache.cache_copies 0 # number of cache copies performed
521system.cpu.dcache.writebacks::writebacks 833475 # number of writebacks
522system.cpu.dcache.writebacks::total 833475 # number of writebacks
523system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
524system.cpu.toL2Bus.throughput 134320283 # Throughput (bytes/s)
525system.cpu.toL2Bus.data_through_bus 243047022 # Total data (bytes)
526system.cpu.toL2Bus.snoop_data_through_bus 2669376 # Total snoop data (bytes)
527
528---------- End Simulation Statistics ----------