| config.ini (9924:31ef410b6843) | config.ini (9988:0b2e590c85be) |
|---|---|
| 1[root] 2type=Root 3children=system | 1[root] 2type=Root 3children=system |
| 4eventq_index=0 |
|
| 4full_system=false | 5full_system=false |
| 6sim_quantum=0 |
|
| 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 12boot_osflags=a 13cache_line_size=64 14clk_domain=system.clk_domain | 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain |
| 17eventq_index=0 |
|
| 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= --- 5 unchanged lines hidden (view full) --- 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 | 18init_param=0 19kernel= 20load_addr_mask=1099511627775 21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= --- 5 unchanged lines hidden (view full) --- 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 |
| 39eventq_index=0 |
|
| 36voltage_domain=system.voltage_domain 37 38[system.cpu] 39type=DerivO3CPU 40children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 59decodeToFetchDelay=1 60decodeToRenameDelay=1 61decodeWidth=8 62dispatchWidth=8 63do_checkpoint_insts=true 64do_quiesce=true 65do_statistics_insts=true 66dtb=system.cpu.dtb | 40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=DerivO3CPU 44children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true --- 15 unchanged lines hidden (view full) --- 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu.dtb |
| 71eventq_index=0 72fetchBufferSize=64 |
|
| 67fetchToDecodeDelay=1 68fetchTrapLatency=1 69fetchWidth=8 70forwardComSize=5 71fuPool=system.cpu.fuPool 72function_trace=false 73function_trace_start=0 74iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 123 124[system.cpu.branchPred] 125type=BranchPredictor 126BTBEntries=4096 127BTBTagSize=16 128RASSize=16 129choiceCtrBits=2 130choicePredictorSize=8192 | 73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 --- 48 unchanged lines hidden (view full) --- 129 130[system.cpu.branchPred] 131type=BranchPredictor 132BTBEntries=4096 133BTBTagSize=16 134RASSize=16 135choiceCtrBits=2 136choicePredictorSize=8192 |
| 137eventq_index=0 |
|
| 131globalCtrBits=2 132globalPredictorSize=8192 133instShiftAmt=2 134localCtrBits=2 135localHistoryTableSize=2048 136localPredictorSize=2048 137numThreads=1 138predType=tournament 139 140[system.cpu.dcache] 141type=BaseCache 142children=tags 143addr_ranges=0:18446744073709551615 144assoc=2 145clk_domain=system.cpu_clk_domain | 138globalCtrBits=2 139globalPredictorSize=8192 140instShiftAmt=2 141localCtrBits=2 142localHistoryTableSize=2048 143localPredictorSize=2048 144numThreads=1 145predType=tournament 146 147[system.cpu.dcache] 148type=BaseCache 149children=tags 150addr_ranges=0:18446744073709551615 151assoc=2 152clk_domain=system.cpu_clk_domain |
| 153eventq_index=0 |
|
| 146forward_snoops=true 147hit_latency=2 148is_top_level=true 149max_miss_count=0 150mshrs=4 151prefetch_on_access=false 152prefetcher=Null 153response_latency=2 --- 6 unchanged lines hidden (view full) --- 160cpu_side=system.cpu.dcache_port 161mem_side=system.cpu.toL2Bus.slave[1] 162 163[system.cpu.dcache.tags] 164type=LRU 165assoc=2 166block_size=64 167clk_domain=system.cpu_clk_domain | 154forward_snoops=true 155hit_latency=2 156is_top_level=true 157max_miss_count=0 158mshrs=4 159prefetch_on_access=false 160prefetcher=Null 161response_latency=2 --- 6 unchanged lines hidden (view full) --- 168cpu_side=system.cpu.dcache_port 169mem_side=system.cpu.toL2Bus.slave[1] 170 171[system.cpu.dcache.tags] 172type=LRU 173assoc=2 174block_size=64 175clk_domain=system.cpu_clk_domain |
| 176eventq_index=0 |
|
| 168hit_latency=2 169size=262144 170 171[system.cpu.dtb] 172type=ArmTLB 173children=walker | 177hit_latency=2 178size=262144 179 180[system.cpu.dtb] 181type=ArmTLB 182children=walker |
| 183eventq_index=0 |
|
| 174size=64 175walker=system.cpu.dtb.walker 176 177[system.cpu.dtb.walker] 178type=ArmTableWalker 179clk_domain=system.cpu_clk_domain | 184size=64 185walker=system.cpu.dtb.walker 186 187[system.cpu.dtb.walker] 188type=ArmTableWalker 189clk_domain=system.cpu_clk_domain |
| 190eventq_index=0 |
|
| 180num_squash_per_cycle=2 181sys=system 182port=system.cpu.toL2Bus.slave[3] 183 184[system.cpu.fuPool] 185type=FUPool 186children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 187FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 | 191num_squash_per_cycle=2 192sys=system 193port=system.cpu.toL2Bus.slave[3] 194 195[system.cpu.fuPool] 196type=FUPool 197children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 198FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 |
| 199eventq_index=0 |
|
| 188 189[system.cpu.fuPool.FUList0] 190type=FUDesc 191children=opList 192count=6 | 200 201[system.cpu.fuPool.FUList0] 202type=FUDesc 203children=opList 204count=6 |
| 205eventq_index=0 |
|
| 193opList=system.cpu.fuPool.FUList0.opList 194 195[system.cpu.fuPool.FUList0.opList] 196type=OpDesc | 206opList=system.cpu.fuPool.FUList0.opList 207 208[system.cpu.fuPool.FUList0.opList] 209type=OpDesc |
| 210eventq_index=0 |
|
| 197issueLat=1 198opClass=IntAlu 199opLat=1 200 201[system.cpu.fuPool.FUList1] 202type=FUDesc 203children=opList0 opList1 204count=2 | 211issueLat=1 212opClass=IntAlu 213opLat=1 214 215[system.cpu.fuPool.FUList1] 216type=FUDesc 217children=opList0 opList1 218count=2 |
| 219eventq_index=0 |
|
| 205opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 206 207[system.cpu.fuPool.FUList1.opList0] 208type=OpDesc | 220opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 221 222[system.cpu.fuPool.FUList1.opList0] 223type=OpDesc |
| 224eventq_index=0 |
|
| 209issueLat=1 210opClass=IntMult 211opLat=3 212 213[system.cpu.fuPool.FUList1.opList1] 214type=OpDesc | 225issueLat=1 226opClass=IntMult 227opLat=3 228 229[system.cpu.fuPool.FUList1.opList1] 230type=OpDesc |
| 231eventq_index=0 |
|
| 215issueLat=19 216opClass=IntDiv 217opLat=20 218 219[system.cpu.fuPool.FUList2] 220type=FUDesc 221children=opList0 opList1 opList2 222count=4 | 232issueLat=19 233opClass=IntDiv 234opLat=20 235 236[system.cpu.fuPool.FUList2] 237type=FUDesc 238children=opList0 opList1 opList2 239count=4 |
| 240eventq_index=0 |
|
| 223opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 224 225[system.cpu.fuPool.FUList2.opList0] 226type=OpDesc | 241opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 242 243[system.cpu.fuPool.FUList2.opList0] 244type=OpDesc |
| 245eventq_index=0 |
|
| 227issueLat=1 228opClass=FloatAdd 229opLat=2 230 231[system.cpu.fuPool.FUList2.opList1] 232type=OpDesc | 246issueLat=1 247opClass=FloatAdd 248opLat=2 249 250[system.cpu.fuPool.FUList2.opList1] 251type=OpDesc |
| 252eventq_index=0 |
|
| 233issueLat=1 234opClass=FloatCmp 235opLat=2 236 237[system.cpu.fuPool.FUList2.opList2] 238type=OpDesc | 253issueLat=1 254opClass=FloatCmp 255opLat=2 256 257[system.cpu.fuPool.FUList2.opList2] 258type=OpDesc |
| 259eventq_index=0 |
|
| 239issueLat=1 240opClass=FloatCvt 241opLat=2 242 243[system.cpu.fuPool.FUList3] 244type=FUDesc 245children=opList0 opList1 opList2 246count=2 | 260issueLat=1 261opClass=FloatCvt 262opLat=2 263 264[system.cpu.fuPool.FUList3] 265type=FUDesc 266children=opList0 opList1 opList2 267count=2 |
| 268eventq_index=0 |
|
| 247opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 248 249[system.cpu.fuPool.FUList3.opList0] 250type=OpDesc | 269opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 270 271[system.cpu.fuPool.FUList3.opList0] 272type=OpDesc |
| 273eventq_index=0 |
|
| 251issueLat=1 252opClass=FloatMult 253opLat=4 254 255[system.cpu.fuPool.FUList3.opList1] 256type=OpDesc | 274issueLat=1 275opClass=FloatMult 276opLat=4 277 278[system.cpu.fuPool.FUList3.opList1] 279type=OpDesc |
| 280eventq_index=0 |
|
| 257issueLat=12 258opClass=FloatDiv 259opLat=12 260 261[system.cpu.fuPool.FUList3.opList2] 262type=OpDesc | 281issueLat=12 282opClass=FloatDiv 283opLat=12 284 285[system.cpu.fuPool.FUList3.opList2] 286type=OpDesc |
| 287eventq_index=0 |
|
| 263issueLat=24 264opClass=FloatSqrt 265opLat=24 266 267[system.cpu.fuPool.FUList4] 268type=FUDesc 269children=opList 270count=0 | 288issueLat=24 289opClass=FloatSqrt 290opLat=24 291 292[system.cpu.fuPool.FUList4] 293type=FUDesc 294children=opList 295count=0 |
| 296eventq_index=0 |
|
| 271opList=system.cpu.fuPool.FUList4.opList 272 273[system.cpu.fuPool.FUList4.opList] 274type=OpDesc | 297opList=system.cpu.fuPool.FUList4.opList 298 299[system.cpu.fuPool.FUList4.opList] 300type=OpDesc |
| 301eventq_index=0 |
|
| 275issueLat=1 276opClass=MemRead 277opLat=1 278 279[system.cpu.fuPool.FUList5] 280type=FUDesc 281children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 282count=4 | 302issueLat=1 303opClass=MemRead 304opLat=1 305 306[system.cpu.fuPool.FUList5] 307type=FUDesc 308children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 309count=4 |
| 310eventq_index=0 |
|
| 283opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 284 285[system.cpu.fuPool.FUList5.opList00] 286type=OpDesc | 311opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 312 313[system.cpu.fuPool.FUList5.opList00] 314type=OpDesc |
| 315eventq_index=0 |
|
| 287issueLat=1 288opClass=SimdAdd 289opLat=1 290 291[system.cpu.fuPool.FUList5.opList01] 292type=OpDesc | 316issueLat=1 317opClass=SimdAdd 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList01] 321type=OpDesc |
| 322eventq_index=0 |
|
| 293issueLat=1 294opClass=SimdAddAcc 295opLat=1 296 297[system.cpu.fuPool.FUList5.opList02] 298type=OpDesc | 323issueLat=1 324opClass=SimdAddAcc 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList02] 328type=OpDesc |
| 329eventq_index=0 |
|
| 299issueLat=1 300opClass=SimdAlu 301opLat=1 302 303[system.cpu.fuPool.FUList5.opList03] 304type=OpDesc | 330issueLat=1 331opClass=SimdAlu 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList03] 335type=OpDesc |
| 336eventq_index=0 |
|
| 305issueLat=1 306opClass=SimdCmp 307opLat=1 308 309[system.cpu.fuPool.FUList5.opList04] 310type=OpDesc | 337issueLat=1 338opClass=SimdCmp 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList04] 342type=OpDesc |
| 343eventq_index=0 |
|
| 311issueLat=1 312opClass=SimdCvt 313opLat=1 314 315[system.cpu.fuPool.FUList5.opList05] 316type=OpDesc | 344issueLat=1 345opClass=SimdCvt 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList05] 349type=OpDesc |
| 350eventq_index=0 |
|
| 317issueLat=1 318opClass=SimdMisc 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList06] 322type=OpDesc | 351issueLat=1 352opClass=SimdMisc 353opLat=1 354 355[system.cpu.fuPool.FUList5.opList06] 356type=OpDesc |
| 357eventq_index=0 |
|
| 323issueLat=1 324opClass=SimdMult 325opLat=1 326 327[system.cpu.fuPool.FUList5.opList07] 328type=OpDesc | 358issueLat=1 359opClass=SimdMult 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList07] 363type=OpDesc |
| 364eventq_index=0 |
|
| 329issueLat=1 330opClass=SimdMultAcc 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList08] 334type=OpDesc | 365issueLat=1 366opClass=SimdMultAcc 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList08] 370type=OpDesc |
| 371eventq_index=0 |
|
| 335issueLat=1 336opClass=SimdShift 337opLat=1 338 339[system.cpu.fuPool.FUList5.opList09] 340type=OpDesc | 372issueLat=1 373opClass=SimdShift 374opLat=1 375 376[system.cpu.fuPool.FUList5.opList09] 377type=OpDesc |
| 378eventq_index=0 |
|
| 341issueLat=1 342opClass=SimdShiftAcc 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList10] 346type=OpDesc | 379issueLat=1 380opClass=SimdShiftAcc 381opLat=1 382 383[system.cpu.fuPool.FUList5.opList10] 384type=OpDesc |
| 385eventq_index=0 |
|
| 347issueLat=1 348opClass=SimdSqrt 349opLat=1 350 351[system.cpu.fuPool.FUList5.opList11] 352type=OpDesc | 386issueLat=1 387opClass=SimdSqrt 388opLat=1 389 390[system.cpu.fuPool.FUList5.opList11] 391type=OpDesc |
| 392eventq_index=0 |
|
| 353issueLat=1 354opClass=SimdFloatAdd 355opLat=1 356 357[system.cpu.fuPool.FUList5.opList12] 358type=OpDesc | 393issueLat=1 394opClass=SimdFloatAdd 395opLat=1 396 397[system.cpu.fuPool.FUList5.opList12] 398type=OpDesc |
| 399eventq_index=0 |
|
| 359issueLat=1 360opClass=SimdFloatAlu 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList13] 364type=OpDesc | 400issueLat=1 401opClass=SimdFloatAlu 402opLat=1 403 404[system.cpu.fuPool.FUList5.opList13] 405type=OpDesc |
| 406eventq_index=0 |
|
| 365issueLat=1 366opClass=SimdFloatCmp 367opLat=1 368 369[system.cpu.fuPool.FUList5.opList14] 370type=OpDesc | 407issueLat=1 408opClass=SimdFloatCmp 409opLat=1 410 411[system.cpu.fuPool.FUList5.opList14] 412type=OpDesc |
| 413eventq_index=0 |
|
| 371issueLat=1 372opClass=SimdFloatCvt 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList15] 376type=OpDesc | 414issueLat=1 415opClass=SimdFloatCvt 416opLat=1 417 418[system.cpu.fuPool.FUList5.opList15] 419type=OpDesc |
| 420eventq_index=0 |
|
| 377issueLat=1 378opClass=SimdFloatDiv 379opLat=1 380 381[system.cpu.fuPool.FUList5.opList16] 382type=OpDesc | 421issueLat=1 422opClass=SimdFloatDiv 423opLat=1 424 425[system.cpu.fuPool.FUList5.opList16] 426type=OpDesc |
| 427eventq_index=0 |
|
| 383issueLat=1 384opClass=SimdFloatMisc 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList17] 388type=OpDesc | 428issueLat=1 429opClass=SimdFloatMisc 430opLat=1 431 432[system.cpu.fuPool.FUList5.opList17] 433type=OpDesc |
| 434eventq_index=0 |
|
| 389issueLat=1 390opClass=SimdFloatMult 391opLat=1 392 393[system.cpu.fuPool.FUList5.opList18] 394type=OpDesc | 435issueLat=1 436opClass=SimdFloatMult 437opLat=1 438 439[system.cpu.fuPool.FUList5.opList18] 440type=OpDesc |
| 441eventq_index=0 |
|
| 395issueLat=1 396opClass=SimdFloatMultAcc 397opLat=1 398 399[system.cpu.fuPool.FUList5.opList19] 400type=OpDesc | 442issueLat=1 443opClass=SimdFloatMultAcc 444opLat=1 445 446[system.cpu.fuPool.FUList5.opList19] 447type=OpDesc |
| 448eventq_index=0 |
|
| 401issueLat=1 402opClass=SimdFloatSqrt 403opLat=1 404 405[system.cpu.fuPool.FUList6] 406type=FUDesc 407children=opList 408count=0 | 449issueLat=1 450opClass=SimdFloatSqrt 451opLat=1 452 453[system.cpu.fuPool.FUList6] 454type=FUDesc 455children=opList 456count=0 |
| 457eventq_index=0 |
|
| 409opList=system.cpu.fuPool.FUList6.opList 410 411[system.cpu.fuPool.FUList6.opList] 412type=OpDesc | 458opList=system.cpu.fuPool.FUList6.opList 459 460[system.cpu.fuPool.FUList6.opList] 461type=OpDesc |
| 462eventq_index=0 |
|
| 413issueLat=1 414opClass=MemWrite 415opLat=1 416 417[system.cpu.fuPool.FUList7] 418type=FUDesc 419children=opList0 opList1 420count=4 | 463issueLat=1 464opClass=MemWrite 465opLat=1 466 467[system.cpu.fuPool.FUList7] 468type=FUDesc 469children=opList0 opList1 470count=4 |
| 471eventq_index=0 |
|
| 421opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 422 423[system.cpu.fuPool.FUList7.opList0] 424type=OpDesc | 472opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 473 474[system.cpu.fuPool.FUList7.opList0] 475type=OpDesc |
| 476eventq_index=0 |
|
| 425issueLat=1 426opClass=MemRead 427opLat=1 428 429[system.cpu.fuPool.FUList7.opList1] 430type=OpDesc | 477issueLat=1 478opClass=MemRead 479opLat=1 480 481[system.cpu.fuPool.FUList7.opList1] 482type=OpDesc |
| 483eventq_index=0 |
|
| 431issueLat=1 432opClass=MemWrite 433opLat=1 434 435[system.cpu.fuPool.FUList8] 436type=FUDesc 437children=opList 438count=1 | 484issueLat=1 485opClass=MemWrite 486opLat=1 487 488[system.cpu.fuPool.FUList8] 489type=FUDesc 490children=opList 491count=1 |
| 492eventq_index=0 |
|
| 439opList=system.cpu.fuPool.FUList8.opList 440 441[system.cpu.fuPool.FUList8.opList] 442type=OpDesc | 493opList=system.cpu.fuPool.FUList8.opList 494 495[system.cpu.fuPool.FUList8.opList] 496type=OpDesc |
| 497eventq_index=0 |
|
| 443issueLat=3 444opClass=IprAccess 445opLat=3 446 447[system.cpu.icache] 448type=BaseCache 449children=tags 450addr_ranges=0:18446744073709551615 451assoc=2 452clk_domain=system.cpu_clk_domain | 498issueLat=3 499opClass=IprAccess 500opLat=3 501 502[system.cpu.icache] 503type=BaseCache 504children=tags 505addr_ranges=0:18446744073709551615 506assoc=2 507clk_domain=system.cpu_clk_domain |
| 508eventq_index=0 |
|
| 453forward_snoops=true 454hit_latency=2 455is_top_level=true 456max_miss_count=0 457mshrs=4 458prefetch_on_access=false 459prefetcher=Null 460response_latency=2 --- 6 unchanged lines hidden (view full) --- 467cpu_side=system.cpu.icache_port 468mem_side=system.cpu.toL2Bus.slave[0] 469 470[system.cpu.icache.tags] 471type=LRU 472assoc=2 473block_size=64 474clk_domain=system.cpu_clk_domain | 509forward_snoops=true 510hit_latency=2 511is_top_level=true 512max_miss_count=0 513mshrs=4 514prefetch_on_access=false 515prefetcher=Null 516response_latency=2 --- 6 unchanged lines hidden (view full) --- 523cpu_side=system.cpu.icache_port 524mem_side=system.cpu.toL2Bus.slave[0] 525 526[system.cpu.icache.tags] 527type=LRU 528assoc=2 529block_size=64 530clk_domain=system.cpu_clk_domain |
| 531eventq_index=0 |
|
| 475hit_latency=2 476size=131072 477 478[system.cpu.interrupts] 479type=ArmInterrupts | 532hit_latency=2 533size=131072 534 535[system.cpu.interrupts] 536type=ArmInterrupts |
| 537eventq_index=0 |
|
| 480 481[system.cpu.isa] 482type=ArmISA | 538 539[system.cpu.isa] 540type=ArmISA |
| 541eventq_index=0 |
|
| 483fpsid=1090793632 484id_isar0=34607377 485id_isar1=34677009 486id_isar2=555950401 487id_isar3=17899825 488id_isar4=268501314 489id_isar5=0 490id_mmfr0=3 491id_mmfr1=0 492id_mmfr2=19070976 493id_mmfr3=4027589137 494id_pfr0=49 495id_pfr1=1 496midr=890224640 497 498[system.cpu.itb] 499type=ArmTLB 500children=walker | 542fpsid=1090793632 543id_isar0=34607377 544id_isar1=34677009 545id_isar2=555950401 546id_isar3=17899825 547id_isar4=268501314 548id_isar5=0 549id_mmfr0=3 550id_mmfr1=0 551id_mmfr2=19070976 552id_mmfr3=4027589137 553id_pfr0=49 554id_pfr1=1 555midr=890224640 556 557[system.cpu.itb] 558type=ArmTLB 559children=walker |
| 560eventq_index=0 |
|
| 501size=64 502walker=system.cpu.itb.walker 503 504[system.cpu.itb.walker] 505type=ArmTableWalker 506clk_domain=system.cpu_clk_domain | 561size=64 562walker=system.cpu.itb.walker 563 564[system.cpu.itb.walker] 565type=ArmTableWalker 566clk_domain=system.cpu_clk_domain |
| 567eventq_index=0 |
|
| 507num_squash_per_cycle=2 508sys=system 509port=system.cpu.toL2Bus.slave[2] 510 511[system.cpu.l2cache] 512type=BaseCache 513children=tags 514addr_ranges=0:18446744073709551615 515assoc=8 516clk_domain=system.cpu_clk_domain | 568num_squash_per_cycle=2 569sys=system 570port=system.cpu.toL2Bus.slave[2] 571 572[system.cpu.l2cache] 573type=BaseCache 574children=tags 575addr_ranges=0:18446744073709551615 576assoc=8 577clk_domain=system.cpu_clk_domain |
| 578eventq_index=0 |
|
| 517forward_snoops=true 518hit_latency=20 519is_top_level=false 520max_miss_count=0 521mshrs=20 522prefetch_on_access=false 523prefetcher=Null 524response_latency=20 --- 6 unchanged lines hidden (view full) --- 531cpu_side=system.cpu.toL2Bus.master[0] 532mem_side=system.membus.slave[1] 533 534[system.cpu.l2cache.tags] 535type=LRU 536assoc=8 537block_size=64 538clk_domain=system.cpu_clk_domain | 579forward_snoops=true 580hit_latency=20 581is_top_level=false 582max_miss_count=0 583mshrs=20 584prefetch_on_access=false 585prefetcher=Null 586response_latency=20 --- 6 unchanged lines hidden (view full) --- 593cpu_side=system.cpu.toL2Bus.master[0] 594mem_side=system.membus.slave[1] 595 596[system.cpu.l2cache.tags] 597type=LRU 598assoc=8 599block_size=64 600clk_domain=system.cpu_clk_domain |
| 601eventq_index=0 |
|
| 539hit_latency=20 540size=2097152 541 542[system.cpu.toL2Bus] 543type=CoherentBus 544clk_domain=system.cpu_clk_domain | 602hit_latency=20 603size=2097152 604 605[system.cpu.toL2Bus] 606type=CoherentBus 607clk_domain=system.cpu_clk_domain |
| 608eventq_index=0 |
|
| 545header_cycles=1 546system=system 547use_default_range=false 548width=32 549master=system.cpu.l2cache.cpu_side 550slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 551 552[system.cpu.tracer] 553type=ExeTracer | 609header_cycles=1 610system=system 611use_default_range=false 612width=32 613master=system.cpu.l2cache.cpu_side 614slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 615 616[system.cpu.tracer] 617type=ExeTracer |
| 618eventq_index=0 |
|
| 554 555[system.cpu.workload] 556type=LiveProcess 557cmd=twolf smred 558cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing 559egid=100 560env= 561errout=cerr 562euid=100 | 619 620[system.cpu.workload] 621type=LiveProcess 622cmd=twolf smred 623cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing 624egid=100 625env= 626errout=cerr 627euid=100 |
| 563executable=/dist/m5/cpu2000/binaries/arm/linux/twolf | 628eventq_index=0 629executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf |
| 564gid=100 565input=cin 566max_stack_size=67108864 567output=cout 568pid=100 569ppid=99 570simpoint=0 571system=system 572uid=100 573 574[system.cpu_clk_domain] 575type=SrcClockDomain 576clock=500 | 630gid=100 631input=cin 632max_stack_size=67108864 633output=cout 634pid=100 635ppid=99 636simpoint=0 637system=system 638uid=100 639 640[system.cpu_clk_domain] 641type=SrcClockDomain 642clock=500 |
| 643eventq_index=0 |
|
| 577voltage_domain=system.voltage_domain 578 579[system.membus] 580type=CoherentBus 581clk_domain=system.clk_domain | 644voltage_domain=system.voltage_domain 645 646[system.membus] 647type=CoherentBus 648clk_domain=system.clk_domain |
| 649eventq_index=0 |
|
| 582header_cycles=1 583system=system 584use_default_range=false 585width=8 586master=system.physmem.port 587slave=system.system_port system.cpu.l2cache.mem_side 588 589[system.physmem] 590type=SimpleDRAM 591activation_limit=4 592addr_mapping=RaBaChCo 593banks_per_rank=8 594burst_length=8 595channels=1 596clk_domain=system.clk_domain 597conf_table_reported=true 598device_bus_width=8 599device_rowbuffer_size=1024 600devices_per_rank=8 | 650header_cycles=1 651system=system 652use_default_range=false 653width=8 654master=system.physmem.port 655slave=system.system_port system.cpu.l2cache.mem_side 656 657[system.physmem] 658type=SimpleDRAM 659activation_limit=4 660addr_mapping=RaBaChCo 661banks_per_rank=8 662burst_length=8 663channels=1 664clk_domain=system.clk_domain 665conf_table_reported=true 666device_bus_width=8 667device_rowbuffer_size=1024 668devices_per_rank=8 |
| 669eventq_index=0 |
|
| 601in_addr_map=true 602mem_sched_policy=frfcfs 603null=false 604page_policy=open 605range=0:134217727 606ranks_per_channel=2 607read_buffer_size=32 608static_backend_latency=10000 609static_frontend_latency=10000 610tBURST=5000 611tCL=13750 | 670in_addr_map=true 671mem_sched_policy=frfcfs 672null=false 673page_policy=open 674range=0:134217727 675ranks_per_channel=2 676read_buffer_size=32 677static_backend_latency=10000 678static_frontend_latency=10000 679tBURST=5000 680tCL=13750 |
| 681tRAS=35000 |
|
| 612tRCD=13750 613tREFI=7800000 614tRFC=300000 615tRP=13750 | 682tRCD=13750 683tREFI=7800000 684tRFC=300000 685tRP=13750 |
| 686tRRD=6250 |
|
| 616tWTR=7500 617tXAW=40000 618write_buffer_size=32 | 687tWTR=7500 688tXAW=40000 689write_buffer_size=32 |
| 619write_thresh_perc=70 | 690write_high_thresh_perc=70 691write_low_thresh_perc=0 |
| 620port=system.membus.master[0] 621 622[system.voltage_domain] 623type=VoltageDomain | 692port=system.membus.master[0] 693 694[system.voltage_domain] 695type=VoltageDomain |
| 696eventq_index=0 |
|
| 624voltage=1.000000 625 | 697voltage=1.000000 698 |