| stats.txt (9797:9cd5f91e7a79) | stats.txt (9838:43d22d746e7a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026765 # Number of seconds simulated 4sim_ticks 26765004500 # Number of ticks simulated 5final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.026765 # Number of seconds simulated 4sim_ticks 26765004500 # Number of ticks simulated 5final_tick 26765004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 88779 # Simulator instruction rate (inst/s) 8host_op_rate 125988 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 33510752 # Simulator tick rate (ticks/s) 10host_mem_usage 255124 # Number of bytes of host memory used 11host_seconds 798.70 # Real time elapsed on the host | 7host_inst_rate 102307 # Simulator instruction rate (inst/s) 8host_op_rate 145187 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38617115 # Simulator tick rate (ticks/s) 10host_mem_usage 251228 # Number of bytes of host memory used 11host_seconds 693.09 # Real time elapsed on the host |
| 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 100626876 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7944704 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8242496 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 297792 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 297792 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5372160 # Number of bytes written to this memory --- 9 unchanged lines hidden (view full) --- 29system.physmem.bw_inst_read::cpu.inst 11126170 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 11126170 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 200715827 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 200715827 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 200715827 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 100626876 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 297792 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7944704 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8242496 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 297792 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 297792 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5372160 # Number of bytes written to this memory --- 9 unchanged lines hidden (view full) --- 29system.physmem.bw_inst_read::cpu.inst 11126170 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 11126170 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 200715827 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 200715827 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 200715827 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 11126170 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 296831783 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 508673780 # Total bandwidth to/from this memory (bytes/s) |
| 37system.physmem.readReqs 128790 # Total number of read requests seen 38system.physmem.writeReqs 83940 # Total number of write requests seen 39system.physmem.cpureqs 213051 # Reqs generatd by CPU via cache - shady | 37system.physmem.readReqs 128790 # Total number of read requests accepted by DRAM controller 38system.physmem.writeReqs 83940 # Total number of write requests accepted by DRAM controller 39system.physmem.readBursts 128790 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 40system.physmem.writeBursts 83940 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts |
| 40system.physmem.bytesRead 8242496 # Total number of bytes read from memory 41system.physmem.bytesWritten 5372160 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize() | 41system.physmem.bytesRead 8242496 # Total number of bytes read from memory 42system.physmem.bytesWritten 5372160 # Total number of bytes written to memory 43system.physmem.bytesConsumedRd 8242496 # bytesRead derated as per pkt->getSize() 44system.physmem.bytesConsumedWr 5372160 # bytesWritten derated as per pkt->getSize() |
| 44system.physmem.servicedByWrQ 3 # Number of read reqs serviced by write Q | 45system.physmem.servicedByWrQ 3 # Number of DRAM read bursts serviced by write Q |
| 45system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 8248 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 8159 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 8298 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 8449 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 8089 # Track reads on a per bank basis --- 255 unchanged lines hidden (view full) --- 308system.membus.throughput 508673780 # Throughput (bytes/s) 309system.membus.trans_dist::ReadReq 26538 # Transaction distribution 310system.membus.trans_dist::ReadResp 26537 # Transaction distribution 311system.membus.trans_dist::Writeback 83940 # Transaction distribution 312system.membus.trans_dist::UpgradeReq 321 # Transaction distribution 313system.membus.trans_dist::UpgradeResp 321 # Transaction distribution 314system.membus.trans_dist::ReadExReq 102252 # Transaction distribution 315system.membus.trans_dist::ReadExResp 102252 # Transaction distribution | 46system.physmem.neitherReadNorWrite 321 # Reqs where no action is needed 47system.physmem.perBankRdReqs::0 8146 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::1 8397 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::2 8248 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::3 8159 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::4 8298 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::5 8449 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::6 8089 # Track reads on a per bank basis --- 255 unchanged lines hidden (view full) --- 309system.membus.throughput 508673780 # Throughput (bytes/s) 310system.membus.trans_dist::ReadReq 26538 # Transaction distribution 311system.membus.trans_dist::ReadResp 26537 # Transaction distribution 312system.membus.trans_dist::Writeback 83940 # Transaction distribution 313system.membus.trans_dist::UpgradeReq 321 # Transaction distribution 314system.membus.trans_dist::UpgradeResp 321 # Transaction distribution 315system.membus.trans_dist::ReadExReq 102252 # Transaction distribution 316system.membus.trans_dist::ReadExResp 102252 # Transaction distribution |
| 316system.membus.pkt_count_system.cpu.l2cache.mem_side 342161 # Packet count per connected master and slave (bytes) 317system.membus.pkt_count 342161 # Packet count per connected master and slave (bytes) 318system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13614656 # Cumulative packet size per connected master and slave (bytes) 319system.membus.tot_pkt_size 13614656 # Cumulative packet size per connected master and slave (bytes) | 317system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 342161 # Packet count per connected master and slave (bytes) 318system.membus.pkt_count::total 342161 # Packet count per connected master and slave (bytes) 319system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13614656 # Cumulative packet size per connected master and slave (bytes) 320system.membus.tot_pkt_size::total 13614656 # Cumulative packet size per connected master and slave (bytes) |
| 320system.membus.data_through_bus 13614656 # Total data (bytes) 321system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 322system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks) 323system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) 324system.membus.respLayer1.occupancy 1207011429 # Layer occupancy (ticks) 325system.membus.respLayer1.utilization 4.5 # Layer utilization (%) 326system.cpu.branchPred.lookups 16635237 # Number of BP lookups 327system.cpu.branchPred.condPredicted 12768503 # Number of conditional branches predicted --- 312 unchanged lines hidden (view full) --- 640system.cpu.toL2Bus.throughput 771895107 # Throughput (bytes/s) 641system.cpu.toL2Bus.trans_dist::ReadReq 86668 # Transaction distribution 642system.cpu.toL2Bus.trans_dist::ReadResp 86666 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::Writeback 129110 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution | 321system.membus.data_through_bus 13614656 # Total data (bytes) 322system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 323system.membus.reqLayer0.occupancy 935941500 # Layer occupancy (ticks) 324system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) 325system.membus.respLayer1.occupancy 1207011429 # Layer occupancy (ticks) 326system.membus.respLayer1.utilization 4.5 # Layer utilization (%) 327system.cpu.branchPred.lookups 16635237 # Number of BP lookups 328system.cpu.branchPred.condPredicted 12768503 # Number of conditional branches predicted --- 312 unchanged lines hidden (view full) --- 641system.cpu.toL2Bus.throughput 771895107 # Throughput (bytes/s) 642system.cpu.toL2Bus.trans_dist::ReadReq 86668 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::ReadResp 86666 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::Writeback 129110 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::UpgradeReq 336 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::UpgradeResp 336 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::ReadExReq 107033 # Transaction distribution 648system.cpu.toL2Bus.trans_dist::ReadExResp 107033 # Transaction distribution |
| 648system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 61963 # Packet count per connected master and slave (bytes) 649system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454719 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.pkt_count 516682 # Packet count per connected master and slave (bytes) 651system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1966784 # Cumulative packet size per connected master and slave (bytes) 652system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18660992 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.tot_pkt_size 20627776 # Cumulative packet size per connected master and slave (bytes) | 649system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 61963 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 454719 # Packet count per connected master and slave (bytes) 651system.cpu.toL2Bus.pkt_count::total 516682 # Packet count per connected master and slave (bytes) 652system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1966784 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18660992 # Cumulative packet size per connected master and slave (bytes) 654system.cpu.toL2Bus.tot_pkt_size::total 20627776 # Cumulative packet size per connected master and slave (bytes) |
| 654system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes) 655system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes) 656system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks) 657system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 658system.cpu.toL2Bus.respLayer0.occupancy 47827231 # Layer occupancy (ticks) 659system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 660system.cpu.toL2Bus.respLayer1.occupancy 262412261 # Layer occupancy (ticks) 661system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) | 655system.cpu.toL2Bus.data_through_bus 20627776 # Total data (bytes) 656system.cpu.toL2Bus.snoop_data_through_bus 32000 # Total snoop data (bytes) 657system.cpu.toL2Bus.reqLayer0.occupancy 290686995 # Layer occupancy (ticks) 658system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 659system.cpu.toL2Bus.respLayer0.occupancy 47827231 # Layer occupancy (ticks) 660system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 661system.cpu.toL2Bus.respLayer1.occupancy 262412261 # Layer occupancy (ticks) 662system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) |
| 662system.cpu.icache.tags.replacements 28871 # number of replacements 663system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use 664system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks. 665system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks. 666system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks. 667system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 668system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor 669system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy 670system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy | 663system.cpu.icache.tags.replacements 28871 # number of replacements 664system.cpu.icache.tags.tagsinuse 1809.449271 # Cycle average of tags in use 665system.cpu.icache.tags.total_refs 11651662 # Total number of references to valid blocks. 666system.cpu.icache.tags.sampled_refs 30904 # Sample count of references to valid blocks. 667system.cpu.icache.tags.avg_refs 377.027634 # Average number of references to valid blocks. 668system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 669system.cpu.icache.tags.occ_blocks::cpu.inst 1809.449271 # Average occupied blocks per requestor 670system.cpu.icache.tags.occ_percent::cpu.inst 0.883520 # Average percentage of cache occupancy 671system.cpu.icache.tags.occ_percent::total 0.883520 # Average percentage of cache occupancy |
| 671system.cpu.icache.ReadReq_hits::cpu.inst 11651673 # number of ReadReq hits 672system.cpu.icache.ReadReq_hits::total 11651673 # number of ReadReq hits 673system.cpu.icache.demand_hits::cpu.inst 11651673 # number of demand (read+write) hits 674system.cpu.icache.demand_hits::total 11651673 # number of demand (read+write) hits 675system.cpu.icache.overall_hits::cpu.inst 11651673 # number of overall hits 676system.cpu.icache.overall_hits::total 11651673 # number of overall hits 677system.cpu.icache.ReadReq_misses::cpu.inst 34991 # number of ReadReq misses 678system.cpu.icache.ReadReq_misses::total 34991 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 738system.cpu.icache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses 739system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21904.401543 # average ReadReq mshr miss latency 740system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21904.401543 # average ReadReq mshr miss latency 741system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency 742system.cpu.icache.demand_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency 743system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency 744system.cpu.icache.overall_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency 745system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 672system.cpu.icache.ReadReq_hits::cpu.inst 11651673 # number of ReadReq hits 673system.cpu.icache.ReadReq_hits::total 11651673 # number of ReadReq hits 674system.cpu.icache.demand_hits::cpu.inst 11651673 # number of demand (read+write) hits 675system.cpu.icache.demand_hits::total 11651673 # number of demand (read+write) hits 676system.cpu.icache.overall_hits::cpu.inst 11651673 # number of overall hits 677system.cpu.icache.overall_hits::total 11651673 # number of overall hits 678system.cpu.icache.ReadReq_misses::cpu.inst 34991 # number of ReadReq misses 679system.cpu.icache.ReadReq_misses::total 34991 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 739system.cpu.icache.overall_mshr_miss_rate::total 0.002672 # mshr miss rate for overall accesses 740system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21904.401543 # average ReadReq mshr miss latency 741system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21904.401543 # average ReadReq mshr miss latency 742system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency 743system.cpu.icache.demand_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency 744system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21904.401543 # average overall mshr miss latency 745system.cpu.icache.overall_avg_mshr_miss_latency::total 21904.401543 # average overall mshr miss latency 746system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 746system.cpu.l2cache.tags.replacements 95660 # number of replacements 747system.cpu.l2cache.tags.tagsinuse 29916.504006 # Cycle average of tags in use 748system.cpu.l2cache.tags.total_refs 88398 # Total number of references to valid blocks. 749system.cpu.l2cache.tags.sampled_refs 126774 # Sample count of references to valid blocks. 750system.cpu.l2cache.tags.avg_refs 0.697288 # Average number of references to valid blocks. 751system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 747system.cpu.l2cache.tags.replacements 95660 # number of replacements 748system.cpu.l2cache.tags.tagsinuse 29916.504006 # Cycle average of tags in use 749system.cpu.l2cache.tags.total_refs 88398 # Total number of references to valid blocks. 750system.cpu.l2cache.tags.sampled_refs 126774 # Sample count of references to valid blocks. 751system.cpu.l2cache.tags.avg_refs 0.697288 # Average number of references to valid blocks. 752system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 752system.cpu.l2cache.tags.occ_blocks::writebacks 26705.369214 # Average occupied blocks per requestor | 753system.cpu.l2cache.tags.occ_blocks::writebacks 26705.369214 # Average occupied blocks per requestor |
| 753system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.053749 # Average occupied blocks per requestor 754system.cpu.l2cache.tags.occ_blocks::cpu.data 1845.081043 # Average occupied blocks per requestor | 754system.cpu.l2cache.tags.occ_blocks::cpu.inst 1366.053749 # Average occupied blocks per requestor 755system.cpu.l2cache.tags.occ_blocks::cpu.data 1845.081043 # Average occupied blocks per requestor |
| 755system.cpu.l2cache.tags.occ_percent::writebacks 0.814983 # Average percentage of cache occupancy 756system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041689 # Average percentage of cache occupancy 757system.cpu.l2cache.tags.occ_percent::cpu.data 0.056307 # Average percentage of cache occupancy | 756system.cpu.l2cache.tags.occ_percent::writebacks 0.814983 # Average percentage of cache occupancy 757system.cpu.l2cache.tags.occ_percent::cpu.inst 0.041689 # Average percentage of cache occupancy 758system.cpu.l2cache.tags.occ_percent::cpu.data 0.056307 # Average percentage of cache occupancy |
| 758system.cpu.l2cache.tags.occ_percent::total 0.912979 # Average percentage of cache occupancy | 759system.cpu.l2cache.tags.occ_percent::total 0.912979 # Average percentage of cache occupancy |
| 759system.cpu.l2cache.ReadReq_hits::cpu.inst 26062 # number of ReadReq hits 760system.cpu.l2cache.ReadReq_hits::cpu.data 33492 # number of ReadReq hits 761system.cpu.l2cache.ReadReq_hits::total 59554 # number of ReadReq hits 762system.cpu.l2cache.Writeback_hits::writebacks 129110 # number of Writeback hits 763system.cpu.l2cache.Writeback_hits::total 129110 # number of Writeback hits 764system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits 765system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits 766system.cpu.l2cache.ReadExReq_hits::cpu.data 4780 # number of ReadExReq hits --- 138 unchanged lines hidden (view full) --- 905system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69414.584423 # average ReadExReq mshr miss latency 906system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency 907system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency 908system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency 909system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency 910system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency 911system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency 912system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 760system.cpu.l2cache.ReadReq_hits::cpu.inst 26062 # number of ReadReq hits 761system.cpu.l2cache.ReadReq_hits::cpu.data 33492 # number of ReadReq hits 762system.cpu.l2cache.ReadReq_hits::total 59554 # number of ReadReq hits 763system.cpu.l2cache.Writeback_hits::writebacks 129110 # number of Writeback hits 764system.cpu.l2cache.Writeback_hits::total 129110 # number of Writeback hits 765system.cpu.l2cache.UpgradeReq_hits::cpu.data 16 # number of UpgradeReq hits 766system.cpu.l2cache.UpgradeReq_hits::total 16 # number of UpgradeReq hits 767system.cpu.l2cache.ReadExReq_hits::cpu.data 4780 # number of ReadExReq hits --- 138 unchanged lines hidden (view full) --- 906system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69414.584423 # average ReadExReq mshr miss latency 907system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency 908system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency 909system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency 910system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71300.343864 # average overall mshr miss latency 911system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69986.508974 # average overall mshr miss latency 912system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70033.975596 # average overall mshr miss latency 913system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 913system.cpu.dcache.tags.replacements 158372 # number of replacements 914system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use 915system.cpu.dcache.tags.total_refs 44374327 # Total number of references to valid blocks. 916system.cpu.dcache.tags.sampled_refs 162468 # Sample count of references to valid blocks. 917system.cpu.dcache.tags.avg_refs 273.126566 # Average number of references to valid blocks. 918system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit. 919system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor 920system.cpu.dcache.tags.occ_percent::cpu.data 0.993506 # Average percentage of cache occupancy 921system.cpu.dcache.tags.occ_percent::total 0.993506 # Average percentage of cache occupancy | 914system.cpu.dcache.tags.replacements 158372 # number of replacements 915system.cpu.dcache.tags.tagsinuse 4069.400137 # Cycle average of tags in use 916system.cpu.dcache.tags.total_refs 44374327 # Total number of references to valid blocks. 917system.cpu.dcache.tags.sampled_refs 162468 # Sample count of references to valid blocks. 918system.cpu.dcache.tags.avg_refs 273.126566 # Average number of references to valid blocks. 919system.cpu.dcache.tags.warmup_cycle 354003250 # Cycle when the warmup percentage was hit. 920system.cpu.dcache.tags.occ_blocks::cpu.data 4069.400137 # Average occupied blocks per requestor 921system.cpu.dcache.tags.occ_percent::cpu.data 0.993506 # Average percentage of cache occupancy 922system.cpu.dcache.tags.occ_percent::total 0.993506 # Average percentage of cache occupancy |
| 922system.cpu.dcache.ReadReq_hits::cpu.data 26075013 # number of ReadReq hits 923system.cpu.dcache.ReadReq_hits::total 26075013 # number of ReadReq hits 924system.cpu.dcache.WriteReq_hits::cpu.data 18266800 # number of WriteReq hits 925system.cpu.dcache.WriteReq_hits::total 18266800 # number of WriteReq hits 926system.cpu.dcache.LoadLockedReq_hits::cpu.data 15987 # number of LoadLockedReq hits 927system.cpu.dcache.LoadLockedReq_hits::total 15987 # number of LoadLockedReq hits 928system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 929system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits --- 111 unchanged lines hidden --- | 923system.cpu.dcache.ReadReq_hits::cpu.data 26075013 # number of ReadReq hits 924system.cpu.dcache.ReadReq_hits::total 26075013 # number of ReadReq hits 925system.cpu.dcache.WriteReq_hits::cpu.data 18266800 # number of WriteReq hits 926system.cpu.dcache.WriteReq_hits::total 18266800 # number of WriteReq hits 927system.cpu.dcache.LoadLockedReq_hits::cpu.data 15987 # number of LoadLockedReq hits 928system.cpu.dcache.LoadLockedReq_hits::total 15987 # number of LoadLockedReq hits 929system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 930system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits --- 111 unchanged lines hidden --- |