| stats.txt (9636:531a176f863d) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.025535 # Number of seconds simulated 4sim_ticks 25534556000 # Number of ticks simulated 5final_tick 25534556000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.026649 # Number of seconds simulated 4sim_ticks 26649062500 # Number of ticks simulated 5final_tick 26649062500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 124211 # Simulator instruction rate (inst/s) 8host_op_rate 176271 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44729688 # Simulator tick rate (ticks/s) 10host_mem_usage 254184 # Number of bytes of host memory used 11host_seconds 570.86 # Real time elapsed on the host | 7host_inst_rate 95593 # Simulator instruction rate (inst/s) 8host_op_rate 135659 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 35926621 # Simulator tick rate (ticks/s) 10host_mem_usage 255136 # Number of bytes of host memory used 11host_seconds 741.76 # Real time elapsed on the host |
| 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 100626876 # Number of ops (including micro ops) simulated | 12sim_insts 70907629 # Number of instructions simulated 13sim_ops 100626876 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 297536 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7943488 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8241024 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 297536 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 297536 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5372480 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5372480 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 4649 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 124117 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 128766 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 83945 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 83945 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 11652288 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 311087767 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 322740055 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 11652288 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 11652288 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 210400369 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 210400369 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 210400369 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 11652288 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 311087767 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 533140424 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 128767 # Total number of read requests seen 38system.physmem.writeReqs 83945 # Total number of write requests seen 39system.physmem.cpureqs 213037 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 8241024 # Total number of bytes read from memory 41system.physmem.bytesWritten 5372480 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 8241024 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 5372480 # bytesWritten derated as per pkt->getSize() | 14system.physmem.bytes_read::cpu.inst 298304 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7942464 # Number of bytes read from this memory 16system.physmem.bytes_read::total 8240768 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 298304 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 298304 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 5372800 # Number of bytes written to this memory 20system.physmem.bytes_written::total 5372800 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 4661 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 124101 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 128762 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 83950 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 83950 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 11193790 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 298039152 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 309232942 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 11193790 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 11193790 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 201613096 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 201613096 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 201613096 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 11193790 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 298039152 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 510846038 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 128763 # Total number of read requests seen 38system.physmem.writeReqs 83950 # Total number of write requests seen 39system.physmem.cpureqs 213025 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 8240768 # Total number of bytes read from memory 41system.physmem.bytesWritten 5372800 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 8240768 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 5372800 # bytesWritten derated as per pkt->getSize() |
| 44system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q | 44system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q |
| 45system.physmem.neitherReadNorWrite 325 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 7974 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 8181 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 8060 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 8163 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 8166 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 8116 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 8007 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 8045 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 8002 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 7985 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 7994 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 8125 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 8030 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 7980 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 7988 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 7949 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 5143 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 5260 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 5208 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 5207 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 5324 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 5374 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 5324 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 5328 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 5262 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 5276 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 5312 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 5351 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 5167 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 5124 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 5132 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 5153 # Track writes on a per bank basis | 45system.physmem.neitherReadNorWrite 312 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 8141 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 8383 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 8250 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 8168 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 8300 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 8450 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 8090 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 7962 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 8062 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 7609 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 7789 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 7813 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 7880 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 7885 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 7974 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 8005 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 5180 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 5377 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 5289 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 5158 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 5268 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 5519 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 5208 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 5049 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 5031 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 5089 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 5253 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 5145 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 5343 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 5363 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 5451 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 5227 # Track writes on a per bank basis |
| 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 80system.physmem.totGap 25534539500 # Total gap between requests | 80system.physmem.totGap 26649044000 # Total gap between requests |
| 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes | 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 87system.physmem.readPktSize::6 128767 # Categorize read packet sizes | 87system.physmem.readPktSize::6 128763 # Categorize read packet sizes |
| 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes | 88system.physmem.writePktSize::0 0 # Categorize write packet sizes 89system.physmem.writePktSize::1 0 # Categorize write packet sizes 90system.physmem.writePktSize::2 0 # Categorize write packet sizes 91system.physmem.writePktSize::3 0 # Categorize write packet sizes 92system.physmem.writePktSize::4 0 # Categorize write packet sizes 93system.physmem.writePktSize::5 0 # Categorize write packet sizes |
| 94system.physmem.writePktSize::6 83945 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 70152 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 56460 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 2075 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 64 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 14 # What read queue length does an incoming req see | 94system.physmem.writePktSize::6 83950 # Categorize write packet sizes 95system.physmem.rdQLenPdf::0 75538 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::1 51656 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::2 1500 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::3 60 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 100system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 119system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 127system.physmem.wrQLenPdf::0 3544 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 3638 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 3647 # What write queue length does an incoming req see | 127system.physmem.wrQLenPdf::0 3572 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::1 3647 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::2 3648 # What write queue length does an incoming req see |
| 130system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see | 130system.physmem.wrQLenPdf::3 3649 # What write queue length does an incoming req see |
| 131system.physmem.wrQLenPdf::4 3650 # What write queue length does an incoming req see | 131system.physmem.wrQLenPdf::4 3649 # What write queue length does an incoming req see |
| 132system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see | 132system.physmem.wrQLenPdf::5 3650 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::6 3650 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::7 3650 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::8 3650 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::9 3650 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::10 3650 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::11 3650 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::12 3650 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::13 3650 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::14 3650 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::15 3650 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::16 3650 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::17 3650 # What write queue length does an incoming req see |
| 145system.physmem.wrQLenPdf::18 3649 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 3649 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 3649 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 3649 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 3649 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 106 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 12 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see | 145system.physmem.wrQLenPdf::18 3650 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::19 3650 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::20 3650 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::21 3650 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::22 3650 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::23 78 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::24 3 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see |
| 153system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see | 153system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see |
| 154system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see | 154system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see |
| 155system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 155system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 159system.physmem.totQLat 3209361000 # Total cycles spent in queuing delays 160system.physmem.totMemAccLat 5253486000 # Sum of mem lat for all requests 161system.physmem.totBusLat 643825000 # Total cycles spent in databus access 162system.physmem.totBankLat 1400300000 # Total cycles spent in bank access 163system.physmem.avgQLat 24924.17 # Average queueing delay per request 164system.physmem.avgBankLat 10874.85 # Average bank access latency per request 165system.physmem.avgBusLat 5000.00 # Average bus latency per request 166system.physmem.avgMemAccLat 40799.02 # Average memory access latency 167system.physmem.avgRdBW 322.74 # Average achieved read bandwidth in MB/s 168system.physmem.avgWrBW 210.40 # Average achieved write bandwidth in MB/s 169system.physmem.avgConsumedRdBW 322.74 # Average consumed read bandwidth in MB/s 170system.physmem.avgConsumedWrBW 210.40 # Average consumed write bandwidth in MB/s | 159system.physmem.bytesPerActivate::samples 34891 # Bytes accessed per row activation 160system.physmem.bytesPerActivate::mean 390.104497 # Bytes accessed per row activation 161system.physmem.bytesPerActivate::gmean 179.978164 # Bytes accessed per row activation 162system.physmem.bytesPerActivate::stdev 858.430673 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::64-65 13421 38.47% 38.47% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::128-129 5383 15.43% 53.89% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::192-193 3065 8.78% 62.68% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::256-257 2226 6.38% 69.06% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::320-321 1625 4.66% 73.72% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::384-385 1388 3.98% 77.69% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::448-449 1071 3.07% 80.76% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::512-513 870 2.49% 83.26% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::576-577 590 1.69% 84.95% # Bytes accessed per row activation 172system.physmem.bytesPerActivate::640-641 488 1.40% 86.35% # Bytes accessed per row activation 173system.physmem.bytesPerActivate::704-705 448 1.28% 87.63% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::768-769 588 1.69% 89.32% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::832-833 296 0.85% 90.16% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::896-897 306 0.88% 91.04% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::960-961 186 0.53% 91.57% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::1024-1025 205 0.59% 92.16% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::1088-1089 126 0.36% 92.52% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::1152-1153 210 0.60% 93.12% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1216-1217 103 0.30% 93.42% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1280-1281 233 0.67% 94.09% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1344-1345 114 0.33% 94.41% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1408-1409 336 0.96% 95.38% # Bytes accessed per row activation 185system.physmem.bytesPerActivate::1472-1473 140 0.40% 95.78% # Bytes accessed per row activation 186system.physmem.bytesPerActivate::1536-1537 305 0.87% 96.65% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1600-1601 63 0.18% 96.83% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1664-1665 139 0.40% 97.23% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1728-1729 46 0.13% 97.36% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1792-1793 83 0.24% 97.60% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1856-1857 24 0.07% 97.67% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1920-1921 56 0.16% 97.83% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1984-1985 22 0.06% 97.89% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::2048-2049 58 0.17% 98.06% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::2112-2113 11 0.03% 98.09% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::2176-2177 27 0.08% 98.17% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2240-2241 19 0.05% 98.22% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2304-2305 23 0.07% 98.29% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2368-2369 10 0.03% 98.32% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2432-2433 17 0.05% 98.37% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2496-2497 8 0.02% 98.39% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2560-2561 14 0.04% 98.43% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2624-2625 16 0.05% 98.48% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2688-2689 16 0.05% 98.52% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2752-2753 9 0.03% 98.55% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2816-2817 15 0.04% 98.59% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2880-2881 9 0.03% 98.62% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2944-2945 7 0.02% 98.64% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::3008-3009 7 0.02% 98.66% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::3072-3073 12 0.03% 98.69% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::3136-3137 4 0.01% 98.70% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3200-3201 11 0.03% 98.73% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3264-3265 7 0.02% 98.75% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3328-3329 7 0.02% 98.77% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3392-3393 3 0.01% 98.78% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3456-3457 9 0.03% 98.81% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3520-3521 3 0.01% 98.82% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3584-3585 7 0.02% 98.84% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3648-3649 3 0.01% 98.84% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3712-3713 3 0.01% 98.85% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3776-3777 2 0.01% 98.86% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3840-3841 7 0.02% 98.88% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3904-3905 2 0.01% 98.89% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3968-3969 5 0.01% 98.90% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::4032-4033 2 0.01% 98.91% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::4096-4097 4 0.01% 98.92% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::4160-4161 1 0.00% 98.92% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4224-4225 3 0.01% 98.93% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4288-4289 2 0.01% 98.93% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4352-4353 7 0.02% 98.95% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4416-4417 2 0.01% 98.96% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4480-4481 4 0.01% 98.97% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4544-4545 1 0.00% 98.97% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4608-4609 3 0.01% 98.98% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4672-4673 1 0.00% 98.99% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4736-4737 3 0.01% 98.99% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4800-4801 4 0.01% 99.01% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4864-4865 4 0.01% 99.02% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4992-4993 4 0.01% 99.03% # Bytes accessed per row activation 240system.physmem.bytesPerActivate::5056-5057 1 0.00% 99.03% # Bytes accessed per row activation 241system.physmem.bytesPerActivate::5120-5121 3 0.01% 99.04% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::5184-5185 4 0.01% 99.05% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::5248-5249 2 0.01% 99.06% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5312-5313 2 0.01% 99.06% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5376-5377 4 0.01% 99.07% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5440-5441 1 0.00% 99.08% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5504-5505 1 0.00% 99.08% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5568-5569 7 0.02% 99.10% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5632-5633 1 0.00% 99.10% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5696-5697 2 0.01% 99.11% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5760-5761 2 0.01% 99.11% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5888-5889 3 0.01% 99.12% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::6016-6017 2 0.01% 99.13% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::6080-6081 1 0.00% 99.13% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::6144-6145 3 0.01% 99.14% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::6208-6209 4 0.01% 99.15% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::6272-6273 2 0.01% 99.16% # Bytes accessed per row activation 258system.physmem.bytesPerActivate::6336-6337 2 0.01% 99.16% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::6400-6401 3 0.01% 99.17% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6464-6465 3 0.01% 99.18% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6528-6529 3 0.01% 99.19% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6592-6593 3 0.01% 99.20% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6656-6657 3 0.01% 99.21% # Bytes accessed per row activation 264system.physmem.bytesPerActivate::6784-6785 2 0.01% 99.21% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.21% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6912-6913 2 0.01% 99.22% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6976-6977 2 0.01% 99.23% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::7040-7041 1 0.00% 99.23% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::7168-7169 1 0.00% 99.23% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::7232-7233 2 0.01% 99.24% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::7296-7297 2 0.01% 99.24% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::7360-7361 1 0.00% 99.25% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.25% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::7488-7489 3 0.01% 99.26% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::7552-7553 2 0.01% 99.26% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7616-7617 4 0.01% 99.27% # Bytes accessed per row activation 277system.physmem.bytesPerActivate::7680-7681 1 0.00% 99.28% # Bytes accessed per row activation 278system.physmem.bytesPerActivate::7744-7745 1 0.00% 99.28% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7808-7809 2 0.01% 99.29% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7872-7873 2 0.01% 99.29% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7936-7937 2 0.01% 99.30% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::8000-8001 1 0.00% 99.30% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::8064-8065 3 0.01% 99.31% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::8128-8129 3 0.01% 99.32% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::8192-8193 238 0.68% 100.00% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::total 34891 # Bytes accessed per row activation 287system.physmem.totQLat 2799338750 # Total cycles spent in queuing delays 288system.physmem.totMemAccLat 4801886250 # Sum of mem lat for all requests 289system.physmem.totBusLat 643800000 # Total cycles spent in databus access 290system.physmem.totBankLat 1358747500 # Total cycles spent in bank access 291system.physmem.avgQLat 21740.58 # Average queueing delay per request 292system.physmem.avgBankLat 10552.48 # Average bank access latency per request 293system.physmem.avgBusLat 4999.96 # Average bus latency per request 294system.physmem.avgMemAccLat 37293.02 # Average memory access latency 295system.physmem.avgRdBW 309.23 # Average achieved read bandwidth in MB/s 296system.physmem.avgWrBW 201.61 # Average achieved write bandwidth in MB/s 297system.physmem.avgConsumedRdBW 309.23 # Average consumed read bandwidth in MB/s 298system.physmem.avgConsumedWrBW 201.61 # Average consumed write bandwidth in MB/s |
| 171system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 299system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 172system.physmem.busUtil 4.17 # Data bus utilization in percentage 173system.physmem.avgRdQLen 0.21 # Average read queue length over time 174system.physmem.avgWrQLen 9.90 # Average write queue length over time 175system.physmem.readRowHits 116738 # Number of row buffer hits during reads 176system.physmem.writeRowHits 52892 # Number of row buffer hits during writes 177system.physmem.readRowHitRate 90.66 # Row buffer hit rate for reads 178system.physmem.writeRowHitRate 63.01 # Row buffer hit rate for writes 179system.physmem.avgGap 120042.78 # Average gap between requests 180system.cpu.branchPred.lookups 16612549 # Number of BP lookups 181system.cpu.branchPred.condPredicted 12751503 # Number of conditional branches predicted 182system.cpu.branchPred.condIncorrect 599939 # Number of conditional branches incorrect 183system.cpu.branchPred.BTBLookups 10534593 # Number of BTB lookups 184system.cpu.branchPred.BTBHits 7757405 # Number of BTB hits | 300system.physmem.busUtil 3.99 # Data bus utilization in percentage 301system.physmem.avgRdQLen 0.18 # Average read queue length over time 302system.physmem.avgWrQLen 10.01 # Average write queue length over time 303system.physmem.readRowHits 120254 # Number of row buffer hits during reads 304system.physmem.writeRowHits 57565 # Number of row buffer hits during writes 305system.physmem.readRowHitRate 93.39 # Row buffer hit rate for reads 306system.physmem.writeRowHitRate 68.57 # Row buffer hit rate for writes 307system.physmem.avgGap 125281.69 # Average gap between requests 308system.membus.throughput 510846038 # Throughput (bytes/s) 309system.membus.trans_dist::ReadReq 26509 # Transaction distribution 310system.membus.trans_dist::ReadResp 26508 # Transaction distribution 311system.membus.trans_dist::Writeback 83950 # Transaction distribution 312system.membus.trans_dist::UpgradeReq 312 # Transaction distribution 313system.membus.trans_dist::UpgradeResp 312 # Transaction distribution 314system.membus.trans_dist::ReadExReq 102254 # Transaction distribution 315system.membus.trans_dist::ReadExResp 102254 # Transaction distribution 316system.membus.pkt_count_system.cpu.l2cache.mem_side 342099 # Packet count per connected master and slave (bytes) 317system.membus.pkt_count 342099 # Packet count per connected master and slave (bytes) 318system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 13613568 # Cumulative packet size per connected master and slave (bytes) 319system.membus.tot_pkt_size 13613568 # Cumulative packet size per connected master and slave (bytes) 320system.membus.data_through_bus 13613568 # Total data (bytes) 321system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 322system.membus.reqLayer0.occupancy 926784500 # Layer occupancy (ticks) 323system.membus.reqLayer0.utilization 3.5 # Layer utilization (%) 324system.membus.respLayer1.occupancy 1200135938 # Layer occupancy (ticks) 325system.membus.respLayer1.utilization 4.5 # Layer utilization (%) 326system.cpu.branchPred.lookups 16620839 # Number of BP lookups 327system.cpu.branchPred.condPredicted 12757336 # Number of conditional branches predicted 328system.cpu.branchPred.condIncorrect 602395 # Number of conditional branches incorrect 329system.cpu.branchPred.BTBLookups 10635009 # Number of BTB lookups 330system.cpu.branchPred.BTBHits 7765773 # Number of BTB hits |
| 185system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 331system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 186system.cpu.branchPred.BTBHitPct 73.637444 # BTB Hit Percentage 187system.cpu.branchPred.usedRAS 1822464 # Number of times the RAS was used to get a target. 188system.cpu.branchPred.RASInCorrect 113740 # Number of incorrect RAS predictions. | 332system.cpu.branchPred.BTBHitPct 73.020841 # BTB Hit Percentage 333system.cpu.branchPred.usedRAS 1824331 # Number of times the RAS was used to get a target. 334system.cpu.branchPred.RASInCorrect 113161 # Number of incorrect RAS predictions. |
| 189system.cpu.dtb.inst_hits 0 # ITB inst hits 190system.cpu.dtb.inst_misses 0 # ITB inst misses 191system.cpu.dtb.read_hits 0 # DTB read hits 192system.cpu.dtb.read_misses 0 # DTB read misses 193system.cpu.dtb.write_hits 0 # DTB write hits 194system.cpu.dtb.write_misses 0 # DTB write misses 195system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 196system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 224system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 225system.cpu.itb.read_accesses 0 # DTB read accesses 226system.cpu.itb.write_accesses 0 # DTB write accesses 227system.cpu.itb.inst_accesses 0 # ITB inst accesses 228system.cpu.itb.hits 0 # DTB hits 229system.cpu.itb.misses 0 # DTB misses 230system.cpu.itb.accesses 0 # DTB accesses 231system.cpu.workload.num_syscalls 1946 # Number of system calls | 335system.cpu.dtb.inst_hits 0 # ITB inst hits 336system.cpu.dtb.inst_misses 0 # ITB inst misses 337system.cpu.dtb.read_hits 0 # DTB read hits 338system.cpu.dtb.read_misses 0 # DTB read misses 339system.cpu.dtb.write_hits 0 # DTB write hits 340system.cpu.dtb.write_misses 0 # DTB write misses 341system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 342system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 370system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 371system.cpu.itb.read_accesses 0 # DTB read accesses 372system.cpu.itb.write_accesses 0 # DTB write accesses 373system.cpu.itb.inst_accesses 0 # ITB inst accesses 374system.cpu.itb.hits 0 # DTB hits 375system.cpu.itb.misses 0 # DTB misses 376system.cpu.itb.accesses 0 # DTB accesses 377system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 232system.cpu.numCycles 51069113 # number of cpu cycles simulated | 378system.cpu.numCycles 53298126 # number of cpu cycles simulated |
| 233system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 234system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 379system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 380system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 235system.cpu.fetch.icacheStallCycles 12514697 # Number of cycles fetch is stalled on an Icache miss 236system.cpu.fetch.Insts 85141272 # Number of instructions fetch has processed 237system.cpu.fetch.Branches 16612549 # Number of branches that fetch encountered 238system.cpu.fetch.predictedBranches 9579869 # Number of branches that fetch has predicted taken 239system.cpu.fetch.Cycles 21174766 # Number of cycles fetch has run and was not squashing or blocked 240system.cpu.fetch.SquashCycles 2353264 # Number of cycles fetch has spent squashing 241system.cpu.fetch.BlockedCycles 10532727 # Number of cycles fetch has spent blocked 242system.cpu.fetch.MiscStallCycles 68 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 243system.cpu.fetch.PendingTrapStallCycles 498 # Number of stall cycles due to pending traps 244system.cpu.fetch.IcacheWaitRetryStallCycles 40 # Number of stall cycles due to full MSHR 245system.cpu.fetch.CacheLines 11663165 # Number of cache lines fetched 246system.cpu.fetch.IcacheSquashes 178973 # Number of outstanding Icache misses that were squashed 247system.cpu.fetch.rateDist::samples 45949088 # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::mean 2.594403 # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::stdev 3.336122 # Number of instructions fetched each cycle (Total) | 381system.cpu.fetch.icacheStallCycles 12535190 # Number of cycles fetch is stalled on an Icache miss 382system.cpu.fetch.Insts 85154971 # Number of instructions fetch has processed 383system.cpu.fetch.Branches 16620839 # Number of branches that fetch encountered 384system.cpu.fetch.predictedBranches 9590104 # Number of branches that fetch has predicted taken 385system.cpu.fetch.Cycles 21184086 # Number of cycles fetch has run and was not squashing or blocked 386system.cpu.fetch.SquashCycles 2355794 # Number of cycles fetch has spent squashing 387system.cpu.fetch.BlockedCycles 10829442 # Number of cycles fetch has spent blocked 388system.cpu.fetch.MiscStallCycles 84 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 389system.cpu.fetch.PendingTrapStallCycles 551 # Number of stall cycles due to pending traps 390system.cpu.fetch.IcacheWaitRetryStallCycles 63 # Number of stall cycles due to full MSHR 391system.cpu.fetch.CacheLines 11674707 # Number of cache lines fetched 392system.cpu.fetch.IcacheSquashes 181091 # Number of outstanding Icache misses that were squashed 393system.cpu.fetch.rateDist::samples 46276167 # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::mean 2.576733 # Number of instructions fetched each cycle (Total) 395system.cpu.fetch.rateDist::stdev 3.331391 # Number of instructions fetched each cycle (Total) |
| 250system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 396system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 251system.cpu.fetch.rateDist::0 24794811 53.96% 53.96% # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::1 2137100 4.65% 58.61% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::2 1960912 4.27% 62.88% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::3 2040333 4.44% 67.32% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::4 1467005 3.19% 70.51% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::5 1375299 2.99% 73.51% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::6 957293 2.08% 75.59% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::7 1188429 2.59% 78.18% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::8 10027906 21.82% 100.00% # Number of instructions fetched each cycle (Total) | 397system.cpu.fetch.rateDist::0 25111993 54.27% 54.27% # Number of instructions fetched each cycle (Total) 398system.cpu.fetch.rateDist::1 2139332 4.62% 58.89% # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::2 1963886 4.24% 63.13% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::3 2043329 4.42% 67.55% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::4 1467358 3.17% 70.72% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::5 1375070 2.97% 73.69% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::6 956833 2.07% 75.76% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::7 1188482 2.57% 78.33% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::8 10029884 21.67% 100.00% # Number of instructions fetched each cycle (Total) |
| 260system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 263system.cpu.fetch.rateDist::total 45949088 # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.branchRate 0.325295 # Number of branch fetches per cycle 265system.cpu.fetch.rate 1.667177 # Number of inst fetches per cycle 266system.cpu.decode.IdleCycles 14598304 # Number of cycles decode is idle 267system.cpu.decode.BlockedCycles 8880725 # Number of cycles decode is blocked 268system.cpu.decode.RunCycles 19456140 # Number of cycles decode is running 269system.cpu.decode.UnblockCycles 1390682 # Number of cycles decode is unblocking 270system.cpu.decode.SquashCycles 1623237 # Number of cycles decode is squashing 271system.cpu.decode.BranchResolved 3327841 # Number of times decode resolved a branch 272system.cpu.decode.BranchMispred 105063 # Number of times decode detected a branch misprediction 273system.cpu.decode.DecodedInsts 116768795 # Number of instructions handled by decode 274system.cpu.decode.SquashedInsts 361627 # Number of squashed instructions handled by decode 275system.cpu.rename.SquashCycles 1623237 # Number of cycles rename is squashing 276system.cpu.rename.IdleCycles 16304724 # Number of cycles rename is idle 277system.cpu.rename.BlockCycles 2541710 # Number of cycles rename is blocking 278system.cpu.rename.serializeStallCycles 873068 # count of cycles rename stalled for serializing inst 279system.cpu.rename.RunCycles 19090805 # Number of cycles rename is running 280system.cpu.rename.UnblockCycles 5515544 # Number of cycles rename is unblocking 281system.cpu.rename.RenamedInsts 114897326 # Number of instructions processed by rename 282system.cpu.rename.ROBFullEvents 145 # Number of times rename has blocked due to ROB full 283system.cpu.rename.IQFullEvents 17204 # Number of times rename has blocked due to IQ full 284system.cpu.rename.LSQFullEvents 4661371 # Number of times rename has blocked due to LSQ full 285system.cpu.rename.FullRegisterEvents 307 # Number of times there has been no free registers 286system.cpu.rename.RenamedOperands 115217977 # Number of destination operands rename has renamed 287system.cpu.rename.RenameLookups 529361609 # Number of register rename lookups that rename has made 288system.cpu.rename.int_rename_lookups 529355204 # Number of integer rename lookups 289system.cpu.rename.fp_rename_lookups 6405 # Number of floating rename lookups | 409system.cpu.fetch.rateDist::total 46276167 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.branchRate 0.311847 # Number of branch fetches per cycle 411system.cpu.fetch.rate 1.597710 # Number of inst fetches per cycle 412system.cpu.decode.IdleCycles 14619512 # Number of cycles decode is idle 413system.cpu.decode.BlockedCycles 9177970 # Number of cycles decode is blocked 414system.cpu.decode.RunCycles 19466340 # Number of cycles decode is running 415system.cpu.decode.UnblockCycles 1388431 # Number of cycles decode is unblocking 416system.cpu.decode.SquashCycles 1623914 # Number of cycles decode is squashing 417system.cpu.decode.BranchResolved 3328977 # Number of times decode resolved a branch 418system.cpu.decode.BranchMispred 104776 # Number of times decode detected a branch misprediction 419system.cpu.decode.DecodedInsts 116789336 # Number of instructions handled by decode 420system.cpu.decode.SquashedInsts 361687 # Number of squashed instructions handled by decode 421system.cpu.rename.SquashCycles 1623914 # Number of cycles rename is squashing 422system.cpu.rename.IdleCycles 16330804 # Number of cycles rename is idle 423system.cpu.rename.BlockCycles 2680643 # Number of cycles rename is blocking 424system.cpu.rename.serializeStallCycles 1000847 # count of cycles rename stalled for serializing inst 425system.cpu.rename.RunCycles 19093672 # Number of cycles rename is running 426system.cpu.rename.UnblockCycles 5546287 # Number of cycles rename is unblocking 427system.cpu.rename.RenamedInsts 114905556 # Number of instructions processed by rename 428system.cpu.rename.ROBFullEvents 219 # Number of times rename has blocked due to ROB full 429system.cpu.rename.IQFullEvents 17136 # Number of times rename has blocked due to IQ full 430system.cpu.rename.LSQFullEvents 4693151 # Number of times rename has blocked due to LSQ full 431system.cpu.rename.FullRegisterEvents 1312 # Number of times there has been no free registers 432system.cpu.rename.RenamedOperands 115218637 # Number of destination operands rename has renamed 433system.cpu.rename.RenameLookups 529387920 # Number of register rename lookups that rename has made 434system.cpu.rename.int_rename_lookups 529379803 # Number of integer rename lookups 435system.cpu.rename.fp_rename_lookups 8117 # Number of floating rename lookups |
| 290system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed | 436system.cpu.rename.CommittedMaps 99132672 # Number of HB maps that are committed |
| 291system.cpu.rename.UndoneMaps 16085305 # Number of HB maps that are undone due to squashing 292system.cpu.rename.serializingInsts 20097 # count of serializing insts renamed 293system.cpu.rename.tempSerializingInsts 20095 # count of temporary serializing insts renamed 294system.cpu.rename.skidInsts 13032825 # count of insts added to the skid buffer 295system.cpu.memDep0.insertedLoads 29592002 # Number of loads inserted to the mem dependence unit. 296system.cpu.memDep0.insertedStores 22430174 # Number of stores inserted to the mem dependence unit. 297system.cpu.memDep0.conflictingLoads 3871274 # Number of conflicting loads. 298system.cpu.memDep0.conflictingStores 4372916 # Number of conflicting stores. 299system.cpu.iq.iqInstsAdded 111465960 # Number of instructions added to the IQ (excludes non-spec) 300system.cpu.iq.iqNonSpecInstsAdded 35763 # Number of non-speculative instructions added to the IQ 301system.cpu.iq.iqInstsIssued 107205680 # Number of instructions issued 302system.cpu.iq.iqSquashedInstsIssued 272682 # Number of squashed instructions issued 303system.cpu.iq.iqSquashedInstsExamined 10729594 # Number of squashed instructions iterated over during squash; mainly for profiling 304system.cpu.iq.iqSquashedOperandsExamined 25689497 # Number of squashed operands that are examined and possibly removed from graph 305system.cpu.iq.iqSquashedNonSpecRemoved 1977 # Number of squashed non-spec instructions that were removed 306system.cpu.iq.issued_per_cycle::samples 45949088 # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::mean 2.333141 # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::stdev 1.988541 # Number of insts issued each cycle | 437system.cpu.rename.UndoneMaps 16085965 # Number of HB maps that are undone due to squashing 438system.cpu.rename.serializingInsts 20302 # count of serializing insts renamed 439system.cpu.rename.tempSerializingInsts 20297 # count of temporary serializing insts renamed 440system.cpu.rename.skidInsts 13065620 # count of insts added to the skid buffer 441system.cpu.memDep0.insertedLoads 29609265 # Number of loads inserted to the mem dependence unit. 442system.cpu.memDep0.insertedStores 22417131 # Number of stores inserted to the mem dependence unit. 443system.cpu.memDep0.conflictingLoads 3885027 # Number of conflicting loads. 444system.cpu.memDep0.conflictingStores 4397806 # Number of conflicting stores. 445system.cpu.iq.iqInstsAdded 111472584 # Number of instructions added to the IQ (excludes non-spec) 446system.cpu.iq.iqNonSpecInstsAdded 35916 # Number of non-speculative instructions added to the IQ 447system.cpu.iq.iqInstsIssued 107208843 # Number of instructions issued 448system.cpu.iq.iqSquashedInstsIssued 271699 # Number of squashed instructions issued 449system.cpu.iq.iqSquashedInstsExamined 10738438 # Number of squashed instructions iterated over during squash; mainly for profiling 450system.cpu.iq.iqSquashedOperandsExamined 25737967 # Number of squashed operands that are examined and possibly removed from graph 451system.cpu.iq.iqSquashedNonSpecRemoved 2130 # Number of squashed non-spec instructions that were removed 452system.cpu.iq.issued_per_cycle::samples 46276167 # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::mean 2.316718 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::stdev 1.989507 # Number of insts issued each cycle |
| 309system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 455system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 310system.cpu.iq.issued_per_cycle::0 10727082 23.35% 23.35% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::1 8071187 17.57% 40.91% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::2 7423916 16.16% 57.07% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::3 7121409 15.50% 72.57% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::4 5405071 11.76% 84.33% # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::5 3914661 8.52% 92.85% # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::6 1842461 4.01% 96.86% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::7 872329 1.90% 98.76% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::8 570972 1.24% 100.00% # Number of insts issued each cycle | 456system.cpu.iq.issued_per_cycle::0 11020528 23.81% 23.81% # Number of insts issued each cycle 457system.cpu.iq.issued_per_cycle::1 8094858 17.49% 41.31% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::2 7429249 16.05% 57.36% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::3 7154901 15.46% 72.82% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::4 5386733 11.64% 84.46% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::5 3906460 8.44% 92.90% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::6 1842144 3.98% 96.89% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::7 871664 1.88% 98.77% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::8 569630 1.23% 100.00% # Number of insts issued each cycle |
| 319system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 465system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 322system.cpu.iq.issued_per_cycle::total 45949088 # Number of insts issued each cycle | 468system.cpu.iq.issued_per_cycle::total 46276167 # Number of insts issued each cycle |
| 323system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 469system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 324system.cpu.iq.fu_full::IntAlu 112030 4.53% 4.53% # attempts to use FU when none available 325system.cpu.iq.fu_full::IntMult 0 0.00% 4.53% # attempts to use FU when none available 326system.cpu.iq.fu_full::IntDiv 0 0.00% 4.53% # attempts to use FU when none available 327system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.53% # attempts to use FU when none available 328system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.53% # attempts to use FU when none available 329system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.53% # attempts to use FU when none available 330system.cpu.iq.fu_full::FloatMult 0 0.00% 4.53% # attempts to use FU when none available 331system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.53% # attempts to use FU when none available 332system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.53% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.53% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.53% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.53% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.53% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.53% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.53% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdMult 0 0.00% 4.53% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.53% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdShift 0 0.00% 4.53% # attempts to use FU when none available 342system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.53% # attempts to use FU when none available 343system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.53% # attempts to use FU when none available 344system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.53% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.53% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.53% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.53% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.53% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.53% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.53% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.53% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.53% # attempts to use FU when none available 353system.cpu.iq.fu_full::MemRead 1365113 55.14% 59.67% # attempts to use FU when none available 354system.cpu.iq.fu_full::MemWrite 998480 40.33% 100.00% # attempts to use FU when none available | 470system.cpu.iq.fu_full::IntAlu 112593 4.57% 4.57% # attempts to use FU when none available 471system.cpu.iq.fu_full::IntMult 0 0.00% 4.57% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntDiv 0 0.00% 4.57% # attempts to use FU when none available 473system.cpu.iq.fu_full::FloatAdd 2 0.00% 4.57% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.57% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.57% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatMult 0 0.00% 4.57% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.57% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.57% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.57% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.57% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.57% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.57% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.57% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.57% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMult 0 0.00% 4.57% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.57% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdShift 0 0.00% 4.57% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.57% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.57% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.57% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.57% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.57% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.57% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.57% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.57% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.57% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.57% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.57% # attempts to use FU when none available 499system.cpu.iq.fu_full::MemRead 1348878 54.73% 59.30% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemWrite 1003122 40.70% 100.00% # attempts to use FU when none available |
| 355system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 356system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 357system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 501system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 502system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 358system.cpu.iq.FU_type_0::IntAlu 56613296 52.81% 52.81% # Type of FU issued 359system.cpu.iq.FU_type_0::IntMult 91558 0.09% 52.89% # Type of FU issued | 504system.cpu.iq.FU_type_0::IntAlu 56608598 52.80% 52.80% # Type of FU issued 505system.cpu.iq.FU_type_0::IntMult 91438 0.09% 52.89% # Type of FU issued |
| 360system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued | 506system.cpu.iq.FU_type_0::IntDiv 0 0.00% 52.89% # Type of FU issued |
| 361system.cpu.iq.FU_type_0::FloatAdd 214 0.00% 52.89% # Type of FU issued | 507system.cpu.iq.FU_type_0::FloatAdd 251 0.00% 52.89% # Type of FU issued |
| 362system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued 363system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued 364system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued 365system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.89% # Type of FU issued 366system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.89% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.89% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.89% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.89% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 379system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.89% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.89% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.89% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.89% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued | 508system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 52.89% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 52.89% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatMult 0 0.00% 52.89% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 52.89% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 52.89% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 52.89% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 52.89% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 52.89% # Type of FU issued --- 9 unchanged lines hidden (view full) --- 525system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 52.89% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 52.89% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 52.89% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 52.89% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 52.89% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 52.89% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 52.89% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 52.89% # Type of FU issued |
| 387system.cpu.iq.FU_type_0::MemRead 28880685 26.94% 79.83% # Type of FU issued 388system.cpu.iq.FU_type_0::MemWrite 21619920 20.17% 100.00% # Type of FU issued | 533system.cpu.iq.FU_type_0::MemRead 28894537 26.95% 79.84% # Type of FU issued 534system.cpu.iq.FU_type_0::MemWrite 21614012 20.16% 100.00% # Type of FU issued |
| 389system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 390system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 535system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 536system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 391system.cpu.iq.FU_type_0::total 107205680 # Type of FU issued 392system.cpu.iq.rate 2.099227 # Inst issue rate 393system.cpu.iq.fu_busy_cnt 2475625 # FU busy when requested 394system.cpu.iq.fu_busy_rate 0.023092 # FU busy rate (busy events/executed inst) 395system.cpu.iq.int_inst_queue_reads 263108167 # Number of integer instruction queue reads 396system.cpu.iq.int_inst_queue_writes 122259769 # Number of integer instruction queue writes 397system.cpu.iq.int_inst_queue_wakeup_accesses 105531182 # Number of integer instruction queue wakeup accesses 398system.cpu.iq.fp_inst_queue_reads 588 # Number of floating instruction queue reads 399system.cpu.iq.fp_inst_queue_writes 948 # Number of floating instruction queue writes 400system.cpu.iq.fp_inst_queue_wakeup_accesses 171 # Number of floating instruction queue wakeup accesses 401system.cpu.iq.int_alu_accesses 109681012 # Number of integer alu accesses 402system.cpu.iq.fp_alu_accesses 293 # Number of floating point alu accesses 403system.cpu.iew.lsq.thread0.forwLoads 2183832 # Number of loads that had data forwarded from stores | 537system.cpu.iq.FU_type_0::total 107208843 # Type of FU issued 538system.cpu.iq.rate 2.011494 # Inst issue rate 539system.cpu.iq.fu_busy_cnt 2464595 # FU busy when requested 540system.cpu.iq.fu_busy_rate 0.022989 # FU busy rate (busy events/executed inst) 541system.cpu.iq.int_inst_queue_reads 263429476 # Number of integer instruction queue reads 542system.cpu.iq.int_inst_queue_writes 122274650 # Number of integer instruction queue writes 543system.cpu.iq.int_inst_queue_wakeup_accesses 105524045 # Number of integer instruction queue wakeup accesses 544system.cpu.iq.fp_inst_queue_reads 671 # Number of floating instruction queue reads 545system.cpu.iq.fp_inst_queue_writes 1168 # Number of floating instruction queue writes 546system.cpu.iq.fp_inst_queue_wakeup_accesses 196 # Number of floating instruction queue wakeup accesses 547system.cpu.iq.int_alu_accesses 109673111 # Number of integer alu accesses 548system.cpu.iq.fp_alu_accesses 327 # Number of floating point alu accesses 549system.cpu.iew.lsq.thread0.forwLoads 2189921 # Number of loads that had data forwarded from stores |
| 404system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 550system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 405system.cpu.iew.lsq.thread0.squashedLoads 2284894 # Number of loads squashed 406system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed 407system.cpu.iew.lsq.thread0.memOrderViolation 30581 # Number of memory ordering violations 408system.cpu.iew.lsq.thread0.squashedStores 1874436 # Number of stores squashed | 551system.cpu.iew.lsq.thread0.squashedLoads 2302157 # Number of loads squashed 552system.cpu.iew.lsq.thread0.ignoredResponses 6684 # Number of memory responses ignored because the instruction is squashed 553system.cpu.iew.lsq.thread0.memOrderViolation 29801 # Number of memory ordering violations 554system.cpu.iew.lsq.thread0.squashedStores 1861393 # Number of stores squashed |
| 409system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 410system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 555system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 556system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 411system.cpu.iew.lsq.thread0.rescheduledLoads 30 # Number of loads that were rescheduled 412system.cpu.iew.lsq.thread0.cacheBlocked 495 # Number of times an access to memory failed due to the cache being blocked | 557system.cpu.iew.lsq.thread0.rescheduledLoads 27 # Number of loads that were rescheduled 558system.cpu.iew.lsq.thread0.cacheBlocked 724 # Number of times an access to memory failed due to the cache being blocked |
| 413system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 559system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 414system.cpu.iew.iewSquashCycles 1623237 # Number of cycles IEW is squashing 415system.cpu.iew.iewBlockCycles 1048241 # Number of cycles IEW is blocking 416system.cpu.iew.iewUnblockCycles 45255 # Number of cycles IEW is unblocking 417system.cpu.iew.iewDispatchedInsts 111511491 # Number of instructions dispatched to IQ 418system.cpu.iew.iewDispSquashedInsts 294294 # Number of squashed instructions skipped by dispatch 419system.cpu.iew.iewDispLoadInsts 29592002 # Number of dispatched load instructions 420system.cpu.iew.iewDispStoreInsts 22430174 # Number of dispatched store instructions 421system.cpu.iew.iewDispNonSpecInsts 19843 # Number of dispatched non-speculative instructions 422system.cpu.iew.iewIQFullEvents 6298 # Number of times the IQ has become full, causing a stall 423system.cpu.iew.iewLSQFullEvents 5233 # Number of times the LSQ has become full, causing a stall 424system.cpu.iew.memOrderViolationEvents 30581 # Number of memory order violations 425system.cpu.iew.predictedTakenIncorrect 389128 # Number of branches that were predicted taken incorrectly 426system.cpu.iew.predictedNotTakenIncorrect 180293 # Number of branches that were predicted not taken incorrectly 427system.cpu.iew.branchMispredicts 569421 # Number of branch mispredicts detected at execute 428system.cpu.iew.iewExecutedInsts 106181674 # Number of executed instructions 429system.cpu.iew.iewExecLoadInsts 28584421 # Number of load instructions executed 430system.cpu.iew.iewExecSquashedInsts 1024006 # Number of squashed instructions skipped in execute | 560system.cpu.iew.iewSquashCycles 1623914 # Number of cycles IEW is squashing 561system.cpu.iew.iewBlockCycles 1145014 # Number of cycles IEW is blocking 562system.cpu.iew.iewUnblockCycles 48197 # Number of cycles IEW is unblocking 563system.cpu.iew.iewDispatchedInsts 111518283 # Number of instructions dispatched to IQ 564system.cpu.iew.iewDispSquashedInsts 295309 # Number of squashed instructions skipped by dispatch 565system.cpu.iew.iewDispLoadInsts 29609265 # Number of dispatched load instructions 566system.cpu.iew.iewDispStoreInsts 22417131 # Number of dispatched store instructions 567system.cpu.iew.iewDispNonSpecInsts 19996 # Number of dispatched non-speculative instructions 568system.cpu.iew.iewIQFullEvents 6449 # Number of times the IQ has become full, causing a stall 569system.cpu.iew.iewLSQFullEvents 5406 # Number of times the LSQ has become full, causing a stall 570system.cpu.iew.memOrderViolationEvents 29801 # Number of memory order violations 571system.cpu.iew.predictedTakenIncorrect 392238 # Number of branches that were predicted taken incorrectly 572system.cpu.iew.predictedNotTakenIncorrect 181031 # Number of branches that were predicted not taken incorrectly 573system.cpu.iew.branchMispredicts 573269 # Number of branch mispredicts detected at execute 574system.cpu.iew.iewExecutedInsts 106181942 # Number of executed instructions 575system.cpu.iew.iewExecLoadInsts 28595303 # Number of load instructions executed 576system.cpu.iew.iewExecSquashedInsts 1026901 # Number of squashed instructions skipped in execute |
| 431system.cpu.iew.exec_swp 0 # number of swp insts executed | 577system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 432system.cpu.iew.exec_nop 9768 # number of nop insts executed 433system.cpu.iew.exec_refs 49919693 # number of memory reference insts executed 434system.cpu.iew.exec_branches 14596236 # Number of branches executed 435system.cpu.iew.exec_stores 21335272 # Number of stores executed 436system.cpu.iew.exec_rate 2.079176 # Inst execution rate 437system.cpu.iew.wb_sent 105750982 # cumulative count of insts sent to commit 438system.cpu.iew.wb_count 105531353 # cumulative count of insts written-back 439system.cpu.iew.wb_producers 53247115 # num instructions producing a value 440system.cpu.iew.wb_consumers 103478594 # num instructions consuming a value | 578system.cpu.iew.exec_nop 9783 # number of nop insts executed 579system.cpu.iew.exec_refs 49924361 # number of memory reference insts executed 580system.cpu.iew.exec_branches 14597950 # Number of branches executed 581system.cpu.iew.exec_stores 21329058 # Number of stores executed 582system.cpu.iew.exec_rate 1.992227 # Inst execution rate 583system.cpu.iew.wb_sent 105744224 # cumulative count of insts sent to commit 584system.cpu.iew.wb_count 105524241 # cumulative count of insts written-back 585system.cpu.iew.wb_producers 53247487 # num instructions producing a value 586system.cpu.iew.wb_consumers 103444790 # num instructions consuming a value |
| 441system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 587system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 442system.cpu.iew.wb_rate 2.066442 # insts written-back per cycle 443system.cpu.iew.wb_fanout 0.514571 # average fanout of values written-back | 588system.cpu.iew.wb_rate 1.979887 # insts written-back per cycle 589system.cpu.iew.wb_fanout 0.514743 # average fanout of values written-back |
| 444system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 590system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 445system.cpu.commit.commitSquashedInsts 10879947 # The number of squashed insts skipped by commit | 591system.cpu.commit.commitSquashedInsts 10886753 # The number of squashed insts skipped by commit |
| 446system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards | 592system.cpu.commit.commitNonSpecStalls 33786 # The number of times commit has been forced to stall to communicate backwards |
| 447system.cpu.commit.branchMispredicts 496884 # The number of times a branch was mispredicted 448system.cpu.commit.committed_per_cycle::samples 44325851 # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::mean 2.270288 # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::stdev 2.765576 # Number of insts commited each cycle | 593system.cpu.commit.branchMispredicts 499558 # The number of times a branch was mispredicted 594system.cpu.commit.committed_per_cycle::samples 44652253 # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::mean 2.253692 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::stdev 2.763005 # Number of insts commited each cycle |
| 451system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 597system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 452system.cpu.commit.committed_per_cycle::0 15270109 34.45% 34.45% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::1 11622339 26.22% 60.67% # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::2 3461273 7.81% 68.48% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::3 2876315 6.49% 74.97% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::4 1875935 4.23% 79.20% # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::5 1955485 4.41% 83.61% # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::6 687541 1.55% 85.16% # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::7 562645 1.27% 86.43% # Number of insts commited each cycle 460system.cpu.commit.committed_per_cycle::8 6014209 13.57% 100.00% # Number of insts commited each cycle | 598system.cpu.commit.committed_per_cycle::0 15559873 34.85% 34.85% # Number of insts commited each cycle 599system.cpu.commit.committed_per_cycle::1 11688259 26.18% 61.02% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::2 3454288 7.74% 68.76% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::3 2872185 6.43% 75.19% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::4 1868727 4.19% 79.38% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::5 1932277 4.33% 83.70% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::6 683931 1.53% 85.24% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::7 562545 1.26% 86.50% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::8 6030168 13.50% 100.00% # Number of insts commited each cycle |
| 461system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 607system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 464system.cpu.commit.committed_per_cycle::total 44325851 # Number of insts commited each cycle | 610system.cpu.commit.committed_per_cycle::total 44652253 # Number of insts commited each cycle |
| 465system.cpu.commit.committedInsts 70913181 # Number of instructions committed 466system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed 467system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 468system.cpu.commit.refs 47862846 # Number of memory references committed 469system.cpu.commit.loads 27307108 # Number of loads committed 470system.cpu.commit.membars 15920 # Number of memory barriers committed 471system.cpu.commit.branches 13741485 # Number of branches committed 472system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 473system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. 474system.cpu.commit.function_calls 1679850 # Number of function calls committed. | 611system.cpu.commit.committedInsts 70913181 # Number of instructions committed 612system.cpu.commit.committedOps 100632428 # Number of ops (including micro ops) committed 613system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 614system.cpu.commit.refs 47862846 # Number of memory references committed 615system.cpu.commit.loads 27307108 # Number of loads committed 616system.cpu.commit.membars 15920 # Number of memory barriers committed 617system.cpu.commit.branches 13741485 # Number of branches committed 618system.cpu.commit.fp_insts 56 # Number of committed floating point instructions. 619system.cpu.commit.int_insts 91472779 # Number of committed integer instructions. 620system.cpu.commit.function_calls 1679850 # Number of function calls committed. |
| 475system.cpu.commit.bw_lim_events 6014209 # number cycles where commit BW limit reached | 621system.cpu.commit.bw_lim_events 6030168 # number cycles where commit BW limit reached |
| 476system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 622system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 477system.cpu.rob.rob_reads 149798718 # The number of ROB reads 478system.cpu.rob.rob_writes 224657070 # The number of ROB writes 479system.cpu.timesIdled 74104 # Number of times that the entire CPU went into an idle state and unscheduled itself 480system.cpu.idleCycles 5120025 # Total number of cycles that the CPU has spent unscheduled due to idling | 623system.cpu.rob.rob_reads 150115967 # The number of ROB reads 624system.cpu.rob.rob_writes 224671489 # The number of ROB writes 625system.cpu.timesIdled 79206 # Number of times that the entire CPU went into an idle state and unscheduled itself 626system.cpu.idleCycles 7021959 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 481system.cpu.committedInsts 70907629 # Number of Instructions Simulated 482system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated 483system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated | 627system.cpu.committedInsts 70907629 # Number of Instructions Simulated 628system.cpu.committedOps 100626876 # Number of Ops (including micro ops) Simulated 629system.cpu.committedInsts_total 70907629 # Number of Instructions Simulated |
| 484system.cpu.cpi 0.720220 # CPI: Cycles Per Instruction 485system.cpu.cpi_total 0.720220 # CPI: Total CPI of All Threads 486system.cpu.ipc 1.388464 # IPC: Instructions Per Cycle 487system.cpu.ipc_total 1.388464 # IPC: Total IPC of All Threads 488system.cpu.int_regfile_reads 511419502 # number of integer regfile reads 489system.cpu.int_regfile_writes 103305182 # number of integer regfile writes 490system.cpu.fp_regfile_reads 846 # number of floating regfile reads 491system.cpu.fp_regfile_writes 738 # number of floating regfile writes 492system.cpu.misc_regfile_reads 49163804 # number of misc regfile reads | 630system.cpu.cpi 0.751656 # CPI: Cycles Per Instruction 631system.cpu.cpi_total 0.751656 # CPI: Total CPI of All Threads 632system.cpu.ipc 1.330396 # IPC: Instructions Per Cycle 633system.cpu.ipc_total 1.330396 # IPC: Total IPC of All Threads 634system.cpu.int_regfile_reads 511415343 # number of integer regfile reads 635system.cpu.int_regfile_writes 103300902 # number of integer regfile writes 636system.cpu.fp_regfile_reads 1012 # number of floating regfile reads 637system.cpu.fp_regfile_writes 876 # number of floating regfile writes 638system.cpu.misc_regfile_reads 49160884 # number of misc regfile reads |
| 493system.cpu.misc_regfile_writes 31840 # number of misc regfile writes | 639system.cpu.misc_regfile_writes 31840 # number of misc regfile writes |
| 494system.cpu.icache.replacements 28595 # number of replacements 495system.cpu.icache.tagsinuse 1814.564534 # Cycle average of tags in use 496system.cpu.icache.total_refs 11628419 # Total number of references to valid blocks. 497system.cpu.icache.sampled_refs 30629 # Sample count of references to valid blocks. 498system.cpu.icache.avg_refs 379.653890 # Average number of references to valid blocks. | 640system.cpu.toL2Bus.throughput 776266857 # Throughput (bytes/s) 641system.cpu.toL2Bus.trans_dist::ReadReq 87116 # Transaction distribution 642system.cpu.toL2Bus.trans_dist::ReadResp 87115 # Transaction distribution 643system.cpu.toL2Bus.trans_dist::Writeback 129077 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::UpgradeReq 326 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::UpgradeResp 326 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::ReadExReq 107039 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::ReadExResp 107039 # Transaction distribution 648system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 62962 # Packet count per connected master and slave (bytes) 649system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 454559 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.pkt_count 517521 # Packet count per connected master and slave (bytes) 651system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 1998208 # Cumulative packet size per connected master and slave (bytes) 652system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 18655488 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.tot_pkt_size 20653696 # Cumulative packet size per connected master and slave (bytes) 654system.cpu.toL2Bus.data_through_bus 20653696 # Total data (bytes) 655system.cpu.toL2Bus.snoop_data_through_bus 33088 # Total snoop data (bytes) 656system.cpu.toL2Bus.reqLayer0.occupancy 290859995 # Layer occupancy (ticks) 657system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 658system.cpu.toL2Bus.respLayer0.occupancy 47617981 # Layer occupancy (ticks) 659system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) 660system.cpu.toL2Bus.respLayer1.occupancy 243817935 # Layer occupancy (ticks) 661system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 662system.cpu.icache.replacements 29381 # number of replacements 663system.cpu.icache.tagsinuse 1810.408207 # Cycle average of tags in use 664system.cpu.icache.total_refs 11639182 # Total number of references to valid blocks. 665system.cpu.icache.sampled_refs 31418 # Sample count of references to valid blocks. 666system.cpu.icache.avg_refs 370.462219 # Average number of references to valid blocks. |
| 499system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 667system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 500system.cpu.icache.occ_blocks::cpu.inst 1814.564534 # Average occupied blocks per requestor 501system.cpu.icache.occ_percent::cpu.inst 0.886018 # Average percentage of cache occupancy 502system.cpu.icache.occ_percent::total 0.886018 # Average percentage of cache occupancy 503system.cpu.icache.ReadReq_hits::cpu.inst 11628429 # number of ReadReq hits 504system.cpu.icache.ReadReq_hits::total 11628429 # number of ReadReq hits 505system.cpu.icache.demand_hits::cpu.inst 11628429 # number of demand (read+write) hits 506system.cpu.icache.demand_hits::total 11628429 # number of demand (read+write) hits 507system.cpu.icache.overall_hits::cpu.inst 11628429 # number of overall hits 508system.cpu.icache.overall_hits::total 11628429 # number of overall hits 509system.cpu.icache.ReadReq_misses::cpu.inst 34736 # number of ReadReq misses 510system.cpu.icache.ReadReq_misses::total 34736 # number of ReadReq misses 511system.cpu.icache.demand_misses::cpu.inst 34736 # number of demand (read+write) misses 512system.cpu.icache.demand_misses::total 34736 # number of demand (read+write) misses 513system.cpu.icache.overall_misses::cpu.inst 34736 # number of overall misses 514system.cpu.icache.overall_misses::total 34736 # number of overall misses 515system.cpu.icache.ReadReq_miss_latency::cpu.inst 739850999 # number of ReadReq miss cycles 516system.cpu.icache.ReadReq_miss_latency::total 739850999 # number of ReadReq miss cycles 517system.cpu.icache.demand_miss_latency::cpu.inst 739850999 # number of demand (read+write) miss cycles 518system.cpu.icache.demand_miss_latency::total 739850999 # number of demand (read+write) miss cycles 519system.cpu.icache.overall_miss_latency::cpu.inst 739850999 # number of overall miss cycles 520system.cpu.icache.overall_miss_latency::total 739850999 # number of overall miss cycles 521system.cpu.icache.ReadReq_accesses::cpu.inst 11663165 # number of ReadReq accesses(hits+misses) 522system.cpu.icache.ReadReq_accesses::total 11663165 # number of ReadReq accesses(hits+misses) 523system.cpu.icache.demand_accesses::cpu.inst 11663165 # number of demand (read+write) accesses 524system.cpu.icache.demand_accesses::total 11663165 # number of demand (read+write) accesses 525system.cpu.icache.overall_accesses::cpu.inst 11663165 # number of overall (read+write) accesses 526system.cpu.icache.overall_accesses::total 11663165 # number of overall (read+write) accesses 527system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.002978 # miss rate for ReadReq accesses 528system.cpu.icache.ReadReq_miss_rate::total 0.002978 # miss rate for ReadReq accesses 529system.cpu.icache.demand_miss_rate::cpu.inst 0.002978 # miss rate for demand accesses 530system.cpu.icache.demand_miss_rate::total 0.002978 # miss rate for demand accesses 531system.cpu.icache.overall_miss_rate::cpu.inst 0.002978 # miss rate for overall accesses 532system.cpu.icache.overall_miss_rate::total 0.002978 # miss rate for overall accesses 533system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21299.257226 # average ReadReq miss latency 534system.cpu.icache.ReadReq_avg_miss_latency::total 21299.257226 # average ReadReq miss latency 535system.cpu.icache.demand_avg_miss_latency::cpu.inst 21299.257226 # average overall miss latency 536system.cpu.icache.demand_avg_miss_latency::total 21299.257226 # average overall miss latency 537system.cpu.icache.overall_avg_miss_latency::cpu.inst 21299.257226 # average overall miss latency 538system.cpu.icache.overall_avg_miss_latency::total 21299.257226 # average overall miss latency 539system.cpu.icache.blocked_cycles::no_mshrs 1371 # number of cycles access was blocked | 668system.cpu.icache.occ_blocks::cpu.inst 1810.408207 # Average occupied blocks per requestor 669system.cpu.icache.occ_percent::cpu.inst 0.883988 # Average percentage of cache occupancy 670system.cpu.icache.occ_percent::total 0.883988 # Average percentage of cache occupancy 671system.cpu.icache.ReadReq_hits::cpu.inst 11639193 # number of ReadReq hits 672system.cpu.icache.ReadReq_hits::total 11639193 # number of ReadReq hits 673system.cpu.icache.demand_hits::cpu.inst 11639193 # number of demand (read+write) hits 674system.cpu.icache.demand_hits::total 11639193 # number of demand (read+write) hits 675system.cpu.icache.overall_hits::cpu.inst 11639193 # number of overall hits 676system.cpu.icache.overall_hits::total 11639193 # number of overall hits 677system.cpu.icache.ReadReq_misses::cpu.inst 35513 # number of ReadReq misses 678system.cpu.icache.ReadReq_misses::total 35513 # number of ReadReq misses 679system.cpu.icache.demand_misses::cpu.inst 35513 # number of demand (read+write) misses 680system.cpu.icache.demand_misses::total 35513 # number of demand (read+write) misses 681system.cpu.icache.overall_misses::cpu.inst 35513 # number of overall misses 682system.cpu.icache.overall_misses::total 35513 # number of overall misses 683system.cpu.icache.ReadReq_miss_latency::cpu.inst 845054999 # number of ReadReq miss cycles 684system.cpu.icache.ReadReq_miss_latency::total 845054999 # number of ReadReq miss cycles 685system.cpu.icache.demand_miss_latency::cpu.inst 845054999 # number of demand (read+write) miss cycles 686system.cpu.icache.demand_miss_latency::total 845054999 # number of demand (read+write) miss cycles 687system.cpu.icache.overall_miss_latency::cpu.inst 845054999 # number of overall miss cycles 688system.cpu.icache.overall_miss_latency::total 845054999 # number of overall miss cycles 689system.cpu.icache.ReadReq_accesses::cpu.inst 11674706 # number of ReadReq accesses(hits+misses) 690system.cpu.icache.ReadReq_accesses::total 11674706 # number of ReadReq accesses(hits+misses) 691system.cpu.icache.demand_accesses::cpu.inst 11674706 # number of demand (read+write) accesses 692system.cpu.icache.demand_accesses::total 11674706 # number of demand (read+write) accesses 693system.cpu.icache.overall_accesses::cpu.inst 11674706 # number of overall (read+write) accesses 694system.cpu.icache.overall_accesses::total 11674706 # number of overall (read+write) accesses 695system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.003042 # miss rate for ReadReq accesses 696system.cpu.icache.ReadReq_miss_rate::total 0.003042 # miss rate for ReadReq accesses 697system.cpu.icache.demand_miss_rate::cpu.inst 0.003042 # miss rate for demand accesses 698system.cpu.icache.demand_miss_rate::total 0.003042 # miss rate for demand accesses 699system.cpu.icache.overall_miss_rate::cpu.inst 0.003042 # miss rate for overall accesses 700system.cpu.icache.overall_miss_rate::total 0.003042 # miss rate for overall accesses 701system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23795.652268 # average ReadReq miss latency 702system.cpu.icache.ReadReq_avg_miss_latency::total 23795.652268 # average ReadReq miss latency 703system.cpu.icache.demand_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency 704system.cpu.icache.demand_avg_miss_latency::total 23795.652268 # average overall miss latency 705system.cpu.icache.overall_avg_miss_latency::cpu.inst 23795.652268 # average overall miss latency 706system.cpu.icache.overall_avg_miss_latency::total 23795.652268 # average overall miss latency 707system.cpu.icache.blocked_cycles::no_mshrs 1082 # number of cycles access was blocked |
| 540system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 708system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 541system.cpu.icache.blocked::no_mshrs 21 # number of cycles access was blocked | 709system.cpu.icache.blocked::no_mshrs 27 # number of cycles access was blocked |
| 542system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 710system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 543system.cpu.icache.avg_blocked_cycles::no_mshrs 65.285714 # average number of cycles each access was blocked | 711system.cpu.icache.avg_blocked_cycles::no_mshrs 40.074074 # average number of cycles each access was blocked |
| 544system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 545system.cpu.icache.fast_writes 0 # number of fast writes performed 546system.cpu.icache.cache_copies 0 # number of cache copies performed | 712system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 713system.cpu.icache.fast_writes 0 # number of fast writes performed 714system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 547system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3776 # number of ReadReq MSHR hits 548system.cpu.icache.ReadReq_mshr_hits::total 3776 # number of ReadReq MSHR hits 549system.cpu.icache.demand_mshr_hits::cpu.inst 3776 # number of demand (read+write) MSHR hits 550system.cpu.icache.demand_mshr_hits::total 3776 # number of demand (read+write) MSHR hits 551system.cpu.icache.overall_mshr_hits::cpu.inst 3776 # number of overall MSHR hits 552system.cpu.icache.overall_mshr_hits::total 3776 # number of overall MSHR hits 553system.cpu.icache.ReadReq_mshr_misses::cpu.inst 30960 # number of ReadReq MSHR misses 554system.cpu.icache.ReadReq_mshr_misses::total 30960 # number of ReadReq MSHR misses 555system.cpu.icache.demand_mshr_misses::cpu.inst 30960 # number of demand (read+write) MSHR misses 556system.cpu.icache.demand_mshr_misses::total 30960 # number of demand (read+write) MSHR misses 557system.cpu.icache.overall_mshr_misses::cpu.inst 30960 # number of overall MSHR misses 558system.cpu.icache.overall_mshr_misses::total 30960 # number of overall MSHR misses 559system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 598675499 # number of ReadReq MSHR miss cycles 560system.cpu.icache.ReadReq_mshr_miss_latency::total 598675499 # number of ReadReq MSHR miss cycles 561system.cpu.icache.demand_mshr_miss_latency::cpu.inst 598675499 # number of demand (read+write) MSHR miss cycles 562system.cpu.icache.demand_mshr_miss_latency::total 598675499 # number of demand (read+write) MSHR miss cycles 563system.cpu.icache.overall_mshr_miss_latency::cpu.inst 598675499 # number of overall MSHR miss cycles 564system.cpu.icache.overall_mshr_miss_latency::total 598675499 # number of overall MSHR miss cycles 565system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for ReadReq accesses 566system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002655 # mshr miss rate for ReadReq accesses 567system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for demand accesses 568system.cpu.icache.demand_mshr_miss_rate::total 0.002655 # mshr miss rate for demand accesses 569system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002655 # mshr miss rate for overall accesses 570system.cpu.icache.overall_mshr_miss_rate::total 0.002655 # mshr miss rate for overall accesses 571system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19337.063921 # average ReadReq mshr miss latency 572system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19337.063921 # average ReadReq mshr miss latency 573system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19337.063921 # average overall mshr miss latency 574system.cpu.icache.demand_avg_mshr_miss_latency::total 19337.063921 # average overall mshr miss latency 575system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19337.063921 # average overall mshr miss latency 576system.cpu.icache.overall_avg_mshr_miss_latency::total 19337.063921 # average overall mshr miss latency | 715system.cpu.icache.ReadReq_mshr_hits::cpu.inst 3773 # number of ReadReq MSHR hits 716system.cpu.icache.ReadReq_mshr_hits::total 3773 # number of ReadReq MSHR hits 717system.cpu.icache.demand_mshr_hits::cpu.inst 3773 # number of demand (read+write) MSHR hits 718system.cpu.icache.demand_mshr_hits::total 3773 # number of demand (read+write) MSHR hits 719system.cpu.icache.overall_mshr_hits::cpu.inst 3773 # number of overall MSHR hits 720system.cpu.icache.overall_mshr_hits::total 3773 # number of overall MSHR hits 721system.cpu.icache.ReadReq_mshr_misses::cpu.inst 31740 # number of ReadReq MSHR misses 722system.cpu.icache.ReadReq_mshr_misses::total 31740 # number of ReadReq MSHR misses 723system.cpu.icache.demand_mshr_misses::cpu.inst 31740 # number of demand (read+write) MSHR misses 724system.cpu.icache.demand_mshr_misses::total 31740 # number of demand (read+write) MSHR misses 725system.cpu.icache.overall_mshr_misses::cpu.inst 31740 # number of overall MSHR misses 726system.cpu.icache.overall_mshr_misses::total 31740 # number of overall MSHR misses 727system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 686303518 # number of ReadReq MSHR miss cycles 728system.cpu.icache.ReadReq_mshr_miss_latency::total 686303518 # number of ReadReq MSHR miss cycles 729system.cpu.icache.demand_mshr_miss_latency::cpu.inst 686303518 # number of demand (read+write) MSHR miss cycles 730system.cpu.icache.demand_mshr_miss_latency::total 686303518 # number of demand (read+write) MSHR miss cycles 731system.cpu.icache.overall_mshr_miss_latency::cpu.inst 686303518 # number of overall MSHR miss cycles 732system.cpu.icache.overall_mshr_miss_latency::total 686303518 # number of overall MSHR miss cycles 733system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.002719 # mshr miss rate for ReadReq accesses 734system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002719 # mshr miss rate for ReadReq accesses 735system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.002719 # mshr miss rate for demand accesses 736system.cpu.icache.demand_mshr_miss_rate::total 0.002719 # mshr miss rate for demand accesses 737system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.002719 # mshr miss rate for overall accesses 738system.cpu.icache.overall_mshr_miss_rate::total 0.002719 # mshr miss rate for overall accesses 739system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21622.669124 # average ReadReq mshr miss latency 740system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21622.669124 # average ReadReq mshr miss latency 741system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21622.669124 # average overall mshr miss latency 742system.cpu.icache.demand_avg_mshr_miss_latency::total 21622.669124 # average overall mshr miss latency 743system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21622.669124 # average overall mshr miss latency 744system.cpu.icache.overall_avg_mshr_miss_latency::total 21622.669124 # average overall mshr miss latency |
| 577system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 745system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 578system.cpu.l2cache.replacements 95632 # number of replacements 579system.cpu.l2cache.tagsinuse 30087.760177 # Cycle average of tags in use 580system.cpu.l2cache.total_refs 88021 # Total number of references to valid blocks. 581system.cpu.l2cache.sampled_refs 126747 # Sample count of references to valid blocks. 582system.cpu.l2cache.avg_refs 0.694462 # Average number of references to valid blocks. | 746system.cpu.l2cache.replacements 95633 # number of replacements 747system.cpu.l2cache.tagsinuse 29922.978563 # Cycle average of tags in use 748system.cpu.l2cache.total_refs 88824 # Total number of references to valid blocks. 749system.cpu.l2cache.sampled_refs 126744 # Sample count of references to valid blocks. 750system.cpu.l2cache.avg_refs 0.700814 # Average number of references to valid blocks. |
| 583system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 751system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 584system.cpu.l2cache.occ_blocks::writebacks 26926.191457 # Average occupied blocks per requestor 585system.cpu.l2cache.occ_blocks::cpu.inst 1374.986838 # Average occupied blocks per requestor 586system.cpu.l2cache.occ_blocks::cpu.data 1786.581881 # Average occupied blocks per requestor 587system.cpu.l2cache.occ_percent::writebacks 0.821722 # Average percentage of cache occupancy 588system.cpu.l2cache.occ_percent::cpu.inst 0.041961 # Average percentage of cache occupancy 589system.cpu.l2cache.occ_percent::cpu.data 0.054522 # Average percentage of cache occupancy 590system.cpu.l2cache.occ_percent::total 0.918206 # Average percentage of cache occupancy 591system.cpu.l2cache.ReadReq_hits::cpu.inst 25771 # number of ReadReq hits 592system.cpu.l2cache.ReadReq_hits::cpu.data 33436 # number of ReadReq hits 593system.cpu.l2cache.ReadReq_hits::total 59207 # number of ReadReq hits 594system.cpu.l2cache.Writeback_hits::writebacks 129075 # number of Writeback hits 595system.cpu.l2cache.Writeback_hits::total 129075 # number of Writeback hits 596system.cpu.l2cache.UpgradeReq_hits::cpu.data 18 # number of UpgradeReq hits 597system.cpu.l2cache.UpgradeReq_hits::total 18 # number of UpgradeReq hits 598system.cpu.l2cache.ReadExReq_hits::cpu.data 4783 # number of ReadExReq hits 599system.cpu.l2cache.ReadExReq_hits::total 4783 # number of ReadExReq hits 600system.cpu.l2cache.demand_hits::cpu.inst 25771 # number of demand (read+write) hits 601system.cpu.l2cache.demand_hits::cpu.data 38219 # number of demand (read+write) hits 602system.cpu.l2cache.demand_hits::total 63990 # number of demand (read+write) hits 603system.cpu.l2cache.overall_hits::cpu.inst 25771 # number of overall hits 604system.cpu.l2cache.overall_hits::cpu.data 38219 # number of overall hits 605system.cpu.l2cache.overall_hits::total 63990 # number of overall hits 606system.cpu.l2cache.ReadReq_misses::cpu.inst 4664 # number of ReadReq misses 607system.cpu.l2cache.ReadReq_misses::cpu.data 21927 # number of ReadReq misses 608system.cpu.l2cache.ReadReq_misses::total 26591 # number of ReadReq misses 609system.cpu.l2cache.UpgradeReq_misses::cpu.data 324 # number of UpgradeReq misses 610system.cpu.l2cache.UpgradeReq_misses::total 324 # number of UpgradeReq misses 611system.cpu.l2cache.ReadExReq_misses::cpu.data 102251 # number of ReadExReq misses 612system.cpu.l2cache.ReadExReq_misses::total 102251 # number of ReadExReq misses 613system.cpu.l2cache.demand_misses::cpu.inst 4664 # number of demand (read+write) misses 614system.cpu.l2cache.demand_misses::cpu.data 124178 # number of demand (read+write) misses 615system.cpu.l2cache.demand_misses::total 128842 # number of demand (read+write) misses 616system.cpu.l2cache.overall_misses::cpu.inst 4664 # number of overall misses 617system.cpu.l2cache.overall_misses::cpu.data 124178 # number of overall misses 618system.cpu.l2cache.overall_misses::total 128842 # number of overall misses 619system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 309050500 # number of ReadReq miss cycles 620system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1483446500 # number of ReadReq miss cycles 621system.cpu.l2cache.ReadReq_miss_latency::total 1792497000 # number of ReadReq miss cycles 622system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 23000 # number of UpgradeReq miss cycles 623system.cpu.l2cache.UpgradeReq_miss_latency::total 23000 # number of UpgradeReq miss cycles 624system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6646929000 # number of ReadExReq miss cycles 625system.cpu.l2cache.ReadExReq_miss_latency::total 6646929000 # number of ReadExReq miss cycles 626system.cpu.l2cache.demand_miss_latency::cpu.inst 309050500 # number of demand (read+write) miss cycles 627system.cpu.l2cache.demand_miss_latency::cpu.data 8130375500 # number of demand (read+write) miss cycles 628system.cpu.l2cache.demand_miss_latency::total 8439426000 # number of demand (read+write) miss cycles 629system.cpu.l2cache.overall_miss_latency::cpu.inst 309050500 # number of overall miss cycles 630system.cpu.l2cache.overall_miss_latency::cpu.data 8130375500 # number of overall miss cycles 631system.cpu.l2cache.overall_miss_latency::total 8439426000 # number of overall miss cycles 632system.cpu.l2cache.ReadReq_accesses::cpu.inst 30435 # number of ReadReq accesses(hits+misses) 633system.cpu.l2cache.ReadReq_accesses::cpu.data 55363 # number of ReadReq accesses(hits+misses) 634system.cpu.l2cache.ReadReq_accesses::total 85798 # number of ReadReq accesses(hits+misses) 635system.cpu.l2cache.Writeback_accesses::writebacks 129075 # number of Writeback accesses(hits+misses) 636system.cpu.l2cache.Writeback_accesses::total 129075 # number of Writeback accesses(hits+misses) 637system.cpu.l2cache.UpgradeReq_accesses::cpu.data 342 # number of UpgradeReq accesses(hits+misses) 638system.cpu.l2cache.UpgradeReq_accesses::total 342 # number of UpgradeReq accesses(hits+misses) 639system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses) 640system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) 641system.cpu.l2cache.demand_accesses::cpu.inst 30435 # number of demand (read+write) accesses 642system.cpu.l2cache.demand_accesses::cpu.data 162397 # number of demand (read+write) accesses 643system.cpu.l2cache.demand_accesses::total 192832 # number of demand (read+write) accesses 644system.cpu.l2cache.overall_accesses::cpu.inst 30435 # number of overall (read+write) accesses 645system.cpu.l2cache.overall_accesses::cpu.data 162397 # number of overall (read+write) accesses 646system.cpu.l2cache.overall_accesses::total 192832 # number of overall (read+write) accesses 647system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.153245 # miss rate for ReadReq accesses 648system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.396059 # miss rate for ReadReq accesses 649system.cpu.l2cache.ReadReq_miss_rate::total 0.309926 # miss rate for ReadReq accesses 650system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.947368 # miss rate for UpgradeReq accesses 651system.cpu.l2cache.UpgradeReq_miss_rate::total 0.947368 # miss rate for UpgradeReq accesses 652system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955313 # miss rate for ReadExReq accesses 653system.cpu.l2cache.ReadExReq_miss_rate::total 0.955313 # miss rate for ReadExReq accesses 654system.cpu.l2cache.demand_miss_rate::cpu.inst 0.153245 # miss rate for demand accesses 655system.cpu.l2cache.demand_miss_rate::cpu.data 0.764657 # miss rate for demand accesses 656system.cpu.l2cache.demand_miss_rate::total 0.668157 # miss rate for demand accesses 657system.cpu.l2cache.overall_miss_rate::cpu.inst 0.153245 # miss rate for overall accesses 658system.cpu.l2cache.overall_miss_rate::cpu.data 0.764657 # miss rate for overall accesses 659system.cpu.l2cache.overall_miss_rate::total 0.668157 # miss rate for overall accesses 660system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66262.971698 # average ReadReq miss latency 661system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67653.874219 # average ReadReq miss latency 662system.cpu.l2cache.ReadReq_avg_miss_latency::total 67409.913129 # average ReadReq miss latency 663system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 70.987654 # average UpgradeReq miss latency 664system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 70.987654 # average UpgradeReq miss latency 665system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 65006.004831 # average ReadExReq miss latency 666system.cpu.l2cache.ReadExReq_avg_miss_latency::total 65006.004831 # average ReadExReq miss latency 667system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66262.971698 # average overall miss latency 668system.cpu.l2cache.demand_avg_miss_latency::cpu.data 65473.558118 # average overall miss latency 669system.cpu.l2cache.demand_avg_miss_latency::total 65502.134397 # average overall miss latency 670system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66262.971698 # average overall miss latency 671system.cpu.l2cache.overall_avg_miss_latency::cpu.data 65473.558118 # average overall miss latency 672system.cpu.l2cache.overall_avg_miss_latency::total 65502.134397 # average overall miss latency | 752system.cpu.l2cache.occ_blocks::writebacks 26721.791186 # Average occupied blocks per requestor 753system.cpu.l2cache.occ_blocks::cpu.inst 1373.170594 # Average occupied blocks per requestor 754system.cpu.l2cache.occ_blocks::cpu.data 1828.016782 # Average occupied blocks per requestor 755system.cpu.l2cache.occ_percent::writebacks 0.815484 # Average percentage of cache occupancy 756system.cpu.l2cache.occ_percent::cpu.inst 0.041906 # Average percentage of cache occupancy 757system.cpu.l2cache.occ_percent::cpu.data 0.055787 # Average percentage of cache occupancy 758system.cpu.l2cache.occ_percent::total 0.913177 # Average percentage of cache occupancy 759system.cpu.l2cache.ReadReq_hits::cpu.inst 26545 # number of ReadReq hits 760system.cpu.l2cache.ReadReq_hits::cpu.data 33468 # number of ReadReq hits 761system.cpu.l2cache.ReadReq_hits::total 60013 # number of ReadReq hits 762system.cpu.l2cache.Writeback_hits::writebacks 129077 # number of Writeback hits 763system.cpu.l2cache.Writeback_hits::total 129077 # number of Writeback hits 764system.cpu.l2cache.UpgradeReq_hits::cpu.data 14 # number of UpgradeReq hits 765system.cpu.l2cache.UpgradeReq_hits::total 14 # number of UpgradeReq hits 766system.cpu.l2cache.ReadExReq_hits::cpu.data 4785 # number of ReadExReq hits 767system.cpu.l2cache.ReadExReq_hits::total 4785 # number of ReadExReq hits 768system.cpu.l2cache.demand_hits::cpu.inst 26545 # number of demand (read+write) hits 769system.cpu.l2cache.demand_hits::cpu.data 38253 # number of demand (read+write) hits 770system.cpu.l2cache.demand_hits::total 64798 # number of demand (read+write) hits 771system.cpu.l2cache.overall_hits::cpu.inst 26545 # number of overall hits 772system.cpu.l2cache.overall_hits::cpu.data 38253 # number of overall hits 773system.cpu.l2cache.overall_hits::total 64798 # number of overall hits 774system.cpu.l2cache.ReadReq_misses::cpu.inst 4678 # number of ReadReq misses 775system.cpu.l2cache.ReadReq_misses::cpu.data 21908 # number of ReadReq misses 776system.cpu.l2cache.ReadReq_misses::total 26586 # number of ReadReq misses 777system.cpu.l2cache.UpgradeReq_misses::cpu.data 312 # number of UpgradeReq misses 778system.cpu.l2cache.UpgradeReq_misses::total 312 # number of UpgradeReq misses 779system.cpu.l2cache.ReadExReq_misses::cpu.data 102254 # number of ReadExReq misses 780system.cpu.l2cache.ReadExReq_misses::total 102254 # number of ReadExReq misses 781system.cpu.l2cache.demand_misses::cpu.inst 4678 # number of demand (read+write) misses 782system.cpu.l2cache.demand_misses::cpu.data 124162 # number of demand (read+write) misses 783system.cpu.l2cache.demand_misses::total 128840 # number of demand (read+write) misses 784system.cpu.l2cache.overall_misses::cpu.inst 4678 # number of overall misses 785system.cpu.l2cache.overall_misses::cpu.data 124162 # number of overall misses 786system.cpu.l2cache.overall_misses::total 128840 # number of overall misses 787system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 388339000 # number of ReadReq miss cycles 788system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1848175500 # number of ReadReq miss cycles 789system.cpu.l2cache.ReadReq_miss_latency::total 2236514500 # number of ReadReq miss cycles 790system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 22500 # number of UpgradeReq miss cycles 791system.cpu.l2cache.UpgradeReq_miss_latency::total 22500 # number of UpgradeReq miss cycles 792system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8303975500 # number of ReadExReq miss cycles 793system.cpu.l2cache.ReadExReq_miss_latency::total 8303975500 # number of ReadExReq miss cycles 794system.cpu.l2cache.demand_miss_latency::cpu.inst 388339000 # number of demand (read+write) miss cycles 795system.cpu.l2cache.demand_miss_latency::cpu.data 10152151000 # number of demand (read+write) miss cycles 796system.cpu.l2cache.demand_miss_latency::total 10540490000 # number of demand (read+write) miss cycles 797system.cpu.l2cache.overall_miss_latency::cpu.inst 388339000 # number of overall miss cycles 798system.cpu.l2cache.overall_miss_latency::cpu.data 10152151000 # number of overall miss cycles 799system.cpu.l2cache.overall_miss_latency::total 10540490000 # number of overall miss cycles 800system.cpu.l2cache.ReadReq_accesses::cpu.inst 31223 # number of ReadReq accesses(hits+misses) 801system.cpu.l2cache.ReadReq_accesses::cpu.data 55376 # number of ReadReq accesses(hits+misses) 802system.cpu.l2cache.ReadReq_accesses::total 86599 # number of ReadReq accesses(hits+misses) 803system.cpu.l2cache.Writeback_accesses::writebacks 129077 # number of Writeback accesses(hits+misses) 804system.cpu.l2cache.Writeback_accesses::total 129077 # number of Writeback accesses(hits+misses) 805system.cpu.l2cache.UpgradeReq_accesses::cpu.data 326 # number of UpgradeReq accesses(hits+misses) 806system.cpu.l2cache.UpgradeReq_accesses::total 326 # number of UpgradeReq accesses(hits+misses) 807system.cpu.l2cache.ReadExReq_accesses::cpu.data 107039 # number of ReadExReq accesses(hits+misses) 808system.cpu.l2cache.ReadExReq_accesses::total 107039 # number of ReadExReq accesses(hits+misses) 809system.cpu.l2cache.demand_accesses::cpu.inst 31223 # number of demand (read+write) accesses 810system.cpu.l2cache.demand_accesses::cpu.data 162415 # number of demand (read+write) accesses 811system.cpu.l2cache.demand_accesses::total 193638 # number of demand (read+write) accesses 812system.cpu.l2cache.overall_accesses::cpu.inst 31223 # number of overall (read+write) accesses 813system.cpu.l2cache.overall_accesses::cpu.data 162415 # number of overall (read+write) accesses 814system.cpu.l2cache.overall_accesses::total 193638 # number of overall (read+write) accesses 815system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.149825 # miss rate for ReadReq accesses 816system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.395623 # miss rate for ReadReq accesses 817system.cpu.l2cache.ReadReq_miss_rate::total 0.307001 # miss rate for ReadReq accesses 818system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.957055 # miss rate for UpgradeReq accesses 819system.cpu.l2cache.UpgradeReq_miss_rate::total 0.957055 # miss rate for UpgradeReq accesses 820system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955297 # miss rate for ReadExReq accesses 821system.cpu.l2cache.ReadExReq_miss_rate::total 0.955297 # miss rate for ReadExReq accesses 822system.cpu.l2cache.demand_miss_rate::cpu.inst 0.149825 # miss rate for demand accesses 823system.cpu.l2cache.demand_miss_rate::cpu.data 0.764474 # miss rate for demand accesses 824system.cpu.l2cache.demand_miss_rate::total 0.665365 # miss rate for demand accesses 825system.cpu.l2cache.overall_miss_rate::cpu.inst 0.149825 # miss rate for overall accesses 826system.cpu.l2cache.overall_miss_rate::cpu.data 0.764474 # miss rate for overall accesses 827system.cpu.l2cache.overall_miss_rate::total 0.665365 # miss rate for overall accesses 828system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 83013.894827 # average ReadReq miss latency 829system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84360.758627 # average ReadReq miss latency 830system.cpu.l2cache.ReadReq_avg_miss_latency::total 84123.768149 # average ReadReq miss latency 831system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 72.115385 # average UpgradeReq miss latency 832system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 72.115385 # average UpgradeReq miss latency 833system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81209.297436 # average ReadExReq miss latency 834system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81209.297436 # average ReadExReq miss latency 835system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83013.894827 # average overall miss latency 836system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81765.362994 # average overall miss latency 837system.cpu.l2cache.demand_avg_miss_latency::total 81810.695436 # average overall miss latency 838system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83013.894827 # average overall miss latency 839system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81765.362994 # average overall miss latency 840system.cpu.l2cache.overall_avg_miss_latency::total 81810.695436 # average overall miss latency |
| 673system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 674system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 675system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 676system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 677system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 678system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 679system.cpu.l2cache.fast_writes 0 # number of fast writes performed 680system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 841system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 842system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 843system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 844system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 845system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 846system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 847system.cpu.l2cache.fast_writes 0 # number of fast writes performed 848system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 681system.cpu.l2cache.writebacks::writebacks 83945 # number of writebacks 682system.cpu.l2cache.writebacks::total 83945 # number of writebacks 683system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 15 # number of ReadReq MSHR hits 684system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits 685system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits 686system.cpu.l2cache.demand_mshr_hits::cpu.inst 15 # number of demand (read+write) MSHR hits 687system.cpu.l2cache.demand_mshr_hits::cpu.data 59 # number of demand (read+write) MSHR hits 688system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits 689system.cpu.l2cache.overall_mshr_hits::cpu.inst 15 # number of overall MSHR hits 690system.cpu.l2cache.overall_mshr_hits::cpu.data 59 # number of overall MSHR hits 691system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits 692system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4649 # number of ReadReq MSHR misses 693system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21868 # number of ReadReq MSHR misses 694system.cpu.l2cache.ReadReq_mshr_misses::total 26517 # number of ReadReq MSHR misses 695system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 324 # number of UpgradeReq MSHR misses 696system.cpu.l2cache.UpgradeReq_mshr_misses::total 324 # number of UpgradeReq MSHR misses 697system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102251 # number of ReadExReq MSHR misses 698system.cpu.l2cache.ReadExReq_mshr_misses::total 102251 # number of ReadExReq MSHR misses 699system.cpu.l2cache.demand_mshr_misses::cpu.inst 4649 # number of demand (read+write) MSHR misses 700system.cpu.l2cache.demand_mshr_misses::cpu.data 124119 # number of demand (read+write) MSHR misses 701system.cpu.l2cache.demand_mshr_misses::total 128768 # number of demand (read+write) MSHR misses 702system.cpu.l2cache.overall_mshr_misses::cpu.inst 4649 # number of overall MSHR misses 703system.cpu.l2cache.overall_mshr_misses::cpu.data 124119 # number of overall MSHR misses 704system.cpu.l2cache.overall_mshr_misses::total 128768 # number of overall MSHR misses 705system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 250601778 # number of ReadReq MSHR miss cycles 706system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1209315656 # number of ReadReq MSHR miss cycles 707system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1459917434 # number of ReadReq MSHR miss cycles 708system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3249822 # number of UpgradeReq MSHR miss cycles 709system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3249822 # number of UpgradeReq MSHR miss cycles 710system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5391078264 # number of ReadExReq MSHR miss cycles 711system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5391078264 # number of ReadExReq MSHR miss cycles 712system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 250601778 # number of demand (read+write) MSHR miss cycles 713system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6600393920 # number of demand (read+write) MSHR miss cycles 714system.cpu.l2cache.demand_mshr_miss_latency::total 6850995698 # number of demand (read+write) MSHR miss cycles 715system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 250601778 # number of overall MSHR miss cycles 716system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6600393920 # number of overall MSHR miss cycles 717system.cpu.l2cache.overall_mshr_miss_latency::total 6850995698 # number of overall MSHR miss cycles 718system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for ReadReq accesses 719system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394993 # mshr miss rate for ReadReq accesses 720system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.309063 # mshr miss rate for ReadReq accesses 721system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.947368 # mshr miss rate for UpgradeReq accesses 722system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.947368 # mshr miss rate for UpgradeReq accesses 723system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955313 # mshr miss rate for ReadExReq accesses 724system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955313 # mshr miss rate for ReadExReq accesses 725system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for demand accesses 726system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764294 # mshr miss rate for demand accesses 727system.cpu.l2cache.demand_mshr_miss_rate::total 0.667773 # mshr miss rate for demand accesses 728system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.152752 # mshr miss rate for overall accesses 729system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764294 # mshr miss rate for overall accesses 730system.cpu.l2cache.overall_mshr_miss_rate::total 0.667773 # mshr miss rate for overall accesses 731system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 53904.447838 # average ReadReq mshr miss latency 732system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55300.697640 # average ReadReq mshr miss latency 733system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55055.905042 # average ReadReq mshr miss latency 734system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10030.314815 # average UpgradeReq mshr miss latency 735system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10030.314815 # average UpgradeReq mshr miss latency 736system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 52723.966162 # average ReadExReq mshr miss latency 737system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 52723.966162 # average ReadExReq mshr miss latency 738system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 53904.447838 # average overall mshr miss latency 739system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53177.949548 # average overall mshr miss latency 740system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53204.178818 # average overall mshr miss latency 741system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 53904.447838 # average overall mshr miss latency 742system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53177.949548 # average overall mshr miss latency 743system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53204.178818 # average overall mshr miss latency | 849system.cpu.l2cache.writebacks::writebacks 83950 # number of writebacks 850system.cpu.l2cache.writebacks::total 83950 # number of writebacks 851system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 16 # number of ReadReq MSHR hits 852system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits 853system.cpu.l2cache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 854system.cpu.l2cache.demand_mshr_hits::cpu.inst 16 # number of demand (read+write) MSHR hits 855system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits 856system.cpu.l2cache.demand_mshr_hits::total 77 # number of demand (read+write) MSHR hits 857system.cpu.l2cache.overall_mshr_hits::cpu.inst 16 # number of overall MSHR hits 858system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits 859system.cpu.l2cache.overall_mshr_hits::total 77 # number of overall MSHR hits 860system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 4662 # number of ReadReq MSHR misses 861system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21847 # number of ReadReq MSHR misses 862system.cpu.l2cache.ReadReq_mshr_misses::total 26509 # number of ReadReq MSHR misses 863system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 312 # number of UpgradeReq MSHR misses 864system.cpu.l2cache.UpgradeReq_mshr_misses::total 312 # number of UpgradeReq MSHR misses 865system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102254 # number of ReadExReq MSHR misses 866system.cpu.l2cache.ReadExReq_mshr_misses::total 102254 # number of ReadExReq MSHR misses 867system.cpu.l2cache.demand_mshr_misses::cpu.inst 4662 # number of demand (read+write) MSHR misses 868system.cpu.l2cache.demand_mshr_misses::cpu.data 124101 # number of demand (read+write) MSHR misses 869system.cpu.l2cache.demand_mshr_misses::total 128763 # number of demand (read+write) MSHR misses 870system.cpu.l2cache.overall_mshr_misses::cpu.inst 4662 # number of overall MSHR misses 871system.cpu.l2cache.overall_mshr_misses::cpu.data 124101 # number of overall MSHR misses 872system.cpu.l2cache.overall_mshr_misses::total 128763 # number of overall MSHR misses 873system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 329021750 # number of ReadReq MSHR miss cycles 874system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1573055250 # number of ReadReq MSHR miss cycles 875system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1902077000 # number of ReadReq MSHR miss cycles 876system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 3120312 # number of UpgradeReq MSHR miss cycles 877system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 3120312 # number of UpgradeReq MSHR miss cycles 878system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7046523750 # number of ReadExReq MSHR miss cycles 879system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7046523750 # number of ReadExReq MSHR miss cycles 880system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 329021750 # number of demand (read+write) MSHR miss cycles 881system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8619579000 # number of demand (read+write) MSHR miss cycles 882system.cpu.l2cache.demand_mshr_miss_latency::total 8948600750 # number of demand (read+write) MSHR miss cycles 883system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 329021750 # number of overall MSHR miss cycles 884system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8619579000 # number of overall MSHR miss cycles 885system.cpu.l2cache.overall_mshr_miss_latency::total 8948600750 # number of overall MSHR miss cycles 886system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.149313 # mshr miss rate for ReadReq accesses 887system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.394521 # mshr miss rate for ReadReq accesses 888system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.306112 # mshr miss rate for ReadReq accesses 889system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.957055 # mshr miss rate for UpgradeReq accesses 890system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.957055 # mshr miss rate for UpgradeReq accesses 891system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955297 # mshr miss rate for ReadExReq accesses 892system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955297 # mshr miss rate for ReadExReq accesses 893system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.149313 # mshr miss rate for demand accesses 894system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.764098 # mshr miss rate for demand accesses 895system.cpu.l2cache.demand_mshr_miss_rate::total 0.664968 # mshr miss rate for demand accesses 896system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.149313 # mshr miss rate for overall accesses 897system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.764098 # mshr miss rate for overall accesses 898system.cpu.l2cache.overall_mshr_miss_rate::total 0.664968 # mshr miss rate for overall accesses 899system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 70575.235950 # average ReadReq mshr miss latency 900system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72003.261317 # average ReadReq mshr miss latency 901system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71752.121921 # average ReadReq mshr miss latency 902system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency 903system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency 904system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68911.961879 # average ReadExReq mshr miss latency 905system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68911.961879 # average ReadExReq mshr miss latency 906system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 70575.235950 # average overall mshr miss latency 907system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69456.160708 # average overall mshr miss latency 908system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69496.678005 # average overall mshr miss latency 909system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 70575.235950 # average overall mshr miss latency 910system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69456.160708 # average overall mshr miss latency 911system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69496.678005 # average overall mshr miss latency |
| 744system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 912system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 745system.cpu.dcache.replacements 158300 # number of replacements 746system.cpu.dcache.tagsinuse 4072.274733 # Cycle average of tags in use 747system.cpu.dcache.total_refs 44344926 # Total number of references to valid blocks. 748system.cpu.dcache.sampled_refs 162396 # Sample count of references to valid blocks. 749system.cpu.dcache.avg_refs 273.066615 # Average number of references to valid blocks. 750system.cpu.dcache.warmup_cycle 284501000 # Cycle when the warmup percentage was hit. 751system.cpu.dcache.occ_blocks::cpu.data 4072.274733 # Average occupied blocks per requestor 752system.cpu.dcache.occ_percent::cpu.data 0.994208 # Average percentage of cache occupancy 753system.cpu.dcache.occ_percent::total 0.994208 # Average percentage of cache occupancy 754system.cpu.dcache.ReadReq_hits::cpu.data 26045310 # number of ReadReq hits 755system.cpu.dcache.ReadReq_hits::total 26045310 # number of ReadReq hits 756system.cpu.dcache.WriteReq_hits::cpu.data 18267055 # number of WriteReq hits 757system.cpu.dcache.WriteReq_hits::total 18267055 # number of WriteReq hits 758system.cpu.dcache.LoadLockedReq_hits::cpu.data 15985 # number of LoadLockedReq hits 759system.cpu.dcache.LoadLockedReq_hits::total 15985 # number of LoadLockedReq hits | 913system.cpu.dcache.replacements 158319 # number of replacements 914system.cpu.dcache.tagsinuse 4069.477080 # Cycle average of tags in use 915system.cpu.dcache.total_refs 44347755 # Total number of references to valid blocks. 916system.cpu.dcache.sampled_refs 162415 # Sample count of references to valid blocks. 917system.cpu.dcache.avg_refs 273.052089 # Average number of references to valid blocks. 918system.cpu.dcache.warmup_cycle 350225000 # Cycle when the warmup percentage was hit. 919system.cpu.dcache.occ_blocks::cpu.data 4069.477080 # Average occupied blocks per requestor 920system.cpu.dcache.occ_percent::cpu.data 0.993525 # Average percentage of cache occupancy 921system.cpu.dcache.occ_percent::total 0.993525 # Average percentage of cache occupancy 922system.cpu.dcache.ReadReq_hits::cpu.data 26048553 # number of ReadReq hits 923system.cpu.dcache.ReadReq_hits::total 26048553 # number of ReadReq hits 924system.cpu.dcache.WriteReq_hits::cpu.data 18266688 # number of WriteReq hits 925system.cpu.dcache.WriteReq_hits::total 18266688 # number of WriteReq hits 926system.cpu.dcache.LoadLockedReq_hits::cpu.data 15980 # number of LoadLockedReq hits 927system.cpu.dcache.LoadLockedReq_hits::total 15980 # number of LoadLockedReq hits |
| 760system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 761system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits | 928system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 929system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits |
| 762system.cpu.dcache.demand_hits::cpu.data 44312365 # number of demand (read+write) hits 763system.cpu.dcache.demand_hits::total 44312365 # number of demand (read+write) hits 764system.cpu.dcache.overall_hits::cpu.data 44312365 # number of overall hits 765system.cpu.dcache.overall_hits::total 44312365 # number of overall hits 766system.cpu.dcache.ReadReq_misses::cpu.data 124675 # number of ReadReq misses 767system.cpu.dcache.ReadReq_misses::total 124675 # number of ReadReq misses 768system.cpu.dcache.WriteReq_misses::cpu.data 1582846 # number of WriteReq misses 769system.cpu.dcache.WriteReq_misses::total 1582846 # number of WriteReq misses 770system.cpu.dcache.LoadLockedReq_misses::cpu.data 42 # number of LoadLockedReq misses 771system.cpu.dcache.LoadLockedReq_misses::total 42 # number of LoadLockedReq misses 772system.cpu.dcache.demand_misses::cpu.data 1707521 # number of demand (read+write) misses 773system.cpu.dcache.demand_misses::total 1707521 # number of demand (read+write) misses 774system.cpu.dcache.overall_misses::cpu.data 1707521 # number of overall misses 775system.cpu.dcache.overall_misses::total 1707521 # number of overall misses 776system.cpu.dcache.ReadReq_miss_latency::cpu.data 4257063500 # number of ReadReq miss cycles 777system.cpu.dcache.ReadReq_miss_latency::total 4257063500 # number of ReadReq miss cycles 778system.cpu.dcache.WriteReq_miss_latency::cpu.data 98390759981 # number of WriteReq miss cycles 779system.cpu.dcache.WriteReq_miss_latency::total 98390759981 # number of WriteReq miss cycles 780system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 860000 # number of LoadLockedReq miss cycles 781system.cpu.dcache.LoadLockedReq_miss_latency::total 860000 # number of LoadLockedReq miss cycles 782system.cpu.dcache.demand_miss_latency::cpu.data 102647823481 # number of demand (read+write) miss cycles 783system.cpu.dcache.demand_miss_latency::total 102647823481 # number of demand (read+write) miss cycles 784system.cpu.dcache.overall_miss_latency::cpu.data 102647823481 # number of overall miss cycles 785system.cpu.dcache.overall_miss_latency::total 102647823481 # number of overall miss cycles 786system.cpu.dcache.ReadReq_accesses::cpu.data 26169985 # number of ReadReq accesses(hits+misses) 787system.cpu.dcache.ReadReq_accesses::total 26169985 # number of ReadReq accesses(hits+misses) | 930system.cpu.dcache.demand_hits::cpu.data 44315241 # number of demand (read+write) hits 931system.cpu.dcache.demand_hits::total 44315241 # number of demand (read+write) hits 932system.cpu.dcache.overall_hits::cpu.data 44315241 # number of overall hits 933system.cpu.dcache.overall_hits::total 44315241 # number of overall hits 934system.cpu.dcache.ReadReq_misses::cpu.data 125407 # number of ReadReq misses 935system.cpu.dcache.ReadReq_misses::total 125407 # number of ReadReq misses 936system.cpu.dcache.WriteReq_misses::cpu.data 1583213 # number of WriteReq misses 937system.cpu.dcache.WriteReq_misses::total 1583213 # number of WriteReq misses 938system.cpu.dcache.LoadLockedReq_misses::cpu.data 44 # number of LoadLockedReq misses 939system.cpu.dcache.LoadLockedReq_misses::total 44 # number of LoadLockedReq misses 940system.cpu.dcache.demand_misses::cpu.data 1708620 # number of demand (read+write) misses 941system.cpu.dcache.demand_misses::total 1708620 # number of demand (read+write) misses 942system.cpu.dcache.overall_misses::cpu.data 1708620 # number of overall misses 943system.cpu.dcache.overall_misses::total 1708620 # number of overall misses 944system.cpu.dcache.ReadReq_miss_latency::cpu.data 5134620500 # number of ReadReq miss cycles 945system.cpu.dcache.ReadReq_miss_latency::total 5134620500 # number of ReadReq miss cycles 946system.cpu.dcache.WriteReq_miss_latency::cpu.data 123147327479 # number of WriteReq miss cycles 947system.cpu.dcache.WriteReq_miss_latency::total 123147327479 # number of WriteReq miss cycles 948system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 951500 # number of LoadLockedReq miss cycles 949system.cpu.dcache.LoadLockedReq_miss_latency::total 951500 # number of LoadLockedReq miss cycles 950system.cpu.dcache.demand_miss_latency::cpu.data 128281947979 # number of demand (read+write) miss cycles 951system.cpu.dcache.demand_miss_latency::total 128281947979 # number of demand (read+write) miss cycles 952system.cpu.dcache.overall_miss_latency::cpu.data 128281947979 # number of overall miss cycles 953system.cpu.dcache.overall_miss_latency::total 128281947979 # number of overall miss cycles 954system.cpu.dcache.ReadReq_accesses::cpu.data 26173960 # number of ReadReq accesses(hits+misses) 955system.cpu.dcache.ReadReq_accesses::total 26173960 # number of ReadReq accesses(hits+misses) |
| 788system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 789system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) | 956system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 957system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) |
| 790system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16027 # number of LoadLockedReq accesses(hits+misses) 791system.cpu.dcache.LoadLockedReq_accesses::total 16027 # number of LoadLockedReq accesses(hits+misses) | 958system.cpu.dcache.LoadLockedReq_accesses::cpu.data 16024 # number of LoadLockedReq accesses(hits+misses) 959system.cpu.dcache.LoadLockedReq_accesses::total 16024 # number of LoadLockedReq accesses(hits+misses) |
| 792system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 793system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) | 960system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 961system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) |
| 794system.cpu.dcache.demand_accesses::cpu.data 46019886 # number of demand (read+write) accesses 795system.cpu.dcache.demand_accesses::total 46019886 # number of demand (read+write) accesses 796system.cpu.dcache.overall_accesses::cpu.data 46019886 # number of overall (read+write) accesses 797system.cpu.dcache.overall_accesses::total 46019886 # number of overall (read+write) accesses 798system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004764 # miss rate for ReadReq accesses 799system.cpu.dcache.ReadReq_miss_rate::total 0.004764 # miss rate for ReadReq accesses 800system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079741 # miss rate for WriteReq accesses 801system.cpu.dcache.WriteReq_miss_rate::total 0.079741 # miss rate for WriteReq accesses 802system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002621 # miss rate for LoadLockedReq accesses 803system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002621 # miss rate for LoadLockedReq accesses 804system.cpu.dcache.demand_miss_rate::cpu.data 0.037104 # miss rate for demand accesses 805system.cpu.dcache.demand_miss_rate::total 0.037104 # miss rate for demand accesses 806system.cpu.dcache.overall_miss_rate::cpu.data 0.037104 # miss rate for overall accesses 807system.cpu.dcache.overall_miss_rate::total 0.037104 # miss rate for overall accesses 808system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34145.285743 # average ReadReq miss latency 809system.cpu.dcache.ReadReq_avg_miss_latency::total 34145.285743 # average ReadReq miss latency 810system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62160.665018 # average WriteReq miss latency 811system.cpu.dcache.WriteReq_avg_miss_latency::total 62160.665018 # average WriteReq miss latency 812system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 20476.190476 # average LoadLockedReq miss latency 813system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 20476.190476 # average LoadLockedReq miss latency 814system.cpu.dcache.demand_avg_miss_latency::cpu.data 60115.116289 # average overall miss latency 815system.cpu.dcache.demand_avg_miss_latency::total 60115.116289 # average overall miss latency 816system.cpu.dcache.overall_avg_miss_latency::cpu.data 60115.116289 # average overall miss latency 817system.cpu.dcache.overall_avg_miss_latency::total 60115.116289 # average overall miss latency 818system.cpu.dcache.blocked_cycles::no_mshrs 3743 # number of cycles access was blocked 819system.cpu.dcache.blocked_cycles::no_targets 661 # number of cycles access was blocked 820system.cpu.dcache.blocked::no_mshrs 131 # number of cycles access was blocked 821system.cpu.dcache.blocked::no_targets 15 # number of cycles access was blocked 822system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.572519 # average number of cycles each access was blocked 823system.cpu.dcache.avg_blocked_cycles::no_targets 44.066667 # average number of cycles each access was blocked | 962system.cpu.dcache.demand_accesses::cpu.data 46023861 # number of demand (read+write) accesses 963system.cpu.dcache.demand_accesses::total 46023861 # number of demand (read+write) accesses 964system.cpu.dcache.overall_accesses::cpu.data 46023861 # number of overall (read+write) accesses 965system.cpu.dcache.overall_accesses::total 46023861 # number of overall (read+write) accesses 966system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004791 # miss rate for ReadReq accesses 967system.cpu.dcache.ReadReq_miss_rate::total 0.004791 # miss rate for ReadReq accesses 968system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.079759 # miss rate for WriteReq accesses 969system.cpu.dcache.WriteReq_miss_rate::total 0.079759 # miss rate for WriteReq accesses 970system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002746 # miss rate for LoadLockedReq accesses 971system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002746 # miss rate for LoadLockedReq accesses 972system.cpu.dcache.demand_miss_rate::cpu.data 0.037125 # miss rate for demand accesses 973system.cpu.dcache.demand_miss_rate::total 0.037125 # miss rate for demand accesses 974system.cpu.dcache.overall_miss_rate::cpu.data 0.037125 # miss rate for overall accesses 975system.cpu.dcache.overall_miss_rate::total 0.037125 # miss rate for overall accesses 976system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 40943.651471 # average ReadReq miss latency 977system.cpu.dcache.ReadReq_avg_miss_latency::total 40943.651471 # average ReadReq miss latency 978system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 77783.170981 # average WriteReq miss latency 979system.cpu.dcache.WriteReq_avg_miss_latency::total 77783.170981 # average WriteReq miss latency 980system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 21625 # average LoadLockedReq miss latency 981system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 21625 # average LoadLockedReq miss latency 982system.cpu.dcache.demand_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency 983system.cpu.dcache.demand_avg_miss_latency::total 75079.273319 # average overall miss latency 984system.cpu.dcache.overall_avg_miss_latency::cpu.data 75079.273319 # average overall miss latency 985system.cpu.dcache.overall_avg_miss_latency::total 75079.273319 # average overall miss latency 986system.cpu.dcache.blocked_cycles::no_mshrs 5184 # number of cycles access was blocked 987system.cpu.dcache.blocked_cycles::no_targets 1288 # number of cycles access was blocked 988system.cpu.dcache.blocked::no_mshrs 145 # number of cycles access was blocked 989system.cpu.dcache.blocked::no_targets 16 # number of cycles access was blocked 990system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.751724 # average number of cycles each access was blocked 991system.cpu.dcache.avg_blocked_cycles::no_targets 80.500000 # average number of cycles each access was blocked |
| 824system.cpu.dcache.fast_writes 0 # number of fast writes performed 825system.cpu.dcache.cache_copies 0 # number of cache copies performed | 992system.cpu.dcache.fast_writes 0 # number of fast writes performed 993system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 826system.cpu.dcache.writebacks::writebacks 129075 # number of writebacks 827system.cpu.dcache.writebacks::total 129075 # number of writebacks 828system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69278 # number of ReadReq MSHR hits 829system.cpu.dcache.ReadReq_mshr_hits::total 69278 # number of ReadReq MSHR hits 830system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475504 # number of WriteReq MSHR hits 831system.cpu.dcache.WriteReq_mshr_hits::total 1475504 # number of WriteReq MSHR hits 832system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 42 # number of LoadLockedReq MSHR hits 833system.cpu.dcache.LoadLockedReq_mshr_hits::total 42 # number of LoadLockedReq MSHR hits 834system.cpu.dcache.demand_mshr_hits::cpu.data 1544782 # number of demand (read+write) MSHR hits 835system.cpu.dcache.demand_mshr_hits::total 1544782 # number of demand (read+write) MSHR hits 836system.cpu.dcache.overall_mshr_hits::cpu.data 1544782 # number of overall MSHR hits 837system.cpu.dcache.overall_mshr_hits::total 1544782 # number of overall MSHR hits 838system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55397 # number of ReadReq MSHR misses 839system.cpu.dcache.ReadReq_mshr_misses::total 55397 # number of ReadReq MSHR misses 840system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107342 # number of WriteReq MSHR misses 841system.cpu.dcache.WriteReq_mshr_misses::total 107342 # number of WriteReq MSHR misses 842system.cpu.dcache.demand_mshr_misses::cpu.data 162739 # number of demand (read+write) MSHR misses 843system.cpu.dcache.demand_mshr_misses::total 162739 # number of demand (read+write) MSHR misses 844system.cpu.dcache.overall_mshr_misses::cpu.data 162739 # number of overall MSHR misses 845system.cpu.dcache.overall_mshr_misses::total 162739 # number of overall MSHR misses 846system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1878555500 # number of ReadReq MSHR miss cycles 847system.cpu.dcache.ReadReq_mshr_miss_latency::total 1878555500 # number of ReadReq MSHR miss cycles 848system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6809217490 # number of WriteReq MSHR miss cycles 849system.cpu.dcache.WriteReq_mshr_miss_latency::total 6809217490 # number of WriteReq MSHR miss cycles 850system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8687772990 # number of demand (read+write) MSHR miss cycles 851system.cpu.dcache.demand_mshr_miss_latency::total 8687772990 # number of demand (read+write) MSHR miss cycles 852system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8687772990 # number of overall MSHR miss cycles 853system.cpu.dcache.overall_mshr_miss_latency::total 8687772990 # number of overall MSHR miss cycles | 994system.cpu.dcache.writebacks::writebacks 129077 # number of writebacks 995system.cpu.dcache.writebacks::total 129077 # number of writebacks 996system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69998 # number of ReadReq MSHR hits 997system.cpu.dcache.ReadReq_mshr_hits::total 69998 # number of ReadReq MSHR hits 998system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1475881 # number of WriteReq MSHR hits 999system.cpu.dcache.WriteReq_mshr_hits::total 1475881 # number of WriteReq MSHR hits 1000system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 44 # number of LoadLockedReq MSHR hits 1001system.cpu.dcache.LoadLockedReq_mshr_hits::total 44 # number of LoadLockedReq MSHR hits 1002system.cpu.dcache.demand_mshr_hits::cpu.data 1545879 # number of demand (read+write) MSHR hits 1003system.cpu.dcache.demand_mshr_hits::total 1545879 # number of demand (read+write) MSHR hits 1004system.cpu.dcache.overall_mshr_hits::cpu.data 1545879 # number of overall MSHR hits 1005system.cpu.dcache.overall_mshr_hits::total 1545879 # number of overall MSHR hits 1006system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55409 # number of ReadReq MSHR misses 1007system.cpu.dcache.ReadReq_mshr_misses::total 55409 # number of ReadReq MSHR misses 1008system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107332 # number of WriteReq MSHR misses 1009system.cpu.dcache.WriteReq_mshr_misses::total 107332 # number of WriteReq MSHR misses 1010system.cpu.dcache.demand_mshr_misses::cpu.data 162741 # number of demand (read+write) MSHR misses 1011system.cpu.dcache.demand_mshr_misses::total 162741 # number of demand (read+write) MSHR misses 1012system.cpu.dcache.overall_mshr_misses::cpu.data 162741 # number of overall MSHR misses 1013system.cpu.dcache.overall_mshr_misses::total 162741 # number of overall MSHR misses 1014system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2243387065 # number of ReadReq MSHR miss cycles 1015system.cpu.dcache.ReadReq_mshr_miss_latency::total 2243387065 # number of ReadReq MSHR miss cycles 1016system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8465944990 # number of WriteReq MSHR miss cycles 1017system.cpu.dcache.WriteReq_mshr_miss_latency::total 8465944990 # number of WriteReq MSHR miss cycles 1018system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10709332055 # number of demand (read+write) MSHR miss cycles 1019system.cpu.dcache.demand_mshr_miss_latency::total 10709332055 # number of demand (read+write) MSHR miss cycles 1020system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10709332055 # number of overall MSHR miss cycles 1021system.cpu.dcache.overall_mshr_miss_latency::total 10709332055 # number of overall MSHR miss cycles |
| 854system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses 855system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses | 1022system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002117 # mshr miss rate for ReadReq accesses 1023system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002117 # mshr miss rate for ReadReq accesses |
| 856system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005408 # mshr miss rate for WriteReq accesses 857system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005408 # mshr miss rate for WriteReq accesses | 1024system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005407 # mshr miss rate for WriteReq accesses 1025system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005407 # mshr miss rate for WriteReq accesses |
| 858system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses 859system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses 860system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses 861system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses | 1026system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for demand accesses 1027system.cpu.dcache.demand_mshr_miss_rate::total 0.003536 # mshr miss rate for demand accesses 1028system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003536 # mshr miss rate for overall accesses 1029system.cpu.dcache.overall_mshr_miss_rate::total 0.003536 # mshr miss rate for overall accesses |
| 862system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 33910.780367 # average ReadReq mshr miss latency 863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 33910.780367 # average ReadReq mshr miss latency 864system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63434.792439 # average WriteReq mshr miss latency 865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63434.792439 # average WriteReq mshr miss latency 866system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53384.701823 # average overall mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::total 53384.701823 # average overall mshr miss latency 868system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53384.701823 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::total 53384.701823 # average overall mshr miss latency | 1030system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 40487.773918 # average ReadReq mshr miss latency 1031system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 40487.773918 # average ReadReq mshr miss latency 1032system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78876.243711 # average WriteReq mshr miss latency 1033system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78876.243711 # average WriteReq mshr miss latency 1034system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency 1035system.cpu.dcache.demand_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency 1036system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65805.986537 # average overall mshr miss latency 1037system.cpu.dcache.overall_avg_mshr_miss_latency::total 65805.986537 # average overall mshr miss latency |
| 870system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 871 872---------- End Simulation Statistics ---------- | 1038system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1039 1040---------- End Simulation Statistics ---------- |